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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_wb_if.v                                                 ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/10/03 10:16:52  primozs
// support for configurable devider added
//
// Revision 1.6  2003/05/28 16:27:09  simons
// Change the address width.
//
// Revision 1.5  2002/04/09 13:24:11  mihad
// Added mouse interface and everything for its handling, cleaned up some unused code
//
// Revision 1.4  2002/02/20 16:35:43  mihad
// Little/big endian changes continued
//
// Revision 1.3  2002/02/20 15:20:10  mihad
// Little/big endian changes incorporated
//
// Revision 1.2  2002/02/18 18:07:55  mihad
// One bug fixed
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_wb_if
(
    wb_clk_i,
    wb_rst_i,
    wb_cyc_i,
    wb_stb_i,
    wb_we_i,
    wb_sel_i,
    wb_adr_i,
    wb_dat_i,
    wb_dat_o,
    wb_ack_o,
 
    wb_int_o,
 
    tx_kbd_write_ack_i,
    tx_kbd_data_o,
    tx_kbd_write_o,
    rx_scancode_i,
    rx_kbd_data_ready_i,
    rx_kbd_read_o,
    translate_o,
    ps2_kbd_clk_i,
    devide_reg_o,
    inhibit_kbd_if_o
    `ifdef PS2_AUX
    ,
    wb_intb_o,
 
    rx_aux_data_i,
    rx_aux_data_ready_i,
    rx_aux_read_o,
    tx_aux_data_o,
    tx_aux_write_o,
    tx_aux_write_ack_i,
    ps2_aux_clk_i,
    inhibit_aux_if_o
`endif
) ;
 
input wb_clk_i,
      wb_rst_i,
      wb_cyc_i,
      wb_stb_i,
      wb_we_i ;
 
input [3:0]  wb_sel_i ;
 
input [3:0]  wb_adr_i ;
 
input [31:0]  wb_dat_i ;
 
output [31:0] wb_dat_o ;
 
output wb_ack_o ;
 
reg wb_ack_o ;
 
output wb_int_o ;
reg    wb_int_o ;
 
input tx_kbd_write_ack_i ;
 
input [7:0] rx_scancode_i ;
input       rx_kbd_data_ready_i ;
output      rx_kbd_read_o ;
 
output      tx_kbd_write_o ;
output [7:0] tx_kbd_data_o ;
 
output translate_o ;
input  ps2_kbd_clk_i ;
 
output inhibit_kbd_if_o ;
 
reg [7:0] input_buffer,
          output_buffer ;
 
output [15:0] devide_reg_o;
reg    [15:0] devide_reg;
assign        devide_reg_o = devide_reg;
 
 
reg [15:0] wb_dat_i_sampled ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_i_sampled <= #1 0 ;
    else if ( wb_cyc_i && wb_stb_i && wb_we_i )
        wb_dat_i_sampled <= #1 wb_dat_i[31:16] ;
end
 
`ifdef PS2_AUX
output wb_intb_o ;
reg    wb_intb_o ;
 
input  [7:0]    rx_aux_data_i ;
input           rx_aux_data_ready_i ;
output          rx_aux_read_o ;
output [7:0]    tx_aux_data_o ;
output          tx_aux_write_o ;
input           tx_aux_write_ack_i ;
input           ps2_aux_clk_i ;
output          inhibit_aux_if_o ;
reg             inhibit_aux_if_o ;
reg             aux_output_buffer_full ;
reg             aux_input_buffer_full ;
reg             interrupt2 ;
reg             enable2    ;
assign          tx_aux_data_o  = output_buffer ;
assign          tx_aux_write_o = aux_output_buffer_full ;
`else
wire aux_input_buffer_full  = 1'b0 ;
wire aux_output_buffer_full = 1'b0 ;
wire interrupt2             = 1'b0 ;
wire enable2                = 1'b1 ;
`endif
 
assign tx_kbd_data_o = output_buffer ;
 
reg input_buffer_full,   // receive buffer
    output_buffer_full ; // transmit buffer
 
assign tx_kbd_write_o = output_buffer_full ;
 
wire system_flag ;
wire a2                       = 1'b0 ;
wire kbd_inhibit              = ps2_kbd_clk_i ;
wire timeout                  = 1'b0 ;
wire perr                     = 1'b0 ;
 
wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full || aux_output_buffer_full, input_buffer_full} ;
 
reg  read_input_buffer_reg ;
wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h0) ;
 
reg  write_output_buffer_reg ;
wire write_output_buffer  = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i  && (wb_adr_i[3:0] == 4'h0) ;
 
reg  read_status_register_reg ;
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h4) ;
 
reg  send_command_reg ;
wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i  && (wb_adr_i[3:0] == 4'h4) ;
 
reg  write_devide_reg0 ;
wire write_devide0 = wb_cyc_i && wb_stb_i && wb_sel_i[2] && !wb_ack_o && !write_devide_reg0 && wb_we_i  && (wb_adr_i[3:0] == 4'h8) ;
 
//reg  read_devide_reg ;
wire read_devide = wb_cyc_i && wb_stb_i &&  ( wb_sel_i[2]|| wb_sel_i [3] ) && !wb_we_i  && (wb_adr_i[3:0] == 4'h8) ;
 
reg  write_devide_reg1 ;
wire write_devide1 = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_devide_reg1 && wb_we_i  && (wb_adr_i[3:0] == 4'h8) ;
 
 
reg  translate_o,
     enable1,
     system,
     interrupt1 ;
 
reg inhibit_kbd_if_o ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_kbd_if_o <= #1 1'b0 ;
    else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)
        inhibit_kbd_if_o <= #1 1'b1 ;
    else if ( !rx_kbd_data_ready_i || enable1 )
        inhibit_kbd_if_o <= #1 1'b0 ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( !rx_aux_data_ready_i || enable2 )
        inhibit_aux_if_o <= #1 1'b0 ;
 
end
`endif
 
assign system_flag = system ;
 
wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;
 
reg [7:0] current_command ;
reg [7:0] current_command_output ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        send_command_reg         <= #1 1'b0 ;
        read_input_buffer_reg    <= #1 1'b0 ;
        write_output_buffer_reg  <= #1 1'b0 ;
        read_status_register_reg <= #1 1'b0 ;
        write_devide_reg0        <= #1 1'b0 ;
        //read_devide_reg          <= #1 1'b0 ;
        write_devide_reg1        <= #1 1'b0 ;
   end
    else
    begin
        send_command_reg         <= #1 send_command ;
        read_input_buffer_reg    <= #1 read_input_buffer ;
        write_output_buffer_reg  <= #1 write_output_buffer ;
        read_status_register_reg <= #1 read_status_register ;
        write_devide_reg0        <= #1 write_devide0 ;
        //read_devide_reg          <= #1 read_devide ;
        write_devide_reg1        <= #1 write_devide1 ;
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command <= #1 8'h0 ;
    else if ( send_command_reg )
        current_command <= #1 wb_dat_i_sampled[15:8] ;
end
 
reg current_command_valid,
    current_command_returns_value,
    current_command_gets_parameter,
    current_command_gets_null_terminated_string ;
 
reg write_output_buffer_reg_previous ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        write_output_buffer_reg_previous <= #1 1'b0 ;
    else
        write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;
end
 
wire invalidate_current_command =
     current_command_valid &&
     (( current_command_returns_value && read_input_buffer_reg && input_buffer_full) ||
      ( current_command_gets_parameter && write_output_buffer_reg_previous ) ||
      ( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) ||
      ( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )
     ) ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command_valid <= #1 1'b0 ;
    else if ( invalidate_current_command )
        current_command_valid <= #1 1'b0 ;
    else if ( send_command_reg )
        current_command_valid <= #1 1'b1 ;
 
end
 
reg write_command_byte ;
reg current_command_output_valid ;
always@(
    current_command or
    command_byte or
    write_output_buffer_reg_previous or
    current_command_valid or
    output_buffer
)
begin
    current_command_returns_value               = 1'b0 ;
    current_command_gets_parameter              = 1'b0 ;
    current_command_gets_null_terminated_string = 1'b0 ;
    current_command_output                      = 8'h00 ;
    write_command_byte                          = 1'b0 ;
    current_command_output_valid                = 1'b0 ;
    case(current_command)
        8'h20:begin
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = command_byte ;
                  current_command_output_valid   = 1'b1 ;
              end
        8'h60:begin
                  current_command_gets_parameter = 1'b1 ;
                  write_command_byte             = write_output_buffer_reg_previous && current_command_valid ;
              end
        8'hA1:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA4:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hF1 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA5:begin
                  current_command_gets_null_terminated_string = 1'b1 ;
              end
        8'hA6:begin
              end
        8'hA7:begin
              end
        8'hA8:begin
              end
        8'hA9:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output_valid  = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_output        = 8'h00 ;  // interface OK
                  `else
                  current_command_output        = 8'h02 ; // clock line stuck high
                  `endif
              end
        8'hAA:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h55 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAB:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAD:begin
              end
        8'hAE:begin
              end
        8'hAF:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC1:begin
              end
        8'hC2:begin
              end
        8'hD0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h01 ; // only system reset bit is 1
                  current_command_output_valid  = 1'b1 ;
              end
        8'hD1:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hD2:begin
                  current_command_returns_value   = 1'b1 ;
                  current_command_gets_parameter  = 1'b1 ;
                  current_command_output          = output_buffer ;
                  current_command_output_valid    = write_output_buffer_reg_previous ;
              end
        8'hD3:begin
                  current_command_gets_parameter = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = output_buffer ;
                  current_command_output_valid   = write_output_buffer_reg_previous ;
                  `endif
              end
        8'hD4:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hE0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
    endcase
end
 
reg cyc_i_previous ;
reg stb_i_previous ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else if ( wb_ack_o )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else
    begin
        cyc_i_previous <= #1 wb_cyc_i ;
        stb_i_previous <= #1 wb_stb_i ;
    end
 
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_ack_o <= #1 1'b0 ;
    else if ( wb_ack_o )
        wb_ack_o <= #1 1'b0 ;
    else
        wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
end
 
reg [31:0] wb_dat_o ;
wire wb_read = read_input_buffer_reg || read_status_register_reg || read_devide ;
 
wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide ? devide_reg : {2{input_buffer}} ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_o <= #1 32'h0 ;
    else if ( wb_read )
        wb_dat_o <= #1 {2{output_data}} ;
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer_full <= #1 1'b0 ;
    else if ( output_buffer_full && tx_kbd_write_ack_i || enable1)
        output_buffer_full <= #1 1'b0 ;
    else
        output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid || (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_output_buffer_full <= #1 1'b0 ;
    else if ( aux_output_buffer_full && tx_aux_write_ack_i || enable2)
        aux_output_buffer_full <= #1 1'b0 ;
    else
        aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;
end
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer <= #1 8'h00 ;
    else if ( write_output_buffer_reg )
        output_buffer <= #1 wb_dat_i_sampled[15:8];
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        devide_reg <= #1 8'h00 ;
    else
      begin
      if ( write_devide_reg0 )
        devide_reg[7:0] <= #1 wb_dat_i_sampled[7:0] ;
      if ( write_devide_reg1 )
        devide_reg[15:8] <= #1 wb_dat_i_sampled[15:8] ;
      end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        translate_o <= #1 1'b0 ;
        system      <= #1 1'b0 ;
        interrupt1  <= #1 1'b0 ;
        `ifdef PS2_AUX
        interrupt2  <= #1 1'b0 ;
        `endif
    end
    else if ( write_command_byte )
    begin
        translate_o <= #1 output_buffer[6] ;
        system      <= #1 output_buffer[2] ;
        interrupt1  <= #1 output_buffer[0] ;
        `ifdef PS2_AUX
        interrupt2  <= #1 output_buffer[1] ;
        `endif
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable1 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hAE) )
        enable1 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hAD) )
        enable1 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable1 <= #1 output_buffer[4] ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable2 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hA8) )
        enable2 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hA7) )
        enable2 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable2 <= #1 output_buffer[5] ;
 
end
`endif
 
wire write_input_buffer_from_command = current_command_valid && current_command_returns_value && current_command_output_valid ;
wire write_input_buffer_from_kbd     = !input_buffer_full && rx_kbd_data_ready_i && !enable1 && !current_command_valid ;
 
`ifdef PS2_AUX
wire write_input_buffer_from_aux     = !input_buffer_full && rx_aux_data_ready_i && !enable2 && !current_command_valid && !write_input_buffer_from_kbd ;
`endif
 
wire load_input_buffer_value =
    write_input_buffer_from_command
    ||
    write_input_buffer_from_kbd
    `ifdef PS2_AUX
    ||
    write_input_buffer_from_aux
    `endif
    ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_full <= #1 1'b0 ;
    else if ( load_input_buffer_value )
        input_buffer_full <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( write_input_buffer_from_aux || (write_input_buffer_from_command && (current_command == 8'hD3)) )
        aux_input_buffer_full <= #1 1'b1 ;
end
`endif
 
reg input_buffer_filled_from_command ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( write_input_buffer_from_command )
        input_buffer_filled_from_command <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
reg [7:0] value_to_load_in_input_buffer ;
always@
(
    write_input_buffer_from_command
    or
    current_command_output
    or
    rx_scancode_i
    or
    write_input_buffer_from_kbd
    or
    rx_aux_data_i
)
begin
    case ({write_input_buffer_from_command, write_input_buffer_from_kbd})
        2'b10,
        2'b11   :   value_to_load_in_input_buffer = current_command_output ;
        2'b01   :   value_to_load_in_input_buffer = rx_scancode_i ;
        2'b00   :   value_to_load_in_input_buffer = rx_aux_data_i ;
    endcase
end
 
`else
wire [7:0] value_to_load_in_input_buffer = write_input_buffer_from_command ? current_command_output : rx_scancode_i ;
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer <= #1 8'h00 ;
    else if ( load_input_buffer_value )
        input_buffer <= #1 value_to_load_in_input_buffer ;
end
 
assign rx_kbd_read_o = rx_kbd_data_ready_i &&
                       ( enable1
                         ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                           `ifdef PS2_AUX
                           &&
                           !aux_input_buffer_full
                           `endif
                          )
                        );
 
`ifdef PS2_AUX
assign rx_aux_read_o = rx_aux_data_ready_i &&
                       ( enable2 ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           aux_input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                          )
                        );
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_int_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable1 || !interrupt1)
        wb_int_o <= #1 1'b0 ;
    else
        wb_int_o <= #1 input_buffer_full
                       `ifdef PS2_AUX
                       &&
                       !aux_input_buffer_full
                       `endif
                       ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_intb_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable2 || !interrupt2)
        wb_intb_o <= #1 1'b0 ;
    else
        wb_intb_o <= #1 input_buffer_full
                       &&
                       aux_input_buffer_full
                       ;
end
`endif
 
endmodule // ps2_wb_if

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_wb_if.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	27	gorand	`// Revision 1.7 2003/10/03 10:16:52 primozs`
47			`// support for configurable devider added`
48			`//`
49	24	primozs	`// Revision 1.6 2003/05/28 16:27:09 simons`
50			`// Change the address width.`
51			`//`
52	15	simons	`// Revision 1.5 2002/04/09 13:24:11 mihad`
53			`// Added mouse interface and everything for its handling, cleaned up some unused code`
54			`//`
55	13	mihad	`// Revision 1.4 2002/02/20 16:35:43 mihad`
56			`// Little/big endian changes continued`
57			`//`
58	7	mihad	`// Revision 1.3 2002/02/20 15:20:10 mihad`
59			`// Little/big endian changes incorporated`
60			`//`
61	6	mihad	`// Revision 1.2 2002/02/18 18:07:55 mihad`
62			`// One bug fixed`
63			`//`
64	5	mihad	`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
65			`// Initial project import - working`
66	2	mihad	`//`
67	5	mihad	`//`
68	2	mihad
69			`// synopsys translate_off`
70			`include "timescale.v"
71			`// synopsys translate_on`
72
73			`module ps2_wb_if`
74			`(`
75			`wb_clk_i,`
76			`wb_rst_i,`
77			`wb_cyc_i,`
78			`wb_stb_i,`
79			`wb_we_i,`
80			`wb_sel_i,`
81			`wb_adr_i,`
82			`wb_dat_i,`
83			`wb_dat_o,`
84			`wb_ack_o,`
85	13	mihad
86	2	mihad	`wb_int_o,`
87
88	13	mihad	`tx_kbd_write_ack_i,`
89			`tx_kbd_data_o,`
90			`tx_kbd_write_o,`
91	2	mihad	`rx_scancode_i,`
92	13	mihad	`rx_kbd_data_ready_i,`
93			`rx_kbd_read_o,`
94	2	mihad	`translate_o,`
95	13	mihad	`ps2_kbd_clk_i,`
96	24	primozs	`devide_reg_o,`
97	2	mihad	`inhibit_kbd_if_o`
98	13	mihad	`ifdef PS2_AUX
99			`,`
100			`wb_intb_o,`
101
102			`rx_aux_data_i,`
103			`rx_aux_data_ready_i,`
104			`rx_aux_read_o,`
105			`tx_aux_data_o,`
106			`tx_aux_write_o,`
107			`tx_aux_write_ack_i,`
108			`ps2_aux_clk_i,`
109			`inhibit_aux_if_o`
110			`endif
111	2	mihad	`) ;`
112
113			`input wb_clk_i,`
114			`wb_rst_i,`
115			`wb_cyc_i,`
116			`wb_stb_i,`
117			`wb_we_i ;`
118
119			`input [3:0] wb_sel_i ;`
120
121	24	primozs	`input [3:0] wb_adr_i ;`
122	2	mihad
123			`input [31:0] wb_dat_i ;`
124
125			`output [31:0] wb_dat_o ;`
126
127			`output wb_ack_o ;`
128
129			`reg wb_ack_o ;`
130
131			`output wb_int_o ;`
132			`reg wb_int_o ;`
133
134	13	mihad	`input tx_kbd_write_ack_i ;`
135	2	mihad
136			`input [7:0] rx_scancode_i ;`
137	13	mihad	`input rx_kbd_data_ready_i ;`
138			`output rx_kbd_read_o ;`
139	2	mihad
140	13	mihad	`output tx_kbd_write_o ;`
141			`output [7:0] tx_kbd_data_o ;`
142	2	mihad
143			`output translate_o ;`
144	13	mihad	`input ps2_kbd_clk_i ;`
145	2	mihad
146			`output inhibit_kbd_if_o ;`
147
148			`reg [7:0] input_buffer,`
149			`output_buffer ;`
150
151	24	primozs	`output [15:0] devide_reg_o;`
152			`reg [15:0] devide_reg;`
153			`assign devide_reg_o = devide_reg;`
154
155
156			`reg [15:0] wb_dat_i_sampled ;`
157	13	mihad	`always@(posedge wb_clk_i or posedge wb_rst_i)`
158			`begin`
159			`if ( wb_rst_i )`
160			`wb_dat_i_sampled <= #1 0 ;`
161			`else if ( wb_cyc_i && wb_stb_i && wb_we_i )`
162	24	primozs	`wb_dat_i_sampled <= #1 wb_dat_i[31:16] ;`
163	13	mihad	`end`
164	2	mihad
165	13	mihad	`ifdef PS2_AUX
166			`output wb_intb_o ;`
167			`reg wb_intb_o ;`
168
169			`input [7:0] rx_aux_data_i ;`
170			`input rx_aux_data_ready_i ;`
171			`output rx_aux_read_o ;`
172			`output [7:0] tx_aux_data_o ;`
173			`output tx_aux_write_o ;`
174			`input tx_aux_write_ack_i ;`
175			`input ps2_aux_clk_i ;`
176			`output inhibit_aux_if_o ;`
177			`reg inhibit_aux_if_o ;`
178			`reg aux_output_buffer_full ;`
179			`reg aux_input_buffer_full ;`
180			`reg interrupt2 ;`
181			`reg enable2 ;`
182			`assign tx_aux_data_o = output_buffer ;`
183			`assign tx_aux_write_o = aux_output_buffer_full ;`
184			`else
185			`wire aux_input_buffer_full = 1'b0 ;`
186			`wire aux_output_buffer_full = 1'b0 ;`
187			`wire interrupt2 = 1'b0 ;`
188			`wire enable2 = 1'b1 ;`
189			`endif
190
191			`assign tx_kbd_data_o = output_buffer ;`
192
193	2	mihad	`reg input_buffer_full, // receive buffer`
194			`output_buffer_full ; // transmit buffer`
195
196	13	mihad	`assign tx_kbd_write_o = output_buffer_full ;`
197	2	mihad
198			`wire system_flag ;`
199			`wire a2 = 1'b0 ;`
200	13	mihad	`wire kbd_inhibit = ps2_kbd_clk_i ;`
201	2	mihad	`wire timeout = 1'b0 ;`
202			`wire perr = 1'b0 ;`
203
204	13	mihad	`wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full \|\| aux_output_buffer_full, input_buffer_full} ;`
205	2	mihad
206			`reg read_input_buffer_reg ;`
207	24	primozs	`wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h0) ;`
208	2	mihad
209			`reg write_output_buffer_reg ;`
210	24	primozs	`wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[3:0] == 4'h0) ;`
211	2	mihad
212			`reg read_status_register_reg ;`
213	24	primozs	`wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[3:0] == 4'h4) ;`
214	2	mihad
215			`reg send_command_reg ;`
216	24	primozs	`wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[3:0] == 4'h4) ;`
217	2	mihad
218	27	gorand	`reg write_devide_reg0 ;`
219			`wire write_devide0 = wb_cyc_i && wb_stb_i && wb_sel_i[2] && !wb_ack_o && !write_devide_reg0 && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;`
220	24	primozs
221	27	gorand	`//reg read_devide_reg ;`
222			`wire read_devide = wb_cyc_i && wb_stb_i && ( wb_sel_i[2]\|\| wb_sel_i [3] ) && !wb_we_i && (wb_adr_i[3:0] == 4'h8) ;`
223
224			`reg write_devide_reg1 ;`
225			`wire write_devide1 = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_devide_reg1 && wb_we_i && (wb_adr_i[3:0] == 4'h8) ;`
226
227
228	2	mihad	`reg translate_o,`
229			`enable1,`
230			`system,`
231			`interrupt1 ;`
232
233			`reg inhibit_kbd_if_o ;`
234			`always@(posedge wb_clk_i or posedge wb_rst_i)`
235			`begin`
236			`if ( wb_rst_i )`
237	24	primozs	`inhibit_kbd_if_o <= #1 1'b0 ;`
238	13	mihad	`else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)`
239	2	mihad	`inhibit_kbd_if_o <= #1 1'b1 ;`
240	13	mihad	`else if ( !rx_kbd_data_ready_i \|\| enable1 )`
241	2	mihad	`inhibit_kbd_if_o <= #1 1'b0 ;`
242	13	mihad
243	2	mihad	`end`
244
245	13	mihad	`ifdef PS2_AUX
246			`always@(posedge wb_clk_i or posedge wb_rst_i)`
247			`begin`
248			`if ( wb_rst_i )`
249			`inhibit_aux_if_o <= #1 1'b1 ;`
250			`else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )`
251			`inhibit_aux_if_o <= #1 1'b1 ;`
252			`else if ( !rx_aux_data_ready_i \|\| enable2 )`
253			`inhibit_aux_if_o <= #1 1'b0 ;`
254	2	mihad
255	13	mihad	`end`
256			`endif
257
258	2	mihad	`assign system_flag = system ;`
259
260			`wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;`
261
262			`reg [7:0] current_command ;`
263			`reg [7:0] current_command_output ;`
264
265			`always@(posedge wb_clk_i or posedge wb_rst_i)`
266			`begin`
267			`if ( wb_rst_i )`
268			`begin`
269			`send_command_reg <= #1 1'b0 ;`
270			`read_input_buffer_reg <= #1 1'b0 ;`
271			`write_output_buffer_reg <= #1 1'b0 ;`
272			`read_status_register_reg <= #1 1'b0 ;`
273	27	gorand	`write_devide_reg0 <= #1 1'b0 ;`
274			`//read_devide_reg <= #1 1'b0 ;`
275			`write_devide_reg1 <= #1 1'b0 ;`
276			`end`
277	2	mihad	`else`
278			`begin`
279			`send_command_reg <= #1 send_command ;`
280			`read_input_buffer_reg <= #1 read_input_buffer ;`
281			`write_output_buffer_reg <= #1 write_output_buffer ;`
282			`read_status_register_reg <= #1 read_status_register ;`
283	27	gorand	`write_devide_reg0 <= #1 write_devide0 ;`
284			`//read_devide_reg <= #1 read_devide ;`
285			`write_devide_reg1 <= #1 write_devide1 ;`
286	2	mihad	`end`
287			`end`
288
289			`always@(posedge wb_clk_i or posedge wb_rst_i)`
290			`begin`
291			`if ( wb_rst_i )`
292			`current_command <= #1 8'h0 ;`
293			`else if ( send_command_reg )`
294	24	primozs	`current_command <= #1 wb_dat_i_sampled[15:8] ;`
295	2	mihad	`end`
296
297			`reg current_command_valid,`
298			`current_command_returns_value,`
299			`current_command_gets_parameter,`
300			`current_command_gets_null_terminated_string ;`
301
302			`reg write_output_buffer_reg_previous ;`
303			`always@(posedge wb_clk_i or posedge wb_rst_i)`
304			`begin`
305			`if ( wb_rst_i )`
306			`write_output_buffer_reg_previous <= #1 1'b0 ;`
307			`else`
308			`write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;`
309			`end`
310
311	13	mihad	`wire invalidate_current_command =`
312			`current_command_valid &&`
313	2	mihad	`(( current_command_returns_value && read_input_buffer_reg && input_buffer_full) \|\|`
314			`( current_command_gets_parameter && write_output_buffer_reg_previous ) \|\|`
315			`( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) \|\|`
316			`( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )`
317			`) ;`
318
319			`always@(posedge wb_clk_i or posedge wb_rst_i)`
320			`begin`
321			`if ( wb_rst_i )`
322			`current_command_valid <= #1 1'b0 ;`
323			`else if ( invalidate_current_command )`
324			`current_command_valid <= #1 1'b0 ;`
325			`else if ( send_command_reg )`
326			`current_command_valid <= #1 1'b1 ;`
327	13	mihad
328	2	mihad	`end`
329
330			`reg write_command_byte ;`
331			`reg current_command_output_valid ;`
332			`always@(`
333			`current_command or`
334			`command_byte or`
335	13	mihad	`write_output_buffer_reg_previous or`
336	2	mihad	`current_command_valid or`
337			`output_buffer`
338			`)`
339			`begin`
340			`current_command_returns_value = 1'b0 ;`
341			`current_command_gets_parameter = 1'b0 ;`
342			`current_command_gets_null_terminated_string = 1'b0 ;`
343			`current_command_output = 8'h00 ;`
344			`write_command_byte = 1'b0 ;`
345			`current_command_output_valid = 1'b0 ;`
346			`case(current_command)`
347			`8'h20:begin`
348			`current_command_returns_value = 1'b1 ;`
349			`current_command_output = command_byte ;`
350			`current_command_output_valid = 1'b1 ;`
351			`end`
352			`8'h60:begin`
353			`current_command_gets_parameter = 1'b1 ;`
354			`write_command_byte = write_output_buffer_reg_previous && current_command_valid ;`
355			`end`
356			`8'hA1:begin`
357			`current_command_returns_value = 1'b1 ;`
358			`current_command_output = 8'h00 ;`
359			`current_command_output_valid = 1'b1 ;`
360	13	mihad	`end`
361	2	mihad	`8'hA4:begin`
362			`current_command_returns_value = 1'b1 ;`
363			`current_command_output = 8'hF1 ;`
364			`current_command_output_valid = 1'b1 ;`
365			`end`
366			`8'hA5:begin`
367			`current_command_gets_null_terminated_string = 1'b1 ;`
368			`end`
369			`8'hA6:begin`
370			`end`
371			`8'hA7:begin`
372	13	mihad	`end`
373	2	mihad	`8'hA8:begin`
374			`end`
375			`8'hA9:begin`
376			`current_command_returns_value = 1'b1 ;`
377	13	mihad	`current_command_output_valid = 1'b1 ;`
378			`ifdef PS2_AUX
379			`current_command_output = 8'h00 ; // interface OK`
380			`else
381	2	mihad	`current_command_output = 8'h02 ; // clock line stuck high`
382	13	mihad	`endif
383	2	mihad	`end`
384			`8'hAA:begin`
385			`current_command_returns_value = 1'b1 ;`
386			`current_command_output = 8'h55 ;`
387			`current_command_output_valid = 1'b1 ;`
388			`end`
389			`8'hAB:begin`
390			`current_command_returns_value = 1'b1 ;`
391			`current_command_output = 8'h00 ;`
392			`current_command_output_valid = 1'b1 ;`
393			`end`
394			`8'hAD:begin`
395	13	mihad	`end`
396	2	mihad	`8'hAE:begin`
397			`end`
398			`8'hAF:begin`
399			`current_command_returns_value = 1'b1 ;`
400			`current_command_output = 8'h00 ;`
401			`current_command_output_valid = 1'b1 ;`
402			`end`
403	13	mihad	`8'hC0:begin`
404	2	mihad	`current_command_returns_value = 1'b1 ;`
405			`current_command_output = 8'hFF ;`
406			`current_command_output_valid = 1'b1 ;`
407			`end`
408			`8'hC1:begin`
409			`end`
410			`8'hC2:begin`
411			`end`
412			`8'hD0:begin`
413			`current_command_returns_value = 1'b1 ;`
414			`current_command_output = 8'h01 ; // only system reset bit is 1`
415			`current_command_output_valid = 1'b1 ;`
416			`end`
417			`8'hD1:begin`
418			`current_command_gets_parameter = 1'b1 ;`
419			`end`
420			`8'hD2:begin`
421	5	mihad	`current_command_returns_value = 1'b1 ;`
422	2	mihad	`current_command_gets_parameter = 1'b1 ;`
423			`current_command_output = output_buffer ;`
424			`current_command_output_valid = write_output_buffer_reg_previous ;`
425			`end`
426			`8'hD3:begin`
427			`current_command_gets_parameter = 1'b1 ;`
428	13	mihad	`ifdef PS2_AUX
429			`current_command_returns_value = 1'b1 ;`
430			`current_command_output = output_buffer ;`
431			`current_command_output_valid = write_output_buffer_reg_previous ;`
432			`endif
433	2	mihad	`end`
434			`8'hD4:begin`
435			`current_command_gets_parameter = 1'b1 ;`
436			`end`
437			`8'hE0:begin`
438			`current_command_returns_value = 1'b1 ;`
439			`current_command_output = 8'hFF ;`
440			`current_command_output_valid = 1'b1 ;`
441			`end`
442	13	mihad	`endcase`
443	2	mihad	`end`
444
445			`reg cyc_i_previous ;`
446			`reg stb_i_previous ;`
447
448			`always@(posedge wb_clk_i or posedge wb_rst_i)`
449			`begin`
450			`if ( wb_rst_i )`
451			`begin`
452			`cyc_i_previous <= #1 1'b0 ;`
453			`stb_i_previous <= #1 1'b0 ;`
454			`end`
455			`else if ( wb_ack_o )`
456			`begin`
457			`cyc_i_previous <= #1 1'b0 ;`
458			`stb_i_previous <= #1 1'b0 ;`
459			`end`
460			`else`
461			`begin`
462			`cyc_i_previous <= #1 wb_cyc_i ;`
463			`stb_i_previous <= #1 wb_stb_i ;`
464			`end`
465	13	mihad
466	2	mihad	`end`
467
468			`always@(posedge wb_clk_i or posedge wb_rst_i)`
469			`begin`
470			`if ( wb_rst_i )`
471			`wb_ack_o <= #1 1'b0 ;`
472			`else if ( wb_ack_o )`
473			`wb_ack_o <= #1 1'b0 ;`
474			`else`
475			`wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;`
476			`end`
477
478			`reg [31:0] wb_dat_o ;`
479	27	gorand	`wire wb_read = read_input_buffer_reg \|\| read_status_register_reg \|\| read_devide ;`
480	2	mihad
481	27	gorand	`wire [15:0] output_data = read_status_register_reg ? {2{status_byte}} : read_devide ? devide_reg : {2{input_buffer}} ;`
482	2	mihad	`always@(posedge wb_clk_i or posedge wb_rst_i)`
483			`begin`
484			`if ( wb_rst_i )`
485			`wb_dat_o <= #1 32'h0 ;`
486			`else if ( wb_read )`
487	24	primozs	`wb_dat_o <= #1 {2{output_data}} ;`
488	2	mihad	`end`
489
490			`always@(posedge wb_clk_i or posedge wb_rst_i)`
491			`begin`
492			`if ( wb_rst_i )`
493			`output_buffer_full <= #1 1'b0 ;`
494	13	mihad	`else if ( output_buffer_full && tx_kbd_write_ack_i \|\| enable1)`
495			`output_buffer_full <= #1 1'b0 ;`
496			`else`
497	2	mihad	`output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid \|\| (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;`
498			`end`
499
500	13	mihad	`ifdef PS2_AUX

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[/] [ps2/] [tags/] [rel_14/] [rtl/] [verilog/] [ps2_wb_if.v] - Blame information for rev 51