URL https://opencores.org/ocsvn/ps2/ps2/trunk

Subversion Repositories ps2

[/] [ps2/] [tags/] [rel_2/] [rtl/] [verilog/] [ps2_translation_table.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_translation_table.v                                     ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "ps2_defines.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_translation_table
(
    reset_i,
    clock_i,
    translate_i,
    code_i,
    code_o,
    address_i,
    data_i,
    we_i,
    re_i,
    data_o,
    rx_data_ready_i,
    rx_translated_data_ready_o,
    rx_read_i,
    rx_read_o,
    rx_extended_i,
    rx_released_i
) ;
 
input reset_i,
      clock_i,
      translate_i ;
 
input  [7:0] code_i ;
output [7:0] code_o ;
input  [7:0] address_i ;
input  [7:0] data_i ;
input        we_i,
             re_i ;
 
output [7:0] data_o ;
 
input rx_data_ready_i,
      rx_read_i ;
 
output rx_translated_data_ready_o ;
output rx_read_o ;
 
input  rx_extended_i,
       rx_released_i ;
 
wire translation_table_write_enable  = we_i && (!translate_i || !rx_data_ready_i) ;
wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
wire translation_table_enable        = we_i || re_i || (translate_i && rx_data_ready_i) ;
 
reg rx_translated_data_ready ;
always@(posedge clock_i or posedge reset_i)
begin
    if ( reset_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else if ( rx_read_i || !translate_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else
        rx_translated_data_ready <= #1 rx_data_ready_i ;
end
 
`ifdef PS2_RAMB4
    `define PS2_RAM_SELECTED
 
    wire [7:0] ram_out ;
    RAMB4_S8 `ifdef SIM
             #("ignore",
               `PS2_TRANSLATION_TABLE_31_0,
               `PS2_TRANSLATION_TABLE_63_32,
               `PS2_TRANSLATION_TABLE_95_64,
               `PS2_TRANSLATION_TABLE_127_96,
               `PS2_TRANSLATION_TABLE_159_128,
               `PS2_TRANSLATION_TABLE_191_160,
               `PS2_TRANSLATION_TABLE_223_192,
               `PS2_TRANSLATION_TABLE_255_224)
              `endif
    ps2_ram
    (
        .DO   (ram_out),
        .ADDR ({1'b0, translation_table_address}),
        .DI   (data_i),
        .EN   (translation_table_enable),
        .CLK  (clock_i),
        .WE   (translation_table_write_enable),
        .RST  (reset_i)
    ) ;
 
`endif
 
`ifdef PS2_RAM_SELECTED
`else
    `define PS2_RAM_SELECTED
 
    reg [7:0] ps2_ram [0:255] ;
    reg [7:0] ram_out ;
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
            ram_out <= #1 ps2_ram[translation_table_address] ;
    end
 
    always@(posedge clock_i)
    begin
        if ( translation_table_write_enable )
            ps2_ram[translation_table_address] <= #1 data_i ;
    end
 
    // synopsys translate_off
    integer i ;
    reg [255:0] temp_init_val ;
    initial
    begin
        temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
 
        for ( i = 0 ; i <= 31 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
 
        for ( i = 32 ; i <= 63 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
 
        for ( i = 64 ; i <= 95 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
 
        for ( i = 96 ; i <= 127 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
 
        for ( i = 128 ; i <= 159 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
 
        for ( i = 160 ; i <= 191 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
 
        for ( i = 192 ; i <= 223 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
 
        for ( i = 224 ; i <= 255 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
    end
 
    // synopsys translate_on
 
`endif
 
assign data_o = ram_out ;
assign code_o = translate_i ? {(rx_released_i | ram_out[7]), ram_out[6:0]} : code_i ;
assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;
assign rx_read_o = rx_read_i ;
 
`undef PS2_RAM_SELECTED
 
endmodule //ps2_translation_table

Browse

Tools

Subversion Repositories ps2

[/] [ps2/] [tags/] [rel_2/] [rtl/] [verilog/] [ps2_translation_table.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_translation_table.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`//`
47
48			`include "ps2_defines.v"
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53
54			`module ps2_translation_table`
55			`(`
56			`reset_i,`
57			`clock_i,`
58			`translate_i,`
59			`code_i,`
60			`code_o,`
61			`address_i,`
62			`data_i,`
63			`we_i,`
64			`re_i,`
65			`data_o,`
66			`rx_data_ready_i,`
67			`rx_translated_data_ready_o,`
68			`rx_read_i,`
69			`rx_read_o,`
70			`rx_extended_i,`
71			`rx_released_i`
72			`) ;`
73
74			`input reset_i,`
75			`clock_i,`
76			`translate_i ;`
77
78			`input [7:0] code_i ;`
79			`output [7:0] code_o ;`
80			`input [7:0] address_i ;`
81			`input [7:0] data_i ;`
82			`input we_i,`
83			`re_i ;`
84
85			`output [7:0] data_o ;`
86
87			`input rx_data_ready_i,`
88			`rx_read_i ;`
89
90			`output rx_translated_data_ready_o ;`
91			`output rx_read_o ;`
92
93			`input rx_extended_i,`
94			`rx_released_i ;`
95
96			`wire translation_table_write_enable = we_i && (!translate_i \|\| !rx_data_ready_i) ;`
97			`wire [7:0] translation_table_address = ((we_i \|\| re_i) && (!rx_data_ready_i \|\| !translate_i)) ? address_i : code_i ;`
98			`wire translation_table_enable = we_i \|\| re_i \|\| (translate_i && rx_data_ready_i) ;`
99
100			`reg rx_translated_data_ready ;`
101			`always@(posedge clock_i or posedge reset_i)`
102			`begin`
103			`if ( reset_i )`
104			`rx_translated_data_ready <= #1 1'b0 ;`
105			`else if ( rx_read_i \|\| !translate_i )`
106			`rx_translated_data_ready <= #1 1'b0 ;`
107			`else`
108			`rx_translated_data_ready <= #1 rx_data_ready_i ;`
109			`end`
110
111			`ifdef PS2_RAMB4
112			`define PS2_RAM_SELECTED
113
114			`wire [7:0] ram_out ;`
115			RAMB4_S8 `ifdef SIM
116			`#("ignore",`
117			`PS2_TRANSLATION_TABLE_31_0,
118			`PS2_TRANSLATION_TABLE_63_32,
119			`PS2_TRANSLATION_TABLE_95_64,
120			`PS2_TRANSLATION_TABLE_127_96,
121			`PS2_TRANSLATION_TABLE_159_128,
122			`PS2_TRANSLATION_TABLE_191_160,
123			`PS2_TRANSLATION_TABLE_223_192,
124			`PS2_TRANSLATION_TABLE_255_224)
125			`endif
126			`ps2_ram`
127			`(`
128			`.DO (ram_out),`
129			`.ADDR ({1'b0, translation_table_address}),`
130			`.DI (data_i),`
131			`.EN (translation_table_enable),`
132			`.CLK (clock_i),`
133			`.WE (translation_table_write_enable),`
134			`.RST (reset_i)`
135			`) ;`
136
137			`endif
138
139			`ifdef PS2_RAM_SELECTED
140			`else
141			`define PS2_RAM_SELECTED
142
143			`reg [7:0] ps2_ram [0:255] ;`
144			`reg [7:0] ram_out ;`
145
146			`always@(posedge clock_i or posedge reset_i)`
147			`begin`
148			`if ( reset_i )`
149			`ram_out <= #1 8'h0 ;`
150			`else if ( translation_table_enable )`
151			`ram_out <= #1 ps2_ram[translation_table_address] ;`
152			`end`
153
154			`always@(posedge clock_i)`
155			`begin`
156			`if ( translation_table_write_enable )`
157			`ps2_ram[translation_table_address] <= #1 data_i ;`
158			`end`
159
160			`// synopsys translate_off`
161			`integer i ;`
162			`reg [255:0] temp_init_val ;`
163			`initial`
164			`begin`
165			temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
166
167			`for ( i = 0 ; i <= 31 ; i = i + 1 )`
168			`begin`
169			`ps2_ram[i] = temp_init_val[7:0] ;`
170			`temp_init_val = temp_init_val >> 8 ;`
171			`end`
172
173			temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
174
175			`for ( i = 32 ; i <= 63 ; i = i + 1 )`
176			`begin`
177			`ps2_ram[i] = temp_init_val[7:0] ;`
178			`temp_init_val = temp_init_val >> 8 ;`
179			`end`
180
181			temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
182
183			`for ( i = 64 ; i <= 95 ; i = i + 1 )`
184			`begin`
185			`ps2_ram[i] = temp_init_val[7:0] ;`
186			`temp_init_val = temp_init_val >> 8 ;`
187			`end`
188
189			temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
190
191			`for ( i = 96 ; i <= 127 ; i = i + 1 )`
192			`begin`
193			`ps2_ram[i] = temp_init_val[7:0] ;`
194			`temp_init_val = temp_init_val >> 8 ;`
195			`end`
196
197			temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
198
199			`for ( i = 128 ; i <= 159 ; i = i + 1 )`
200			`begin`
201			`ps2_ram[i] = temp_init_val[7:0] ;`
202			`temp_init_val = temp_init_val >> 8 ;`
203			`end`
204
205			temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
206
207			`for ( i = 160 ; i <= 191 ; i = i + 1 )`
208			`begin`
209			`ps2_ram[i] = temp_init_val[7:0] ;`
210			`temp_init_val = temp_init_val >> 8 ;`
211			`end`
212
213			temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
214
215			`for ( i = 192 ; i <= 223 ; i = i + 1 )`
216			`begin`
217			`ps2_ram[i] = temp_init_val[7:0] ;`
218			`temp_init_val = temp_init_val >> 8 ;`
219			`end`
220
221			temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
222
223			`for ( i = 224 ; i <= 255 ; i = i + 1 )`
224			`begin`
225			`ps2_ram[i] = temp_init_val[7:0] ;`
226			`temp_init_val = temp_init_val >> 8 ;`
227			`end`
228			`end`
229
230			`// synopsys translate_on`
231
232			`endif
233
234			`assign data_o = ram_out ;`
235			`assign code_o = translate_i ? {(rx_released_i \| ram_out[7]), ram_out[6:0]} : code_i ;`
236			`assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;`
237			`assign rx_read_o = rx_read_i ;`
238
239			`undef PS2_RAM_SELECTED
240
241			`endmodule //ps2_translation_table`