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[/] [ps2/] [tags/] [rel_3/] [rtl/] [verilog/] [ps2_translation_table.v] - Blame information for rev 51

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_translation_table.v                                     ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/04/09 13:21:15  mihad
// Added mouse interface and everything for its handling, cleaned up some unused code
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
`include "ps2_defines.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_translation_table
(
    reset_i,
    clock_i,
    translate_i,
    code_i,
    code_o,
    address_i,
    data_i,
    we_i,
    re_i,
    data_o,
    rx_data_ready_i,
    rx_translated_data_ready_o,
    rx_read_i,
    rx_read_o,
    rx_released_i
) ;
 
input reset_i,
      clock_i,
      translate_i ;
 
input  [7:0] code_i ;
output [7:0] code_o ;
input  [7:0] address_i ;
input  [7:0] data_i ;
input        we_i,
             re_i ;
 
output [7:0] data_o ;
 
input rx_data_ready_i,
      rx_read_i ;
 
output rx_translated_data_ready_o ;
output rx_read_o ;
 
input  rx_released_i ;
 
wire translation_table_write_enable  = we_i && (!translate_i || !rx_data_ready_i) ;
wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
wire translation_table_enable        = we_i || re_i || (translate_i && rx_data_ready_i) ;
 
reg rx_translated_data_ready ;
always@(posedge clock_i or posedge reset_i)
begin
    if ( reset_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else if ( rx_read_i || !translate_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else
        rx_translated_data_ready <= #1 rx_data_ready_i ;
end
 
`ifdef PS2_RAMB4
    `define PS2_RAM_SELECTED
 
    wire [7:0] ram_out ;
    RAMB4_S8
             `ifdef SIM
             #("ignore",
               `PS2_TRANSLATION_TABLE_31_0,
               `PS2_TRANSLATION_TABLE_63_32,
               `PS2_TRANSLATION_TABLE_95_64,
               `PS2_TRANSLATION_TABLE_127_96,
               `PS2_TRANSLATION_TABLE_159_128,
               `PS2_TRANSLATION_TABLE_191_160,
               `PS2_TRANSLATION_TABLE_223_192,
               `PS2_TRANSLATION_TABLE_255_224)
              `endif
    ps2_ram
    (
        .DO   (ram_out),
        .ADDR ({1'b0, translation_table_address}),
        .DI   (data_i),
        .EN   (translation_table_enable),
        .CLK  (clock_i),
        .WE   (translation_table_write_enable),
        .RST  (reset_i)
    ) ;
 
`endif
 
`ifdef PS2_RAM_SELECTED
`else
    `define PS2_RAM_SELECTED
 
    reg [7:0] ps2_ram [0:255] ;
    reg [7:0] ram_out ;
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
            ram_out <= #1 ps2_ram[translation_table_address] ;
    end
 
    always@(posedge clock_i)
    begin
        if ( translation_table_write_enable )
            ps2_ram[translation_table_address] <= #1 data_i ;
    end
 
    // synopsys translate_off
    integer i ;
    reg [255:0] temp_init_val ;
    initial
    begin
        temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
 
        for ( i = 0 ; i <= 31 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
 
        for ( i = 32 ; i <= 63 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
 
        for ( i = 64 ; i <= 95 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
 
        for ( i = 96 ; i <= 127 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
 
        for ( i = 128 ; i <= 159 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
 
        for ( i = 160 ; i <= 191 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
 
        for ( i = 192 ; i <= 223 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
 
        for ( i = 224 ; i <= 255 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
    end
 
    // synopsys translate_on
 
`endif
 
assign data_o = ram_out ;
assign code_o = translate_i ? {(rx_released_i | ram_out[7]), ram_out[6:0]} : code_i ;
assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;
assign rx_read_o = rx_read_i ;
 
`undef PS2_RAM_SELECTED
 
endmodule //ps2_translation_table

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_translation_table.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	17	simons	`// Revision 1.2 2002/04/09 13:21:15 mihad`
47			`// Added mouse interface and everything for its handling, cleaned up some unused code`
48			`//`
49	13	mihad	`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
50			`// Initial project import - working`
51	2	mihad	`//`
52	13	mihad	`//`
53	2	mihad
54			`include "ps2_defines.v"
55
56			`// synopsys translate_off`
57			`include "timescale.v"
58			`// synopsys translate_on`
59
60			`module ps2_translation_table`
61			`(`
62			`reset_i,`
63			`clock_i,`
64			`translate_i,`
65			`code_i,`
66			`code_o,`
67			`address_i,`
68			`data_i,`
69			`we_i,`
70			`re_i,`
71			`data_o,`
72			`rx_data_ready_i,`
73			`rx_translated_data_ready_o,`
74			`rx_read_i,`
75			`rx_read_o,`
76			`rx_released_i`
77			`) ;`
78
79			`input reset_i,`
80			`clock_i,`
81			`translate_i ;`
82
83			`input [7:0] code_i ;`
84			`output [7:0] code_o ;`
85			`input [7:0] address_i ;`
86			`input [7:0] data_i ;`
87			`input we_i,`
88			`re_i ;`
89
90			`output [7:0] data_o ;`
91
92			`input rx_data_ready_i,`
93			`rx_read_i ;`
94
95			`output rx_translated_data_ready_o ;`
96			`output rx_read_o ;`
97
98	13	mihad	`input rx_released_i ;`
99	2	mihad
100			`wire translation_table_write_enable = we_i && (!translate_i \|\| !rx_data_ready_i) ;`
101			`wire [7:0] translation_table_address = ((we_i \|\| re_i) && (!rx_data_ready_i \|\| !translate_i)) ? address_i : code_i ;`
102			`wire translation_table_enable = we_i \|\| re_i \|\| (translate_i && rx_data_ready_i) ;`
103
104			`reg rx_translated_data_ready ;`
105			`always@(posedge clock_i or posedge reset_i)`
106			`begin`
107			`if ( reset_i )`
108			`rx_translated_data_ready <= #1 1'b0 ;`
109			`else if ( rx_read_i \|\| !translate_i )`
110			`rx_translated_data_ready <= #1 1'b0 ;`
111			`else`
112			`rx_translated_data_ready <= #1 rx_data_ready_i ;`
113			`end`
114
115			`ifdef PS2_RAMB4
116			`define PS2_RAM_SELECTED
117	13	mihad
118	2	mihad	`wire [7:0] ram_out ;`
119	17	simons	`RAMB4_S8`
120			`ifdef SIM
121	2	mihad	`#("ignore",`
122	13	mihad	`PS2_TRANSLATION_TABLE_31_0,
123			`PS2_TRANSLATION_TABLE_63_32,
124			`PS2_TRANSLATION_TABLE_95_64,
125			`PS2_TRANSLATION_TABLE_127_96,
126			`PS2_TRANSLATION_TABLE_159_128,
127			`PS2_TRANSLATION_TABLE_191_160,
128			`PS2_TRANSLATION_TABLE_223_192,
129	2	mihad	`PS2_TRANSLATION_TABLE_255_224)
130			`endif
131			`ps2_ram`
132			`(`
133			`.DO (ram_out),`
134			`.ADDR ({1'b0, translation_table_address}),`
135			`.DI (data_i),`
136			`.EN (translation_table_enable),`
137			`.CLK (clock_i),`
138			`.WE (translation_table_write_enable),`
139			`.RST (reset_i)`
140			`) ;`
141	13	mihad
142	2	mihad	`endif
143
144			`ifdef PS2_RAM_SELECTED
145			`else
146			`define PS2_RAM_SELECTED
147	13	mihad
148	2	mihad	`reg [7:0] ps2_ram [0:255] ;`
149			`reg [7:0] ram_out ;`
150	13	mihad
151	2	mihad	`always@(posedge clock_i or posedge reset_i)`
152			`begin`
153			`if ( reset_i )`
154			`ram_out <= #1 8'h0 ;`
155			`else if ( translation_table_enable )`
156			`ram_out <= #1 ps2_ram[translation_table_address] ;`
157			`end`
158
159			`always@(posedge clock_i)`
160			`begin`
161			`if ( translation_table_write_enable )`
162			`ps2_ram[translation_table_address] <= #1 data_i ;`
163			`end`
164
165			`// synopsys translate_off`
166			`integer i ;`
167			`reg [255:0] temp_init_val ;`
168			`initial`
169			`begin`
170			temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
171
172			`for ( i = 0 ; i <= 31 ; i = i + 1 )`
173			`begin`
174			`ps2_ram[i] = temp_init_val[7:0] ;`
175			`temp_init_val = temp_init_val >> 8 ;`
176			`end`
177
178			temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
179	13	mihad
180	2	mihad	`for ( i = 32 ; i <= 63 ; i = i + 1 )`
181			`begin`
182			`ps2_ram[i] = temp_init_val[7:0] ;`
183			`temp_init_val = temp_init_val >> 8 ;`
184			`end`
185
186			temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
187	13	mihad
188	2	mihad	`for ( i = 64 ; i <= 95 ; i = i + 1 )`
189			`begin`
190			`ps2_ram[i] = temp_init_val[7:0] ;`
191			`temp_init_val = temp_init_val >> 8 ;`
192			`end`
193	13	mihad
194	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
195	13	mihad
196	2	mihad	`for ( i = 96 ; i <= 127 ; i = i + 1 )`
197			`begin`
198			`ps2_ram[i] = temp_init_val[7:0] ;`
199			`temp_init_val = temp_init_val >> 8 ;`
200			`end`
201
202			temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
203	13	mihad
204	2	mihad	`for ( i = 128 ; i <= 159 ; i = i + 1 )`
205			`begin`
206			`ps2_ram[i] = temp_init_val[7:0] ;`
207			`temp_init_val = temp_init_val >> 8 ;`
208			`end`
209	13	mihad
210	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
211	13	mihad
212	2	mihad	`for ( i = 160 ; i <= 191 ; i = i + 1 )`
213			`begin`
214			`ps2_ram[i] = temp_init_val[7:0] ;`
215			`temp_init_val = temp_init_val >> 8 ;`
216			`end`
217	13	mihad
218	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
219	13	mihad
220	2	mihad	`for ( i = 192 ; i <= 223 ; i = i + 1 )`
221			`begin`
222			`ps2_ram[i] = temp_init_val[7:0] ;`
223			`temp_init_val = temp_init_val >> 8 ;`
224			`end`
225	13	mihad
226	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
227	13	mihad
228	2	mihad	`for ( i = 224 ; i <= 255 ; i = i + 1 )`
229			`begin`
230			`ps2_ram[i] = temp_init_val[7:0] ;`
231			`temp_init_val = temp_init_val >> 8 ;`
232			`end`
233			`end`
234
235			`// synopsys translate_on`
236
237			`endif
238
239			`assign data_o = ram_out ;`
240			`assign code_o = translate_i ? {(rx_released_i \| ram_out[7]), ram_out[6:0]} : code_i ;`
241			`assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;`
242			`assign rx_read_o = rx_read_i ;`
243
244	13	mihad	`undef PS2_RAM_SELECTED
245	2	mihad
246			`endmodule //ps2_translation_table`

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