1 |
13 |
mihad |
//-------------------------------------------------------------------------------------
|
2 |
|
|
//
|
3 |
|
|
// Author: John Clayton
|
4 |
|
|
// Date : April 30, 2001
|
5 |
|
|
// Update: 4/30/01 copied this file from lcd_2.v (pared down).
|
6 |
|
|
// Update: 5/24/01 changed the first module from "ps2_keyboard_receiver"
|
7 |
|
|
// to "ps2_keyboard_interface"
|
8 |
|
|
// Update: 5/29/01 Added input synchronizing flip-flops. Changed state
|
9 |
|
|
// encoding (m1) for good operation after part config.
|
10 |
|
|
// Update: 5/31/01 Added low drive strength and slow transitions to ps2_clk
|
11 |
|
|
// and ps2_data in the constraints file. Added the signal
|
12 |
|
|
// "tx_shifting_done" as distinguished from "rx_shifting_done."
|
13 |
|
|
// Debugged the transmitter portion in the lab.
|
14 |
|
|
// Update: 6/01/01 Added horizontal tab to the ascii output.
|
15 |
|
|
// Update: 6/01/01 Added parameter TRAP_SHIFT_KEYS.
|
16 |
|
|
// Update: 6/05/01 Debugged the "debounce" timer functionality.
|
17 |
|
|
// Used 60usec timer as a "watchdog" timeout during
|
18 |
|
|
// receive from the keyboard. This means that a keyboard
|
19 |
|
|
// can now be "hot plugged" into the interface, without
|
20 |
|
|
// messing up the bit_count, since the bit_count is reset
|
21 |
|
|
// to zero during periods of inactivity anyway. This was
|
22 |
|
|
// difficult to debug. I ended up using the logic analyzer,
|
23 |
|
|
// and had to scratch my head quite a bit.
|
24 |
|
|
// Update: 6/06/01 Removed extra comments before the input synchronizing
|
25 |
|
|
// flip-flops. Used the correct parameter to size the
|
26 |
|
|
// 5usec_timer_count. Changed the name of this file from
|
27 |
|
|
// ps2.v to ps2_keyboard.v
|
28 |
|
|
// Update: 6/06/01 Removed "&& q[7:0]" in output_strobe logic. Removed extra
|
29 |
|
|
// commented out "else" condition in the shift register and
|
30 |
|
|
// bit counter.
|
31 |
|
|
// Update: 6/07/01 Changed default values for 60usec timer parameters so that
|
32 |
|
|
// they correspond to 60usec for a 49.152MHz clock.
|
33 |
|
|
//
|
34 |
|
|
//
|
35 |
|
|
//
|
36 |
|
|
//
|
37 |
|
|
//
|
38 |
|
|
// Description
|
39 |
|
|
//-------------------------------------------------------------------------------------
|
40 |
|
|
// This is a state-machine driven serial-to-parallel and parallel-to-serial
|
41 |
|
|
// interface to the ps2 style keyboard interface. The details of the operation
|
42 |
|
|
// of the keyboard interface were obtained from the following website:
|
43 |
|
|
//
|
44 |
|
|
// http://www.beyondlogic.org/keyboard/keybrd.htm
|
45 |
|
|
//
|
46 |
|
|
// Some aspects of the keyboard interface are not implemented (e.g, parity
|
47 |
|
|
// checking for the receive side, and recognition of the various commands
|
48 |
|
|
// which the keyboard sends out, such as "power on selt test passed," "Error"
|
49 |
|
|
// and "Resend.") However, if the user wishes to recognize these reply
|
50 |
|
|
// messages, the scan code output can always be used to extend functionality
|
51 |
|
|
// as desired.
|
52 |
|
|
//
|
53 |
|
|
// Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
|
54 |
|
|
// The rx interface provides separate indicator flags for these two conditions
|
55 |
|
|
// with every valid character scan code which it provides. The shift keys are
|
56 |
|
|
// also trapped by the interface, in order to provide correct uppercase ASCII
|
57 |
|
|
// characters at the ascii output, although the scan codes for the shift keys
|
58 |
|
|
// are still provided at the scan code output. So, the left/right ALT keys
|
59 |
|
|
// can be differentiated by the presence of the rx_entended signal, while the
|
60 |
|
|
// left/right shift keys are differentiable by the different scan codes
|
61 |
|
|
// received.
|
62 |
|
|
//
|
63 |
|
|
// The interface to the ps2 keyboard uses ps2_clk clock rates of
|
64 |
|
|
// 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
|
65 |
|
|
// machine runs should be at least twice the rate of the ps2_clk, so that the
|
66 |
|
|
// states can accurately follow the clock signal itself. Four times
|
67 |
|
|
// oversampling is better. Say 200kHz at least. The upper limit for clocking
|
68 |
|
|
// the state machine will undoubtedly be determined by delays in the logic
|
69 |
|
|
// which decodes the scan codes into ASCII equivalents. The maximum speed
|
70 |
|
|
// will be most likely many megahertz, depending upon target technology.
|
71 |
|
|
// In order to run the state machine extremely fast, synchronizing flip-flops
|
72 |
|
|
// have been added to the ps2_clk and ps2_data inputs of the state machine.
|
73 |
|
|
// This avoids poor performance related to slow transitions of the inputs.
|
74 |
|
|
//
|
75 |
|
|
// Because this is a bi-directional interface, while reading from the keyboard
|
76 |
|
|
// the ps2_clk and ps2_data lines are used as inputs. While writing to the
|
77 |
|
|
// keyboard, however (which may be done at any time. If writing interrupts a
|
78 |
|
|
// read from the keyboard, the keyboard will buffer up its data, and send
|
79 |
|
|
// it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
|
80 |
|
|
// and pullup resistors are used to bring the lines high again, by setting
|
81 |
|
|
// the drivers to high impedance state.
|
82 |
|
|
//
|
83 |
|
|
// The tx interface, for writing to the keyboard, does not provide any special
|
84 |
|
|
// pre-processing. It simply transmits the 8-bit command value to the
|
85 |
|
|
// keyboard.
|
86 |
|
|
//
|
87 |
|
|
// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
|
88 |
|
|
// whether they be internal to an FPGA I/O pad, or externally placed.
|
89 |
|
|
// If internal pullups are used, they may be fairly weak, causing bounces
|
90 |
|
|
// due to crosstalk, etc. There is a "debounce timer" implemented in order
|
91 |
|
|
// to eliminate erroneous state transitions which would occur based on bounce.
|
92 |
|
|
//
|
93 |
|
|
// Parameters are provided in order to configure and appropriately size the
|
94 |
|
|
// counter of a 60 microsecond timer used in the transmitter, depending on
|
95 |
|
|
// the clock frequency used. The 60 microsecond period is guaranteed to be
|
96 |
|
|
// more than one period of the ps2_clk_s signal.
|
97 |
|
|
//
|
98 |
|
|
// Also, a smaller 5 microsecond timer has been included for "debounce".
|
99 |
|
|
// This is used because, with internal pullups on the ps2_clk and ps2_data
|
100 |
|
|
// lines, there is some bouncing around which occurs
|
101 |
|
|
//
|
102 |
|
|
// A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
|
103 |
|
|
// from producing scan codes (along with their "undefined" ASCII equivalents)
|
104 |
|
|
// at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
|
105 |
|
|
// key status will only be reported by rx_shift_key_on. No ascii or scan
|
106 |
|
|
// codes will be reported for the shift keys. This is useful for those who
|
107 |
|
|
// wish to use the ASCII data stream, and who don't want to have to "filter
|
108 |
|
|
// out" the shift key codes.
|
109 |
|
|
//
|
110 |
|
|
//-------------------------------------------------------------------------------------
|
111 |
|
|
|
112 |
|
|
|
113 |
|
|
// synopsys translate_off
|
114 |
|
|
`include "timescale.v"
|
115 |
|
|
// synopsys translate_on
|
116 |
|
|
`define TOTAL_BITS 11
|
117 |
|
|
`define RELEASE_CODE 16'hF0
|
118 |
|
|
|
119 |
|
|
module ps2_keyboard (
|
120 |
|
|
clk,
|
121 |
|
|
reset,
|
122 |
|
|
ps2_clk_en_o_,
|
123 |
|
|
ps2_data_en_o_,
|
124 |
|
|
ps2_clk_i,
|
125 |
|
|
ps2_data_i,
|
126 |
|
|
rx_released,
|
127 |
|
|
rx_scan_code,
|
128 |
|
|
rx_data_ready, // rx_read_o
|
129 |
|
|
rx_read, // rx_read_ack_i
|
130 |
|
|
tx_data,
|
131 |
|
|
tx_write,
|
132 |
|
|
tx_write_ack_o,
|
133 |
|
|
tx_error_no_keyboard_ack,
|
134 |
24 |
primozs |
translate,
|
135 |
|
|
devide_reg_i
|
136 |
13 |
mihad |
);
|
137 |
|
|
|
138 |
|
|
// Parameters
|
139 |
|
|
|
140 |
24 |
primozs |
|
141 |
13 |
mihad |
// The timer value can be up to (2^bits) inclusive.
|
142 |
|
|
parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.
|
143 |
|
|
parameter TIMER_60USEC_BITS_PP = 12; // Number of bits needed for timer
|
144 |
|
|
parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
|
145 |
|
|
parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
|
146 |
|
|
|
147 |
|
|
// State encodings, provided as parameters
|
148 |
|
|
// for flexibility to the one instantiating the module.
|
149 |
|
|
// In general, the default values need not be changed.
|
150 |
|
|
|
151 |
|
|
// State "m1_rx_clk_l" has been chosen on purpose. Since the input
|
152 |
|
|
// synchronizing flip-flops initially contain zero, it takes one clk
|
153 |
|
|
// for them to update to reflect the actual (idle = high) status of
|
154 |
|
|
// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
|
155 |
|
|
// allows the state machine to transition to m1_rx_clk_h when the true
|
156 |
|
|
// values of the input signals become present at the outputs of the
|
157 |
|
|
// synchronizing flip-flops. This initial transition is harmless, and it
|
158 |
|
|
// eliminates the need for a "reset" pulse before the interface can operate.
|
159 |
|
|
|
160 |
|
|
parameter m1_rx_clk_h = 1;
|
161 |
|
|
parameter m1_rx_clk_l = 0;
|
162 |
|
|
parameter m1_rx_falling_edge_marker = 13;
|
163 |
|
|
parameter m1_rx_rising_edge_marker = 14;
|
164 |
|
|
parameter m1_tx_force_clk_l = 3;
|
165 |
|
|
parameter m1_tx_first_wait_clk_h = 10;
|
166 |
|
|
parameter m1_tx_first_wait_clk_l = 11;
|
167 |
|
|
parameter m1_tx_reset_timer = 12;
|
168 |
|
|
parameter m1_tx_wait_clk_h = 2;
|
169 |
|
|
parameter m1_tx_clk_h = 4;
|
170 |
|
|
parameter m1_tx_clk_l = 5;
|
171 |
|
|
parameter m1_tx_wait_keyboard_ack = 6;
|
172 |
|
|
parameter m1_tx_done_recovery = 7;
|
173 |
|
|
parameter m1_tx_error_no_keyboard_ack = 8;
|
174 |
|
|
parameter m1_tx_rising_edge_marker = 9;
|
175 |
|
|
parameter m2_rx_data_ready = 1;
|
176 |
|
|
parameter m2_rx_data_ready_ack = 0;
|
177 |
|
|
|
178 |
|
|
|
179 |
|
|
// I/O declarations
|
180 |
|
|
input clk;
|
181 |
|
|
input reset;
|
182 |
|
|
output ps2_clk_en_o_ ;
|
183 |
|
|
output ps2_data_en_o_ ;
|
184 |
|
|
input ps2_clk_i ;
|
185 |
|
|
input ps2_data_i ;
|
186 |
|
|
output rx_released;
|
187 |
|
|
output [7:0] rx_scan_code;
|
188 |
|
|
output rx_data_ready;
|
189 |
|
|
input rx_read;
|
190 |
|
|
input [7:0] tx_data;
|
191 |
|
|
input tx_write;
|
192 |
|
|
output tx_write_ack_o;
|
193 |
|
|
output tx_error_no_keyboard_ack;
|
194 |
|
|
input translate ;
|
195 |
|
|
|
196 |
24 |
primozs |
input [15:0] devide_reg_i;
|
197 |
|
|
|
198 |
13 |
mihad |
reg rx_released;
|
199 |
|
|
reg [7:0] rx_scan_code;
|
200 |
|
|
reg rx_data_ready;
|
201 |
|
|
reg tx_error_no_keyboard_ack;
|
202 |
|
|
|
203 |
|
|
// Internal signal declarations
|
204 |
|
|
wire timer_60usec_done;
|
205 |
|
|
wire timer_5usec_done;
|
206 |
|
|
wire released;
|
207 |
|
|
|
208 |
|
|
// NOTE: These two signals used to be one. They
|
209 |
|
|
// were split into two signals because of
|
210 |
|
|
// shift key trapping. With shift key
|
211 |
|
|
// trapping, no event is generated externally,
|
212 |
|
|
// but the "hold" data must still be cleared
|
213 |
|
|
// anyway regardless, in preparation for the
|
214 |
|
|
// next scan codes.
|
215 |
|
|
wire rx_output_event; // Used only to clear: hold_released, hold_extended
|
216 |
|
|
wire rx_output_strobe; // Used to produce the actual output.
|
217 |
|
|
|
218 |
|
|
wire tx_parity_bit;
|
219 |
|
|
wire rx_shifting_done;
|
220 |
|
|
wire tx_shifting_done;
|
221 |
|
|
|
222 |
|
|
reg [`TOTAL_BITS-1:0] q;
|
223 |
|
|
reg [3:0] m1_state;
|
224 |
|
|
reg [3:0] m1_next_state;
|
225 |
|
|
reg m2_state;
|
226 |
|
|
reg m2_next_state;
|
227 |
|
|
reg [3:0] bit_count;
|
228 |
|
|
reg enable_timer_60usec;
|
229 |
|
|
reg enable_timer_5usec;
|
230 |
|
|
reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
|
231 |
|
|
reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
|
232 |
|
|
reg hold_released; // Holds prior value, cleared at rx_output_strobe
|
233 |
|
|
reg ps2_clk_s; // Synchronous version of this input
|
234 |
|
|
reg ps2_data_s; // Synchronous version of this input
|
235 |
|
|
reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
|
236 |
|
|
reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
|
237 |
24 |
primozs |
reg ps2_clk_ms;
|
238 |
|
|
reg ps2_data_ms;
|
239 |
13 |
mihad |
|
240 |
24 |
primozs |
|
241 |
|
|
reg [15:0] timer_5usec;
|
242 |
|
|
reg timer_done;
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
|
246 |
13 |
mihad |
//--------------------------------------------------------------------------
|
247 |
|
|
// Module code
|
248 |
|
|
|
249 |
|
|
assign ps2_clk_en_o_ = ps2_clk_hi_z ;
|
250 |
|
|
assign ps2_data_en_o_ = ps2_data_hi_z ;
|
251 |
|
|
|
252 |
|
|
// Input "synchronizing" logic -- synchronizes the inputs to the state
|
253 |
|
|
// machine clock, thus avoiding errors related to
|
254 |
|
|
// spurious state machine transitions.
|
255 |
|
|
always @(posedge clk)
|
256 |
|
|
begin
|
257 |
25 |
primozs |
ps2_clk_ms <= #1 ps2_clk_i;
|
258 |
|
|
ps2_data_ms <= #1 ps2_data_i;
|
259 |
24 |
primozs |
|
260 |
25 |
primozs |
ps2_clk_s <= #1 ps2_clk_ms;
|
261 |
|
|
ps2_data_s <= #1 ps2_data_ms;
|
262 |
24 |
primozs |
|
263 |
13 |
mihad |
end
|
264 |
|
|
|
265 |
|
|
// State register
|
266 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
267 |
13 |
mihad |
begin : m1_state_register
|
268 |
25 |
primozs |
if (reset) m1_state <= #1 m1_rx_clk_h;
|
269 |
|
|
else m1_state <= #1 m1_next_state;
|
270 |
13 |
mihad |
end
|
271 |
|
|
|
272 |
|
|
// State transition logic
|
273 |
|
|
always @(m1_state
|
274 |
|
|
or q
|
275 |
|
|
or tx_shifting_done
|
276 |
|
|
or tx_write
|
277 |
|
|
or ps2_clk_s
|
278 |
|
|
or ps2_data_s
|
279 |
|
|
or timer_60usec_done
|
280 |
|
|
or timer_5usec_done
|
281 |
|
|
)
|
282 |
|
|
begin : m1_state_logic
|
283 |
|
|
|
284 |
|
|
// Output signals default to this value, unless changed in a state condition.
|
285 |
25 |
primozs |
ps2_clk_hi_z <= #1 1;
|
286 |
|
|
ps2_data_hi_z <= #1 1;
|
287 |
|
|
tx_error_no_keyboard_ack <= #1 1'b0;
|
288 |
|
|
enable_timer_60usec <= #1 0;
|
289 |
|
|
enable_timer_5usec <= #1 0;
|
290 |
13 |
mihad |
|
291 |
|
|
case (m1_state)
|
292 |
|
|
|
293 |
|
|
m1_rx_clk_h :
|
294 |
|
|
begin
|
295 |
25 |
primozs |
enable_timer_60usec <= #1 1;
|
296 |
|
|
if (tx_write) m1_next_state <= #1 m1_tx_reset_timer;
|
297 |
|
|
else if (~ps2_clk_s) m1_next_state <= #1 m1_rx_falling_edge_marker;
|
298 |
|
|
else m1_next_state <= #1 m1_rx_clk_h;
|
299 |
13 |
mihad |
end
|
300 |
|
|
|
301 |
|
|
m1_rx_falling_edge_marker :
|
302 |
|
|
begin
|
303 |
25 |
primozs |
enable_timer_60usec <= #1 0;
|
304 |
|
|
m1_next_state <= #1 m1_rx_clk_l;
|
305 |
13 |
mihad |
end
|
306 |
|
|
|
307 |
|
|
m1_rx_rising_edge_marker :
|
308 |
|
|
begin
|
309 |
25 |
primozs |
enable_timer_60usec <= #1 0;
|
310 |
|
|
m1_next_state <= #1 m1_rx_clk_h;
|
311 |
13 |
mihad |
end
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
m1_rx_clk_l :
|
315 |
|
|
begin
|
316 |
25 |
primozs |
enable_timer_60usec <= #1 1;
|
317 |
|
|
if (tx_write) m1_next_state <= #1 m1_tx_reset_timer;
|
318 |
|
|
else if (ps2_clk_s) m1_next_state <= #1 m1_rx_rising_edge_marker;
|
319 |
|
|
else m1_next_state <= #1 m1_rx_clk_l;
|
320 |
13 |
mihad |
end
|
321 |
|
|
|
322 |
|
|
m1_tx_reset_timer:
|
323 |
|
|
begin
|
324 |
25 |
primozs |
enable_timer_60usec <= #1 0;
|
325 |
|
|
m1_next_state <= #1 m1_tx_force_clk_l;
|
326 |
13 |
mihad |
end
|
327 |
|
|
|
328 |
|
|
m1_tx_force_clk_l :
|
329 |
|
|
begin
|
330 |
25 |
primozs |
enable_timer_60usec <= #1 1;
|
331 |
|
|
ps2_clk_hi_z <= #1 0; // Force the ps2_clk line low.
|
332 |
|
|
if (timer_60usec_done) m1_next_state <= #1 m1_tx_first_wait_clk_h;
|
333 |
|
|
else m1_next_state <= #1 m1_tx_force_clk_l;
|
334 |
13 |
mihad |
end
|
335 |
|
|
|
336 |
|
|
m1_tx_first_wait_clk_h :
|
337 |
|
|
begin
|
338 |
25 |
primozs |
enable_timer_5usec <= #1 1;
|
339 |
|
|
ps2_data_hi_z <= #1 0; // Start bit.
|
340 |
13 |
mihad |
if (~ps2_clk_s && timer_5usec_done)
|
341 |
25 |
primozs |
m1_next_state <= #1 m1_tx_clk_l;
|
342 |
13 |
mihad |
else
|
343 |
25 |
primozs |
m1_next_state <= #1 m1_tx_first_wait_clk_h;
|
344 |
13 |
mihad |
end
|
345 |
|
|
|
346 |
|
|
// This state must be included because the device might possibly
|
347 |
|
|
// delay for up to 10 milliseconds before beginning its clock pulses.
|
348 |
|
|
// During that waiting time, we cannot drive the data (q[0]) because it
|
349 |
|
|
// is possibly 1, which would cause the keyboard to abort its receive
|
350 |
|
|
// and the expected clocks would then never be generated.
|
351 |
|
|
m1_tx_first_wait_clk_l :
|
352 |
|
|
begin
|
353 |
25 |
primozs |
ps2_data_hi_z <= #1 0;
|
354 |
|
|
if (~ps2_clk_s) m1_next_state <= #1 m1_tx_clk_l;
|
355 |
|
|
else m1_next_state <= #1 m1_tx_first_wait_clk_l;
|
356 |
13 |
mihad |
end
|
357 |
|
|
|
358 |
|
|
m1_tx_wait_clk_h :
|
359 |
|
|
begin
|
360 |
25 |
primozs |
enable_timer_5usec <= #1 1;
|
361 |
|
|
ps2_data_hi_z <= #1 q[0];
|
362 |
13 |
mihad |
if (ps2_clk_s && timer_5usec_done)
|
363 |
25 |
primozs |
m1_next_state <= #1 m1_tx_rising_edge_marker;
|
364 |
13 |
mihad |
else
|
365 |
25 |
primozs |
m1_next_state <= #1 m1_tx_wait_clk_h;
|
366 |
13 |
mihad |
end
|
367 |
|
|
|
368 |
|
|
m1_tx_rising_edge_marker :
|
369 |
|
|
begin
|
370 |
25 |
primozs |
ps2_data_hi_z <= #1 q[0];
|
371 |
|
|
m1_next_state <= #1 m1_tx_clk_h;
|
372 |
13 |
mihad |
end
|
373 |
|
|
|
374 |
|
|
m1_tx_clk_h :
|
375 |
|
|
begin
|
376 |
25 |
primozs |
ps2_data_hi_z <= #1 q[0];
|
377 |
|
|
if (tx_shifting_done) m1_next_state <= #1 m1_tx_wait_keyboard_ack;
|
378 |
|
|
else if (~ps2_clk_s) m1_next_state <= #1 m1_tx_clk_l;
|
379 |
|
|
else m1_next_state <= #1 m1_tx_clk_h;
|
380 |
13 |
mihad |
end
|
381 |
|
|
|
382 |
|
|
m1_tx_clk_l :
|
383 |
|
|
begin
|
384 |
25 |
primozs |
ps2_data_hi_z <= #1 q[0];
|
385 |
|
|
if (ps2_clk_s) m1_next_state <= #1 m1_tx_wait_clk_h;
|
386 |
|
|
else m1_next_state <= #1 m1_tx_clk_l;
|
387 |
13 |
mihad |
end
|
388 |
|
|
|
389 |
|
|
m1_tx_wait_keyboard_ack :
|
390 |
|
|
begin
|
391 |
|
|
if (~ps2_clk_s && ps2_data_s)
|
392 |
25 |
primozs |
m1_next_state <= #1 m1_tx_error_no_keyboard_ack;
|
393 |
13 |
mihad |
else if (~ps2_clk_s && ~ps2_data_s)
|
394 |
25 |
primozs |
m1_next_state <= #1 m1_tx_done_recovery;
|
395 |
|
|
else m1_next_state <= #1 m1_tx_wait_keyboard_ack;
|
396 |
13 |
mihad |
end
|
397 |
|
|
|
398 |
|
|
m1_tx_done_recovery :
|
399 |
|
|
begin
|
400 |
25 |
primozs |
if (ps2_clk_s && ps2_data_s) m1_next_state <= #1 m1_rx_clk_h;
|
401 |
|
|
else m1_next_state <= #1 m1_tx_done_recovery;
|
402 |
13 |
mihad |
end
|
403 |
|
|
|
404 |
|
|
m1_tx_error_no_keyboard_ack :
|
405 |
|
|
begin
|
406 |
25 |
primozs |
tx_error_no_keyboard_ack <= #1 1;
|
407 |
|
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= #1 m1_rx_clk_h;
|
408 |
|
|
else m1_next_state <= #1 m1_tx_error_no_keyboard_ack;
|
409 |
13 |
mihad |
end
|
410 |
|
|
|
411 |
25 |
primozs |
default : m1_next_state <= #1 m1_rx_clk_h;
|
412 |
13 |
mihad |
endcase
|
413 |
|
|
end
|
414 |
|
|
|
415 |
|
|
// State register
|
416 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
417 |
13 |
mihad |
begin : m2_state_register
|
418 |
25 |
primozs |
if (reset) m2_state <= #1 m2_rx_data_ready_ack;
|
419 |
|
|
else m2_state <= #1 m2_next_state;
|
420 |
13 |
mihad |
end
|
421 |
|
|
|
422 |
|
|
// State transition logic
|
423 |
|
|
always @(m2_state or rx_output_strobe or rx_read)
|
424 |
|
|
begin : m2_state_logic
|
425 |
|
|
case (m2_state)
|
426 |
|
|
m2_rx_data_ready_ack:
|
427 |
|
|
begin
|
428 |
25 |
primozs |
rx_data_ready <= #1 1'b0;
|
429 |
|
|
if (rx_output_strobe) m2_next_state <= #1 m2_rx_data_ready;
|
430 |
|
|
else m2_next_state <= #1 m2_rx_data_ready_ack;
|
431 |
13 |
mihad |
end
|
432 |
|
|
m2_rx_data_ready:
|
433 |
|
|
begin
|
434 |
25 |
primozs |
rx_data_ready <= #1 1'b1;
|
435 |
|
|
if (rx_read) m2_next_state <= #1 m2_rx_data_ready_ack;
|
436 |
|
|
else m2_next_state <= #1 m2_rx_data_ready;
|
437 |
13 |
mihad |
end
|
438 |
25 |
primozs |
default : m2_next_state <= #1 m2_rx_data_ready_ack;
|
439 |
13 |
mihad |
endcase
|
440 |
|
|
end
|
441 |
|
|
|
442 |
|
|
// This is the bit counter
|
443 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
444 |
13 |
mihad |
begin
|
445 |
25 |
primozs |
if ( reset) bit_count <= #1 0;
|
446 |
24 |
primozs |
else if ( rx_shifting_done || (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
|
447 |
25 |
primozs |
) bit_count <= #1 0; // normal reset
|
448 |
13 |
mihad |
else if (timer_60usec_done
|
449 |
|
|
&& (m1_state == m1_rx_clk_h)
|
450 |
|
|
&& (ps2_clk_s)
|
451 |
25 |
primozs |
) bit_count <= #1 0; // rx watchdog timer reset
|
452 |
13 |
mihad |
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
|
453 |
|
|
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
|
454 |
|
|
)
|
455 |
25 |
primozs |
bit_count <= #1 bit_count + 1;
|
456 |
13 |
mihad |
end
|
457 |
|
|
// This signal is high for one clock at the end of the timer count.
|
458 |
|
|
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
|
459 |
|
|
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
|
460 |
|
|
|
461 |
|
|
// This is the signal which enables loading of the shift register.
|
462 |
|
|
// It also indicates "ack" to the device writing to the transmitter.
|
463 |
|
|
assign tx_write_ack_o = ( (tx_write && (m1_state == m1_rx_clk_h))
|
464 |
|
|
||(tx_write && (m1_state == m1_rx_clk_l))
|
465 |
|
|
);
|
466 |
|
|
|
467 |
|
|
// This is the ODD parity bit for the transmitted word.
|
468 |
|
|
assign tx_parity_bit = ~^tx_data;
|
469 |
|
|
|
470 |
|
|
// This is the shift register
|
471 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
472 |
13 |
mihad |
begin
|
473 |
25 |
primozs |
if (reset) q <= #1 0;
|
474 |
|
|
else if (tx_write_ack_o) q <= #1 {1'b1,tx_parity_bit,tx_data,1'b0};
|
475 |
13 |
mihad |
else if ( (m1_state == m1_rx_falling_edge_marker)
|
476 |
|
|
||(m1_state == m1_tx_rising_edge_marker) )
|
477 |
25 |
primozs |
q <= #1 {ps2_data_s,q[`TOTAL_BITS-1:1]};
|
478 |
13 |
mihad |
end
|
479 |
|
|
|
480 |
|
|
// This is the 60usec timer counter
|
481 |
|
|
always @(posedge clk)
|
482 |
|
|
begin
|
483 |
25 |
primozs |
if (~enable_timer_60usec) timer_60usec_count <= #1 0;
|
484 |
24 |
primozs |
else if ( timer_done && !timer_60usec_done)
|
485 |
25 |
primozs |
timer_60usec_count<= #1 timer_60usec_count +1;
|
486 |
24 |
primozs |
end
|
487 |
|
|
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP ));
|
488 |
13 |
mihad |
|
489 |
24 |
primozs |
|
490 |
|
|
|
491 |
|
|
always @(posedge clk or posedge reset)
|
492 |
25 |
primozs |
if (reset) timer_5usec <= #1 1;
|
493 |
|
|
else if (!enable_timer_60usec) timer_5usec <= #1 1;
|
494 |
24 |
primozs |
else if (timer_5usec == devide_reg_i)
|
495 |
|
|
begin
|
496 |
25 |
primozs |
timer_5usec <= #1 1;
|
497 |
|
|
timer_done <= #1 1;
|
498 |
24 |
primozs |
end
|
499 |
|
|
else
|
500 |
|
|
begin
|
501 |
25 |
primozs |
timer_5usec<= #1 timer_5usec +1;
|
502 |
|
|
timer_done <= #1 0;
|
503 |
24 |
primozs |
end
|
504 |
|
|
|
505 |
13 |
mihad |
// This is the 5usec timer counter
|
506 |
|
|
always @(posedge clk)
|
507 |
|
|
begin
|
508 |
25 |
primozs |
if (~enable_timer_5usec) timer_5usec_count <= #1 0;
|
509 |
|
|
else if (~timer_5usec_done) timer_5usec_count <= #1 timer_5usec_count + 1;
|
510 |
13 |
mihad |
end
|
511 |
24 |
primozs |
assign timer_5usec_done = (timer_5usec_count == devide_reg_i -1);
|
512 |
13 |
mihad |
|
513 |
|
|
|
514 |
|
|
// Create the signals which indicate special scan codes received.
|
515 |
|
|
// These are the "unlatched versions."
|
516 |
|
|
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done && translate ;
|
517 |
|
|
|
518 |
|
|
// Store the special scan code status bits
|
519 |
|
|
// Not the final output, but an intermediate storage place,
|
520 |
|
|
// until the entire set of output data can be assembled.
|
521 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
522 |
13 |
mihad |
begin
|
523 |
25 |
primozs |
if (reset) hold_released <= #1 0;
|
524 |
24 |
primozs |
else if (rx_output_event)
|
525 |
13 |
mihad |
begin
|
526 |
25 |
primozs |
hold_released <= #1 0;
|
527 |
13 |
mihad |
end
|
528 |
|
|
else
|
529 |
|
|
begin
|
530 |
25 |
primozs |
if (rx_shifting_done && released) hold_released <= #1 1;
|
531 |
13 |
mihad |
end
|
532 |
|
|
end
|
533 |
|
|
|
534 |
|
|
// Output the special scan code flags, the scan code and the ascii
|
535 |
24 |
primozs |
always @(posedge clk or posedge reset)
|
536 |
13 |
mihad |
begin
|
537 |
|
|
if (reset)
|
538 |
|
|
begin
|
539 |
25 |
primozs |
rx_released <= #1 0;
|
540 |
|
|
rx_scan_code <= #1 0;
|
541 |
13 |
mihad |
end
|
542 |
|
|
else if (rx_output_strobe)
|
543 |
|
|
begin
|
544 |
25 |
primozs |
rx_released <= #1 hold_released;
|
545 |
|
|
rx_scan_code <= #1 q[8:1];
|
546 |
13 |
mihad |
end
|
547 |
|
|
end
|
548 |
|
|
|
549 |
|
|
// Store the final rx output data only when all extend and release codes
|
550 |
|
|
// are received and the next (actual key) scan code is also ready.
|
551 |
|
|
// (the presence of rx_extended or rx_released refers to the
|
552 |
|
|
// the current latest scan code received, not the previously latched flags.)
|
553 |
|
|
assign rx_output_event = (rx_shifting_done
|
554 |
|
|
&& ~released
|
555 |
|
|
);
|
556 |
|
|
|
557 |
|
|
assign rx_output_strobe = (rx_shifting_done
|
558 |
|
|
&& ~released
|
559 |
|
|
);
|
560 |
|
|
|
561 |
|
|
endmodule
|
562 |
|
|
|
563 |
|
|
//`undefine TOTAL_BITS
|
564 |
|
|
//`undefine EXTEND_CODE
|
565 |
|
|
//`undefine RELEASE_CODE
|
566 |
|
|
//`undefine LEFT_SHIFT
|
567 |
|
|
//`undefine RIGHT_SHIFT
|
568 |
|
|
|