URL https://opencores.org/ocsvn/ps2/ps2/trunk

Subversion Repositories ps2

[/] [ps2/] [tags/] [rel_8/] [rtl/] [verilog/] [ps2_translation_table.v] - Blame information for rev 51

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_translation_table.v                                     ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/06/02 17:13:22  simons
// resetall keyword removed. ifdef moved to a separated line.
//
// Revision 1.2  2002/04/09 13:21:15  mihad
// Added mouse interface and everything for its handling, cleaned up some unused code
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
`include "ps2_defines.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_translation_table
(
    reset_i,
    clock_i,
    translate_i,
    code_i,
    code_o,
    address_i,
    data_i,
    we_i,
    re_i,
    data_o,
    rx_data_ready_i,
    rx_translated_data_ready_o,
    rx_read_i,
    rx_read_o,
    rx_released_i
) ;
 
input reset_i,
      clock_i,
      translate_i ;
 
input  [7:0] code_i ;
output [7:0] code_o ;
input  [7:0] address_i ;
input  [7:0] data_i ;
input        we_i,
             re_i ;
 
output [7:0] data_o ;
 
input rx_data_ready_i,
      rx_read_i ;
 
output rx_translated_data_ready_o ;
output rx_read_o ;
 
input  rx_released_i ;
 
wire translation_table_write_enable  = we_i && (!translate_i || !rx_data_ready_i) ;
wire [7:0] translation_table_address = ((we_i || re_i) && (!rx_data_ready_i || !translate_i)) ? address_i : code_i ;
wire translation_table_enable        = we_i || re_i || (translate_i && rx_data_ready_i) ;
 
reg rx_translated_data_ready ;
always@(posedge clock_i or posedge reset_i)
begin
    if ( reset_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else if ( rx_read_i || !translate_i )
        rx_translated_data_ready <= #1 1'b0 ;
    else
        rx_translated_data_ready <= #1 rx_data_ready_i ;
end
 
`ifdef PS2_RAMB4
    `define PS2_RAM_SELECTED
 
    wire [7:0] ram_out ;
    RAMB4_S8
             `ifdef SIM
             #("ignore",
               `PS2_TRANSLATION_TABLE_31_0,
               `PS2_TRANSLATION_TABLE_63_32,
               `PS2_TRANSLATION_TABLE_95_64,
               `PS2_TRANSLATION_TABLE_127_96,
               `PS2_TRANSLATION_TABLE_159_128,
               `PS2_TRANSLATION_TABLE_191_160,
               `PS2_TRANSLATION_TABLE_223_192,
               `PS2_TRANSLATION_TABLE_255_224)
              `endif
    ps2_ram
    (
        .DO   (ram_out),
        .ADDR ({1'b0, translation_table_address}),
        .DI   (data_i),
        .EN   (translation_table_enable),
        .CLK  (clock_i),
        .WE   (translation_table_write_enable),
        .RST  (reset_i)
    ) ;
 
`endif
 
`ifdef PS2_CONSTANTS_ROM
    `define PS2_RAM_SELECTED
 
    reg [32 * 8 - 1:0] ps2_32byte_constant ;
    reg [7:0] ram_out ;
 
    always@(translation_table_address)
    begin
        case (translation_table_address[7:5])
            3'b000:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_31_0    ;
            3'b001:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_63_32   ;
            3'b010:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_95_64   ;
            3'b011:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_127_96  ;
            3'b100:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_159_128 ;
            3'b101:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_191_160 ;
            3'b110:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_223_192 ;
            3'b111:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_255_224 ;
        endcase
    end
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
        begin:get_dat_out
            reg [7:0] bit_num ;
 
            bit_num = translation_table_address[4:0] << 3 ;
 
            repeat(8)
            begin
                ram_out[bit_num % 8] <= #1 ps2_32byte_constant[bit_num] ;
                bit_num = bit_num + 1'b1 ;
            end
        end
    end
 
`endif
 
`ifdef PS2_RAM_SELECTED
`else
    `define PS2_RAM_SELECTED
 
    reg [7:0] ps2_ram [0:255] ;
    reg [7:0] ram_out ;
 
    always@(posedge clock_i or posedge reset_i)
    begin
        if ( reset_i )
            ram_out <= #1 8'h0 ;
        else if ( translation_table_enable )
            ram_out <= #1 ps2_ram[translation_table_address] ;
    end
 
    always@(posedge clock_i)
    begin
        if ( translation_table_write_enable )
            ps2_ram[translation_table_address] <= #1 data_i ;
    end
 
    // synopsys translate_off
    initial
    begin:ps2_ram_init
        integer i ;
        reg [255:0] temp_init_val ;
 
        temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
 
        for ( i = 0 ; i <= 31 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
 
        for ( i = 32 ; i <= 63 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
 
        for ( i = 64 ; i <= 95 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
 
        for ( i = 96 ; i <= 127 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
 
        for ( i = 128 ; i <= 159 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
 
        for ( i = 160 ; i <= 191 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
 
        for ( i = 192 ; i <= 223 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
 
        temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
 
        for ( i = 224 ; i <= 255 ; i = i + 1 )
        begin
            ps2_ram[i] = temp_init_val[7:0] ;
            temp_init_val = temp_init_val >> 8 ;
        end
    end
 
    // synopsys translate_on
 
`endif
 
assign data_o = ram_out ;
assign code_o = translate_i ? {(rx_released_i | ram_out[7]), ram_out[6:0]} : code_i ;
assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;
assign rx_read_o = rx_read_i ;
 
`undef PS2_RAM_SELECTED
 
endmodule //ps2_translation_table

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_translation_table.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	23	mihad	`// Revision 1.3 2003/06/02 17:13:22 simons`
47			`// resetall keyword removed. ifdef moved to a separated line.`
48			`//`
49	17	simons	`// Revision 1.2 2002/04/09 13:21:15 mihad`
50			`// Added mouse interface and everything for its handling, cleaned up some unused code`
51			`//`
52	13	mihad	`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
53			`// Initial project import - working`
54	2	mihad	`//`
55	13	mihad	`//`
56	2	mihad
57			`include "ps2_defines.v"
58
59			`// synopsys translate_off`
60			`include "timescale.v"
61			`// synopsys translate_on`
62
63			`module ps2_translation_table`
64			`(`
65			`reset_i,`
66			`clock_i,`
67			`translate_i,`
68			`code_i,`
69			`code_o,`
70			`address_i,`
71			`data_i,`
72			`we_i,`
73			`re_i,`
74			`data_o,`
75			`rx_data_ready_i,`
76			`rx_translated_data_ready_o,`
77			`rx_read_i,`
78			`rx_read_o,`
79			`rx_released_i`
80			`) ;`
81
82			`input reset_i,`
83			`clock_i,`
84			`translate_i ;`
85
86			`input [7:0] code_i ;`
87			`output [7:0] code_o ;`
88			`input [7:0] address_i ;`
89			`input [7:0] data_i ;`
90			`input we_i,`
91			`re_i ;`
92
93			`output [7:0] data_o ;`
94
95			`input rx_data_ready_i,`
96			`rx_read_i ;`
97
98			`output rx_translated_data_ready_o ;`
99			`output rx_read_o ;`
100
101	13	mihad	`input rx_released_i ;`
102	2	mihad
103			`wire translation_table_write_enable = we_i && (!translate_i \|\| !rx_data_ready_i) ;`
104			`wire [7:0] translation_table_address = ((we_i \|\| re_i) && (!rx_data_ready_i \|\| !translate_i)) ? address_i : code_i ;`
105			`wire translation_table_enable = we_i \|\| re_i \|\| (translate_i && rx_data_ready_i) ;`
106
107			`reg rx_translated_data_ready ;`
108			`always@(posedge clock_i or posedge reset_i)`
109			`begin`
110			`if ( reset_i )`
111			`rx_translated_data_ready <= #1 1'b0 ;`
112			`else if ( rx_read_i \|\| !translate_i )`
113			`rx_translated_data_ready <= #1 1'b0 ;`
114			`else`
115			`rx_translated_data_ready <= #1 rx_data_ready_i ;`
116			`end`
117
118			`ifdef PS2_RAMB4
119			`define PS2_RAM_SELECTED
120	13	mihad
121	2	mihad	`wire [7:0] ram_out ;`
122	17	simons	`RAMB4_S8`
123			`ifdef SIM
124	2	mihad	`#("ignore",`
125	13	mihad	`PS2_TRANSLATION_TABLE_31_0,
126			`PS2_TRANSLATION_TABLE_63_32,
127			`PS2_TRANSLATION_TABLE_95_64,
128			`PS2_TRANSLATION_TABLE_127_96,
129			`PS2_TRANSLATION_TABLE_159_128,
130			`PS2_TRANSLATION_TABLE_191_160,
131			`PS2_TRANSLATION_TABLE_223_192,
132	2	mihad	`PS2_TRANSLATION_TABLE_255_224)
133			`endif
134			`ps2_ram`
135			`(`
136			`.DO (ram_out),`
137			`.ADDR ({1'b0, translation_table_address}),`
138			`.DI (data_i),`
139			`.EN (translation_table_enable),`
140			`.CLK (clock_i),`
141			`.WE (translation_table_write_enable),`
142			`.RST (reset_i)`
143			`) ;`
144	13	mihad
145	2	mihad	`endif
146
147	23	mihad	`ifdef PS2_CONSTANTS_ROM
148			`define PS2_RAM_SELECTED
149
150			`reg [32 * 8 - 1:0] ps2_32byte_constant ;`
151			`reg [7:0] ram_out ;`
152
153			`always@(translation_table_address)`
154			`begin`
155			`case (translation_table_address[7:5])`
156			3'b000:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_31_0 ;
157			3'b001:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_63_32 ;
158			3'b010:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_95_64 ;
159			3'b011:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_127_96 ;
160			3'b100:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_159_128 ;
161			3'b101:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_191_160 ;
162			3'b110:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_223_192 ;
163			3'b111:ps2_32byte_constant = `PS2_TRANSLATION_TABLE_255_224 ;
164			`endcase`
165			`end`
166
167			`always@(posedge clock_i or posedge reset_i)`
168			`begin`
169			`if ( reset_i )`
170			`ram_out <= #1 8'h0 ;`
171			`else if ( translation_table_enable )`
172			`begin:get_dat_out`
173			`reg [7:0] bit_num ;`
174
175			`bit_num = translation_table_address[4:0] << 3 ;`
176
177			`repeat(8)`
178			`begin`
179			`ram_out[bit_num % 8] <= #1 ps2_32byte_constant[bit_num] ;`
180			`bit_num = bit_num + 1'b1 ;`
181			`end`
182			`end`
183			`end`
184
185			`endif
186
187	2	mihad	`ifdef PS2_RAM_SELECTED
188			`else
189			`define PS2_RAM_SELECTED
190	13	mihad
191	2	mihad	`reg [7:0] ps2_ram [0:255] ;`
192			`reg [7:0] ram_out ;`
193	13	mihad
194	2	mihad	`always@(posedge clock_i or posedge reset_i)`
195			`begin`
196			`if ( reset_i )`
197			`ram_out <= #1 8'h0 ;`
198			`else if ( translation_table_enable )`
199			`ram_out <= #1 ps2_ram[translation_table_address] ;`
200			`end`
201
202			`always@(posedge clock_i)`
203			`begin`
204			`if ( translation_table_write_enable )`
205			`ps2_ram[translation_table_address] <= #1 data_i ;`
206			`end`
207
208			`// synopsys translate_off`
209			`initial`
210	23	mihad	`begin:ps2_ram_init`
211			`integer i ;`
212			`reg [255:0] temp_init_val ;`
213
214	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_31_0 ;
215
216			`for ( i = 0 ; i <= 31 ; i = i + 1 )`
217			`begin`
218			`ps2_ram[i] = temp_init_val[7:0] ;`
219			`temp_init_val = temp_init_val >> 8 ;`
220			`end`
221
222			temp_init_val = `PS2_TRANSLATION_TABLE_63_32 ;
223	13	mihad
224	2	mihad	`for ( i = 32 ; i <= 63 ; i = i + 1 )`
225			`begin`
226			`ps2_ram[i] = temp_init_val[7:0] ;`
227			`temp_init_val = temp_init_val >> 8 ;`
228			`end`
229
230			temp_init_val = `PS2_TRANSLATION_TABLE_95_64 ;
231	13	mihad
232	2	mihad	`for ( i = 64 ; i <= 95 ; i = i + 1 )`
233			`begin`
234			`ps2_ram[i] = temp_init_val[7:0] ;`
235			`temp_init_val = temp_init_val >> 8 ;`
236			`end`
237	13	mihad
238	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_127_96 ;
239	13	mihad
240	2	mihad	`for ( i = 96 ; i <= 127 ; i = i + 1 )`
241			`begin`
242			`ps2_ram[i] = temp_init_val[7:0] ;`
243			`temp_init_val = temp_init_val >> 8 ;`
244			`end`
245
246			temp_init_val = `PS2_TRANSLATION_TABLE_159_128 ;
247	13	mihad
248	2	mihad	`for ( i = 128 ; i <= 159 ; i = i + 1 )`
249			`begin`
250			`ps2_ram[i] = temp_init_val[7:0] ;`
251			`temp_init_val = temp_init_val >> 8 ;`
252			`end`
253	13	mihad
254	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_191_160 ;
255	13	mihad
256	2	mihad	`for ( i = 160 ; i <= 191 ; i = i + 1 )`
257			`begin`
258			`ps2_ram[i] = temp_init_val[7:0] ;`
259			`temp_init_val = temp_init_val >> 8 ;`
260			`end`
261	13	mihad
262	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_223_192 ;
263	13	mihad
264	2	mihad	`for ( i = 192 ; i <= 223 ; i = i + 1 )`
265			`begin`
266			`ps2_ram[i] = temp_init_val[7:0] ;`
267			`temp_init_val = temp_init_val >> 8 ;`
268			`end`
269	13	mihad
270	2	mihad	temp_init_val = `PS2_TRANSLATION_TABLE_255_224 ;
271	13	mihad
272	2	mihad	`for ( i = 224 ; i <= 255 ; i = i + 1 )`
273			`begin`
274			`ps2_ram[i] = temp_init_val[7:0] ;`
275			`temp_init_val = temp_init_val >> 8 ;`
276			`end`
277			`end`
278
279			`// synopsys translate_on`
280
281			`endif
282
283			`assign data_o = ram_out ;`
284			`assign code_o = translate_i ? {(rx_released_i \| ram_out[7]), ram_out[6:0]} : code_i ;`
285			`assign rx_translated_data_ready_o = translate_i ? rx_translated_data_ready : rx_data_ready_i ;`
286			`assign rx_read_o = rx_read_i ;`
287
288	13	mihad	`undef PS2_RAM_SELECTED
289	2	mihad
290			`endmodule //ps2_translation_table`

Browse

Tools

Subversion Repositories ps2

[/] [ps2/] [tags/] [rel_8/] [rtl/] [verilog/] [ps2_translation_table.v] - Blame information for rev 51