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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ps2_wb_if.v                                                 ////
////                                                              ////
////  This file is part of the "ps2" project                      ////
////  http://www.opencores.org/cores/ps2/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/04/09 13:24:11  mihad
// Added mouse interface and everything for its handling, cleaned up some unused code
//
// Revision 1.4  2002/02/20 16:35:43  mihad
// Little/big endian changes continued
//
// Revision 1.3  2002/02/20 15:20:10  mihad
// Little/big endian changes incorporated
//
// Revision 1.2  2002/02/18 18:07:55  mihad
// One bug fixed
//
// Revision 1.1.1.1  2002/02/18 16:16:56  mihad
// Initial project import - working
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ps2_wb_if
(
    wb_clk_i,
    wb_rst_i,
    wb_cyc_i,
    wb_stb_i,
    wb_we_i,
    wb_sel_i,
    wb_adr_i,
    wb_dat_i,
    wb_dat_o,
    wb_ack_o,
 
    wb_int_o,
 
    tx_kbd_write_ack_i,
    tx_kbd_data_o,
    tx_kbd_write_o,
    rx_scancode_i,
    rx_kbd_data_ready_i,
    rx_kbd_read_o,
    translate_o,
    ps2_kbd_clk_i,
    inhibit_kbd_if_o
    `ifdef PS2_AUX
    ,
    wb_intb_o,
 
    rx_aux_data_i,
    rx_aux_data_ready_i,
    rx_aux_read_o,
    tx_aux_data_o,
    tx_aux_write_o,
    tx_aux_write_ack_i,
    ps2_aux_clk_i,
    inhibit_aux_if_o
`endif
) ;
 
input wb_clk_i,
      wb_rst_i,
      wb_cyc_i,
      wb_stb_i,
      wb_we_i ;
 
input [3:0]  wb_sel_i ;
 
input [2:0]  wb_adr_i ;
 
input [31:0]  wb_dat_i ;
 
output [31:0] wb_dat_o ;
 
output wb_ack_o ;
 
reg wb_ack_o ;
 
output wb_int_o ;
reg    wb_int_o ;
 
input tx_kbd_write_ack_i ;
 
input [7:0] rx_scancode_i ;
input       rx_kbd_data_ready_i ;
output      rx_kbd_read_o ;
 
output      tx_kbd_write_o ;
output [7:0] tx_kbd_data_o ;
 
output translate_o ;
input  ps2_kbd_clk_i ;
 
output inhibit_kbd_if_o ;
 
reg [7:0] input_buffer,
          output_buffer ;
 
reg [7:0] wb_dat_i_sampled ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_i_sampled <= #1 0 ;
    else if ( wb_cyc_i && wb_stb_i && wb_we_i )
        wb_dat_i_sampled <= #1 wb_dat_i[31:24] ;
end
 
`ifdef PS2_AUX
output wb_intb_o ;
reg    wb_intb_o ;
 
input  [7:0]    rx_aux_data_i ;
input           rx_aux_data_ready_i ;
output          rx_aux_read_o ;
output [7:0]    tx_aux_data_o ;
output          tx_aux_write_o ;
input           tx_aux_write_ack_i ;
input           ps2_aux_clk_i ;
output          inhibit_aux_if_o ;
reg             inhibit_aux_if_o ;
reg             aux_output_buffer_full ;
reg             aux_input_buffer_full ;
reg             interrupt2 ;
reg             enable2    ;
assign          tx_aux_data_o  = output_buffer ;
assign          tx_aux_write_o = aux_output_buffer_full ;
`else
wire aux_input_buffer_full  = 1'b0 ;
wire aux_output_buffer_full = 1'b0 ;
wire interrupt2             = 1'b0 ;
wire enable2                = 1'b1 ;
`endif
 
assign tx_kbd_data_o = output_buffer ;
 
reg input_buffer_full,   // receive buffer
    output_buffer_full ; // transmit buffer
 
assign tx_kbd_write_o = output_buffer_full ;
 
wire system_flag ;
wire a2                       = 1'b0 ;
wire kbd_inhibit              = ps2_kbd_clk_i ;
wire timeout                  = 1'b0 ;
wire perr                     = 1'b0 ;
 
wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full || aux_output_buffer_full, input_buffer_full} ;
 
reg  read_input_buffer_reg ;
wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;
 
reg  write_output_buffer_reg ;
wire write_output_buffer  = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i  && (wb_adr_i[2:0] == 3'h0) ;
 
reg  read_status_register_reg ;
wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;
 
reg  send_command_reg ;
wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i  && (wb_adr_i[2:0] == 3'h4) ;
 
reg  translate_o,
     enable1,
     system,
     interrupt1 ;
 
reg inhibit_kbd_if_o ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_kbd_if_o <= #1 1'b1 ;
    else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)
        inhibit_kbd_if_o <= #1 1'b1 ;
    else if ( !rx_kbd_data_ready_i || enable1 )
        inhibit_kbd_if_o <= #1 1'b0 ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )
        inhibit_aux_if_o <= #1 1'b1 ;
    else if ( !rx_aux_data_ready_i || enable2 )
        inhibit_aux_if_o <= #1 1'b0 ;
 
end
`endif
 
assign system_flag = system ;
 
wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;
 
reg [7:0] current_command ;
reg [7:0] current_command_output ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        send_command_reg         <= #1 1'b0 ;
        read_input_buffer_reg    <= #1 1'b0 ;
        write_output_buffer_reg  <= #1 1'b0 ;
        read_status_register_reg <= #1 1'b0 ;
    end
    else
    begin
        send_command_reg         <= #1 send_command ;
        read_input_buffer_reg    <= #1 read_input_buffer ;
        write_output_buffer_reg  <= #1 write_output_buffer ;
        read_status_register_reg <= #1 read_status_register ;
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command <= #1 8'h0 ;
    else if ( send_command_reg )
        current_command <= #1 wb_dat_i_sampled ;
end
 
reg current_command_valid,
    current_command_returns_value,
    current_command_gets_parameter,
    current_command_gets_null_terminated_string ;
 
reg write_output_buffer_reg_previous ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        write_output_buffer_reg_previous <= #1 1'b0 ;
    else
        write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;
end
 
wire invalidate_current_command =
     current_command_valid &&
     (( current_command_returns_value && read_input_buffer_reg && input_buffer_full) ||
      ( current_command_gets_parameter && write_output_buffer_reg_previous ) ||
      ( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) ||
      ( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )
     ) ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        current_command_valid <= #1 1'b0 ;
    else if ( invalidate_current_command )
        current_command_valid <= #1 1'b0 ;
    else if ( send_command_reg )
        current_command_valid <= #1 1'b1 ;
 
end
 
reg write_command_byte ;
reg current_command_output_valid ;
always@(
    current_command or
    command_byte or
    write_output_buffer_reg_previous or
    current_command_valid or
    output_buffer
)
begin
    current_command_returns_value               = 1'b0 ;
    current_command_gets_parameter              = 1'b0 ;
    current_command_gets_null_terminated_string = 1'b0 ;
    current_command_output                      = 8'h00 ;
    write_command_byte                          = 1'b0 ;
    current_command_output_valid                = 1'b0 ;
    case(current_command)
        8'h20:begin
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = command_byte ;
                  current_command_output_valid   = 1'b1 ;
              end
        8'h60:begin
                  current_command_gets_parameter = 1'b1 ;
                  write_command_byte             = write_output_buffer_reg_previous && current_command_valid ;
              end
        8'hA1:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA4:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hF1 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hA5:begin
                  current_command_gets_null_terminated_string = 1'b1 ;
              end
        8'hA6:begin
              end
        8'hA7:begin
              end
        8'hA8:begin
              end
        8'hA9:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output_valid  = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_output        = 8'h00 ;  // interface OK
                  `else
                  current_command_output        = 8'h02 ; // clock line stuck high
                  `endif
              end
        8'hAA:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h55 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAB:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hAD:begin
              end
        8'hAE:begin
              end
        8'hAF:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h00 ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
        8'hC1:begin
              end
        8'hC2:begin
              end
        8'hD0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'h01 ; // only system reset bit is 1
                  current_command_output_valid  = 1'b1 ;
              end
        8'hD1:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hD2:begin
                  current_command_returns_value   = 1'b1 ;
                  current_command_gets_parameter  = 1'b1 ;
                  current_command_output          = output_buffer ;
                  current_command_output_valid    = write_output_buffer_reg_previous ;
              end
        8'hD3:begin
                  current_command_gets_parameter = 1'b1 ;
                  `ifdef PS2_AUX
                  current_command_returns_value  = 1'b1 ;
                  current_command_output         = output_buffer ;
                  current_command_output_valid   = write_output_buffer_reg_previous ;
                  `endif
              end
        8'hD4:begin
                  current_command_gets_parameter = 1'b1 ;
              end
        8'hE0:begin
                  current_command_returns_value = 1'b1 ;
                  current_command_output        = 8'hFF ;
                  current_command_output_valid  = 1'b1 ;
              end
    endcase
end
 
reg cyc_i_previous ;
reg stb_i_previous ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else if ( wb_ack_o )
    begin
        cyc_i_previous <= #1 1'b0 ;
        stb_i_previous <= #1 1'b0 ;
    end
    else
    begin
        cyc_i_previous <= #1 wb_cyc_i ;
        stb_i_previous <= #1 wb_stb_i ;
    end
 
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_ack_o <= #1 1'b0 ;
    else if ( wb_ack_o )
        wb_ack_o <= #1 1'b0 ;
    else
        wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;
end
 
reg [31:0] wb_dat_o ;
wire wb_read = read_input_buffer_reg || read_status_register_reg ;
 
wire [7:0] output_data = read_status_register_reg ? status_byte : input_buffer ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_dat_o <= #1 32'h0 ;
    else if ( wb_read )
        wb_dat_o <= #1 {4{output_data}} ;
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer_full <= #1 1'b0 ;
    else if ( output_buffer_full && tx_kbd_write_ack_i || enable1)
        output_buffer_full <= #1 1'b0 ;
    else
        output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid || (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_output_buffer_full <= #1 1'b0 ;
    else if ( aux_output_buffer_full && tx_aux_write_ack_i || enable2)
        aux_output_buffer_full <= #1 1'b0 ;
    else
        aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;
end
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        output_buffer <= #1 8'h00 ;
    else if ( write_output_buffer_reg )
        output_buffer <= #1 wb_dat_i_sampled ;
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
    begin
        translate_o <= #1 1'b0 ;
        system      <= #1 1'b0 ;
        interrupt1  <= #1 1'b0 ;
        `ifdef PS2_AUX
        interrupt2  <= #1 1'b0 ;
        `endif
    end
    else if ( write_command_byte )
    begin
        translate_o <= #1 output_buffer[6] ;
        system      <= #1 output_buffer[2] ;
        interrupt1  <= #1 output_buffer[0] ;
        `ifdef PS2_AUX
        interrupt2  <= #1 output_buffer[1] ;
        `endif
    end
end
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable1 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hAE) )
        enable1 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hAD) )
        enable1 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable1 <= #1 output_buffer[4] ;
 
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        enable2 <= #1 1'b1 ;
    else if ( current_command_valid && (current_command == 8'hA8) )
        enable2 <= #1 1'b0 ;
    else if ( current_command_valid && (current_command == 8'hA7) )
        enable2 <= #1 1'b1 ;
    else if ( write_command_byte )
        enable2 <= #1 output_buffer[5] ;
 
end
`endif
 
wire write_input_buffer_from_command = current_command_valid && current_command_returns_value && current_command_output_valid ;
wire write_input_buffer_from_kbd     = !input_buffer_full && rx_kbd_data_ready_i && !enable1 && !current_command_valid ;
 
`ifdef PS2_AUX
wire write_input_buffer_from_aux     = !input_buffer_full && rx_aux_data_ready_i && !enable2 && !current_command_valid && !write_input_buffer_from_kbd ;
`endif
 
wire load_input_buffer_value =
    write_input_buffer_from_command
    ||
    write_input_buffer_from_kbd
    `ifdef PS2_AUX
    ||
    write_input_buffer_from_aux
    `endif
    ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_full <= #1 1'b0 ;
    else if ( load_input_buffer_value )
        input_buffer_full <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        aux_input_buffer_full <= #1 1'b0 ;
    else if ( write_input_buffer_from_aux || (write_input_buffer_from_command && (current_command == 8'hD3)) )
        aux_input_buffer_full <= #1 1'b1 ;
end
`endif
 
reg input_buffer_filled_from_command ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( read_input_buffer_reg )
        input_buffer_filled_from_command <= #1 1'b0 ;
    else if ( write_input_buffer_from_command )
        input_buffer_filled_from_command <= #1 1'b1 ;
end
 
`ifdef PS2_AUX
reg [7:0] value_to_load_in_input_buffer ;
always@
(
    write_input_buffer_from_command
    or
    current_command_output
    or
    rx_scancode_i
    or
    write_input_buffer_from_kbd
    or
    rx_aux_data_i
)
begin
    case ({write_input_buffer_from_command, write_input_buffer_from_kbd})
        2'b10,
        2'b11   :   value_to_load_in_input_buffer = current_command_output ;
        2'b01   :   value_to_load_in_input_buffer = rx_scancode_i ;
        2'b00   :   value_to_load_in_input_buffer = rx_aux_data_i ;
    endcase
end
 
`else
wire [7:0] value_to_load_in_input_buffer = write_input_buffer_from_command ? current_command_output : rx_scancode_i ;
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        input_buffer <= #1 8'h00 ;
    else if ( load_input_buffer_value )
        input_buffer <= #1 value_to_load_in_input_buffer ;
end
 
assign rx_kbd_read_o = rx_kbd_data_ready_i &&
                       ( enable1
                         ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                           `ifdef PS2_AUX
                           &&
                           !aux_input_buffer_full
                           `endif
                          )
                        );
 
`ifdef PS2_AUX
assign rx_aux_read_o = rx_aux_data_ready_i &&
                       ( enable2 ||
                         ( read_input_buffer_reg
                           &&
                           input_buffer_full
                           &&
                           aux_input_buffer_full
                           &&
                           !input_buffer_filled_from_command
                          )
                        );
`endif
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_int_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable1 || !interrupt1)
        wb_int_o <= #1 1'b0 ;
    else
        wb_int_o <= #1 input_buffer_full
                       `ifdef PS2_AUX
                       &&
                       !aux_input_buffer_full
                       `endif
                       ;
end
 
`ifdef PS2_AUX
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if ( wb_rst_i )
        wb_intb_o <= #1 1'b0 ;
    else if ( read_input_buffer_reg || enable2 || !interrupt2)
        wb_intb_o <= #1 1'b0 ;
    else
        wb_intb_o <= #1 input_buffer_full
                       &&
                       aux_input_buffer_full
                       ;
end
`endif
 
endmodule // ps2_wb_if

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ps2_wb_if.v ////`
4			`//// ////`
5			`//// This file is part of the "ps2" project ////`
6			`//// http://www.opencores.org/cores/ps2/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	15	simons	`// Revision 1.5 2002/04/09 13:24:11 mihad`
47			`// Added mouse interface and everything for its handling, cleaned up some unused code`
48			`//`
49	13	mihad	`// Revision 1.4 2002/02/20 16:35:43 mihad`
50			`// Little/big endian changes continued`
51			`//`
52	7	mihad	`// Revision 1.3 2002/02/20 15:20:10 mihad`
53			`// Little/big endian changes incorporated`
54			`//`
55	6	mihad	`// Revision 1.2 2002/02/18 18:07:55 mihad`
56			`// One bug fixed`
57			`//`
58	5	mihad	`// Revision 1.1.1.1 2002/02/18 16:16:56 mihad`
59			`// Initial project import - working`
60	2	mihad	`//`
61	5	mihad	`//`
62	2	mihad
63			`// synopsys translate_off`
64			`include "timescale.v"
65			`// synopsys translate_on`
66
67			`module ps2_wb_if`
68			`(`
69			`wb_clk_i,`
70			`wb_rst_i,`
71			`wb_cyc_i,`
72			`wb_stb_i,`
73			`wb_we_i,`
74			`wb_sel_i,`
75			`wb_adr_i,`
76			`wb_dat_i,`
77			`wb_dat_o,`
78			`wb_ack_o,`
79	13	mihad
80	2	mihad	`wb_int_o,`
81
82	13	mihad	`tx_kbd_write_ack_i,`
83			`tx_kbd_data_o,`
84			`tx_kbd_write_o,`
85	2	mihad	`rx_scancode_i,`
86	13	mihad	`rx_kbd_data_ready_i,`
87			`rx_kbd_read_o,`
88	2	mihad	`translate_o,`
89	13	mihad	`ps2_kbd_clk_i,`
90	2	mihad	`inhibit_kbd_if_o`
91	13	mihad	`ifdef PS2_AUX
92			`,`
93			`wb_intb_o,`
94
95			`rx_aux_data_i,`
96			`rx_aux_data_ready_i,`
97			`rx_aux_read_o,`
98			`tx_aux_data_o,`
99			`tx_aux_write_o,`
100			`tx_aux_write_ack_i,`
101			`ps2_aux_clk_i,`
102			`inhibit_aux_if_o`
103			`endif
104	2	mihad	`) ;`
105
106			`input wb_clk_i,`
107			`wb_rst_i,`
108			`wb_cyc_i,`
109			`wb_stb_i,`
110			`wb_we_i ;`
111
112			`input [3:0] wb_sel_i ;`
113
114	15	simons	`input [2:0] wb_adr_i ;`
115	2	mihad
116			`input [31:0] wb_dat_i ;`
117
118			`output [31:0] wb_dat_o ;`
119
120			`output wb_ack_o ;`
121
122			`reg wb_ack_o ;`
123
124			`output wb_int_o ;`
125			`reg wb_int_o ;`
126
127	13	mihad	`input tx_kbd_write_ack_i ;`
128	2	mihad
129			`input [7:0] rx_scancode_i ;`
130	13	mihad	`input rx_kbd_data_ready_i ;`
131			`output rx_kbd_read_o ;`
132	2	mihad
133	13	mihad	`output tx_kbd_write_o ;`
134			`output [7:0] tx_kbd_data_o ;`
135	2	mihad
136			`output translate_o ;`
137	13	mihad	`input ps2_kbd_clk_i ;`
138	2	mihad
139			`output inhibit_kbd_if_o ;`
140
141			`reg [7:0] input_buffer,`
142			`output_buffer ;`
143
144	13	mihad	`reg [7:0] wb_dat_i_sampled ;`
145			`always@(posedge wb_clk_i or posedge wb_rst_i)`
146			`begin`
147			`if ( wb_rst_i )`
148			`wb_dat_i_sampled <= #1 0 ;`
149			`else if ( wb_cyc_i && wb_stb_i && wb_we_i )`
150			`wb_dat_i_sampled <= #1 wb_dat_i[31:24] ;`
151			`end`
152	2	mihad
153	13	mihad	`ifdef PS2_AUX
154			`output wb_intb_o ;`
155			`reg wb_intb_o ;`
156
157			`input [7:0] rx_aux_data_i ;`
158			`input rx_aux_data_ready_i ;`
159			`output rx_aux_read_o ;`
160			`output [7:0] tx_aux_data_o ;`
161			`output tx_aux_write_o ;`
162			`input tx_aux_write_ack_i ;`
163			`input ps2_aux_clk_i ;`
164			`output inhibit_aux_if_o ;`
165			`reg inhibit_aux_if_o ;`
166			`reg aux_output_buffer_full ;`
167			`reg aux_input_buffer_full ;`
168			`reg interrupt2 ;`
169			`reg enable2 ;`
170			`assign tx_aux_data_o = output_buffer ;`
171			`assign tx_aux_write_o = aux_output_buffer_full ;`
172			`else
173			`wire aux_input_buffer_full = 1'b0 ;`
174			`wire aux_output_buffer_full = 1'b0 ;`
175			`wire interrupt2 = 1'b0 ;`
176			`wire enable2 = 1'b1 ;`
177			`endif
178
179			`assign tx_kbd_data_o = output_buffer ;`
180
181	2	mihad	`reg input_buffer_full, // receive buffer`
182			`output_buffer_full ; // transmit buffer`
183
184	13	mihad	`assign tx_kbd_write_o = output_buffer_full ;`
185	2	mihad
186			`wire system_flag ;`
187			`wire a2 = 1'b0 ;`
188	13	mihad	`wire kbd_inhibit = ps2_kbd_clk_i ;`
189	2	mihad	`wire timeout = 1'b0 ;`
190			`wire perr = 1'b0 ;`
191
192	13	mihad	`wire [7:0] status_byte = {perr, timeout, aux_input_buffer_full, kbd_inhibit, a2, system_flag, output_buffer_full \|\| aux_output_buffer_full, input_buffer_full} ;`
193	2	mihad
194			`reg read_input_buffer_reg ;`
195	6	mihad	`wire read_input_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_input_buffer_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h0) ;`
196	2	mihad
197			`reg write_output_buffer_reg ;`
198	6	mihad	`wire write_output_buffer = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !write_output_buffer_reg && wb_we_i && (wb_adr_i[2:0] == 3'h0) ;`
199	2	mihad
200			`reg read_status_register_reg ;`
201	6	mihad	`wire read_status_register = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !read_status_register_reg && !wb_we_i && (wb_adr_i[2:0] == 3'h4) ;`
202	2	mihad
203			`reg send_command_reg ;`
204	6	mihad	`wire send_command = wb_cyc_i && wb_stb_i && wb_sel_i[3] && !wb_ack_o && !send_command_reg && wb_we_i && (wb_adr_i[2:0] == 3'h4) ;`
205	2	mihad
206			`reg translate_o,`
207			`enable1,`
208			`system,`
209			`interrupt1 ;`
210
211			`reg inhibit_kbd_if_o ;`
212			`always@(posedge wb_clk_i or posedge wb_rst_i)`
213			`begin`
214			`if ( wb_rst_i )`
215			`inhibit_kbd_if_o <= #1 1'b1 ;`
216	13	mihad	`else if ( ps2_kbd_clk_i && rx_kbd_data_ready_i && !enable1)`
217	2	mihad	`inhibit_kbd_if_o <= #1 1'b1 ;`
218	13	mihad	`else if ( !rx_kbd_data_ready_i \|\| enable1 )`
219	2	mihad	`inhibit_kbd_if_o <= #1 1'b0 ;`
220	13	mihad
221	2	mihad	`end`
222
223	13	mihad	`ifdef PS2_AUX
224			`always@(posedge wb_clk_i or posedge wb_rst_i)`
225			`begin`
226			`if ( wb_rst_i )`
227			`inhibit_aux_if_o <= #1 1'b1 ;`
228			`else if ( ps2_aux_clk_i && rx_aux_data_ready_i && !enable2 )`
229			`inhibit_aux_if_o <= #1 1'b1 ;`
230			`else if ( !rx_aux_data_ready_i \|\| enable2 )`
231			`inhibit_aux_if_o <= #1 1'b0 ;`
232	2	mihad
233	13	mihad	`end`
234			`endif
235
236	2	mihad	`assign system_flag = system ;`
237
238			`wire [7:0] command_byte = {1'b0, translate_o, enable2, enable1, 1'b0, system, interrupt2, interrupt1} ;`
239
240			`reg [7:0] current_command ;`
241			`reg [7:0] current_command_output ;`
242
243			`always@(posedge wb_clk_i or posedge wb_rst_i)`
244			`begin`
245			`if ( wb_rst_i )`
246			`begin`
247			`send_command_reg <= #1 1'b0 ;`
248			`read_input_buffer_reg <= #1 1'b0 ;`
249			`write_output_buffer_reg <= #1 1'b0 ;`
250			`read_status_register_reg <= #1 1'b0 ;`
251			`end`
252			`else`
253			`begin`
254			`send_command_reg <= #1 send_command ;`
255			`read_input_buffer_reg <= #1 read_input_buffer ;`
256			`write_output_buffer_reg <= #1 write_output_buffer ;`
257			`read_status_register_reg <= #1 read_status_register ;`
258			`end`
259			`end`
260
261			`always@(posedge wb_clk_i or posedge wb_rst_i)`
262			`begin`
263			`if ( wb_rst_i )`
264			`current_command <= #1 8'h0 ;`
265			`else if ( send_command_reg )`
266	13	mihad	`current_command <= #1 wb_dat_i_sampled ;`
267	2	mihad	`end`
268
269			`reg current_command_valid,`
270			`current_command_returns_value,`
271			`current_command_gets_parameter,`
272			`current_command_gets_null_terminated_string ;`
273
274			`reg write_output_buffer_reg_previous ;`
275			`always@(posedge wb_clk_i or posedge wb_rst_i)`
276			`begin`
277			`if ( wb_rst_i )`
278			`write_output_buffer_reg_previous <= #1 1'b0 ;`
279			`else`
280			`write_output_buffer_reg_previous <= #1 write_output_buffer_reg ;`
281			`end`
282
283	13	mihad	`wire invalidate_current_command =`
284			`current_command_valid &&`
285	2	mihad	`(( current_command_returns_value && read_input_buffer_reg && input_buffer_full) \|\|`
286			`( current_command_gets_parameter && write_output_buffer_reg_previous ) \|\|`
287			`( current_command_gets_null_terminated_string && write_output_buffer_reg_previous && (output_buffer == 8'h00) ) \|\|`
288			`( !current_command_returns_value && !current_command_gets_parameter && !current_command_gets_null_terminated_string )`
289			`) ;`
290
291			`always@(posedge wb_clk_i or posedge wb_rst_i)`
292			`begin`
293			`if ( wb_rst_i )`
294			`current_command_valid <= #1 1'b0 ;`
295			`else if ( invalidate_current_command )`
296			`current_command_valid <= #1 1'b0 ;`
297			`else if ( send_command_reg )`
298			`current_command_valid <= #1 1'b1 ;`
299	13	mihad
300	2	mihad	`end`
301
302			`reg write_command_byte ;`
303			`reg current_command_output_valid ;`
304			`always@(`
305			`current_command or`
306			`command_byte or`
307	13	mihad	`write_output_buffer_reg_previous or`
308	2	mihad	`current_command_valid or`
309			`output_buffer`
310			`)`
311			`begin`
312			`current_command_returns_value = 1'b0 ;`
313			`current_command_gets_parameter = 1'b0 ;`
314			`current_command_gets_null_terminated_string = 1'b0 ;`
315			`current_command_output = 8'h00 ;`
316			`write_command_byte = 1'b0 ;`
317			`current_command_output_valid = 1'b0 ;`
318			`case(current_command)`
319			`8'h20:begin`
320			`current_command_returns_value = 1'b1 ;`
321			`current_command_output = command_byte ;`
322			`current_command_output_valid = 1'b1 ;`
323			`end`
324			`8'h60:begin`
325			`current_command_gets_parameter = 1'b1 ;`
326			`write_command_byte = write_output_buffer_reg_previous && current_command_valid ;`
327			`end`
328			`8'hA1:begin`
329			`current_command_returns_value = 1'b1 ;`
330			`current_command_output = 8'h00 ;`
331			`current_command_output_valid = 1'b1 ;`
332	13	mihad	`end`
333	2	mihad	`8'hA4:begin`
334			`current_command_returns_value = 1'b1 ;`
335			`current_command_output = 8'hF1 ;`
336			`current_command_output_valid = 1'b1 ;`
337			`end`
338			`8'hA5:begin`
339			`current_command_gets_null_terminated_string = 1'b1 ;`
340			`end`
341			`8'hA6:begin`
342			`end`
343			`8'hA7:begin`
344	13	mihad	`end`
345	2	mihad	`8'hA8:begin`
346			`end`
347			`8'hA9:begin`
348			`current_command_returns_value = 1'b1 ;`
349	13	mihad	`current_command_output_valid = 1'b1 ;`
350			`ifdef PS2_AUX
351			`current_command_output = 8'h00 ; // interface OK`
352			`else
353	2	mihad	`current_command_output = 8'h02 ; // clock line stuck high`
354	13	mihad	`endif
355	2	mihad	`end`
356			`8'hAA:begin`
357			`current_command_returns_value = 1'b1 ;`
358			`current_command_output = 8'h55 ;`
359			`current_command_output_valid = 1'b1 ;`
360			`end`
361			`8'hAB:begin`
362			`current_command_returns_value = 1'b1 ;`
363			`current_command_output = 8'h00 ;`
364			`current_command_output_valid = 1'b1 ;`
365			`end`
366			`8'hAD:begin`
367	13	mihad	`end`
368	2	mihad	`8'hAE:begin`
369			`end`
370			`8'hAF:begin`
371			`current_command_returns_value = 1'b1 ;`
372			`current_command_output = 8'h00 ;`
373			`current_command_output_valid = 1'b1 ;`
374			`end`
375	13	mihad	`8'hC0:begin`
376	2	mihad	`current_command_returns_value = 1'b1 ;`
377			`current_command_output = 8'hFF ;`
378			`current_command_output_valid = 1'b1 ;`
379			`end`
380			`8'hC1:begin`
381			`end`
382			`8'hC2:begin`
383			`end`
384			`8'hD0:begin`
385			`current_command_returns_value = 1'b1 ;`
386			`current_command_output = 8'h01 ; // only system reset bit is 1`
387			`current_command_output_valid = 1'b1 ;`
388			`end`
389			`8'hD1:begin`
390			`current_command_gets_parameter = 1'b1 ;`
391			`end`
392			`8'hD2:begin`
393	5	mihad	`current_command_returns_value = 1'b1 ;`
394	2	mihad	`current_command_gets_parameter = 1'b1 ;`
395			`current_command_output = output_buffer ;`
396			`current_command_output_valid = write_output_buffer_reg_previous ;`
397			`end`
398			`8'hD3:begin`
399			`current_command_gets_parameter = 1'b1 ;`
400	13	mihad	`ifdef PS2_AUX
401			`current_command_returns_value = 1'b1 ;`
402			`current_command_output = output_buffer ;`
403			`current_command_output_valid = write_output_buffer_reg_previous ;`
404			`endif
405	2	mihad	`end`
406			`8'hD4:begin`
407			`current_command_gets_parameter = 1'b1 ;`
408			`end`
409			`8'hE0:begin`
410			`current_command_returns_value = 1'b1 ;`
411			`current_command_output = 8'hFF ;`
412			`current_command_output_valid = 1'b1 ;`
413			`end`
414	13	mihad	`endcase`
415	2	mihad	`end`
416
417			`reg cyc_i_previous ;`
418			`reg stb_i_previous ;`
419
420			`always@(posedge wb_clk_i or posedge wb_rst_i)`
421			`begin`
422			`if ( wb_rst_i )`
423			`begin`
424			`cyc_i_previous <= #1 1'b0 ;`
425			`stb_i_previous <= #1 1'b0 ;`
426			`end`
427			`else if ( wb_ack_o )`
428			`begin`
429			`cyc_i_previous <= #1 1'b0 ;`
430			`stb_i_previous <= #1 1'b0 ;`
431			`end`
432			`else`
433			`begin`
434			`cyc_i_previous <= #1 wb_cyc_i ;`
435			`stb_i_previous <= #1 wb_stb_i ;`
436			`end`
437	13	mihad
438	2	mihad	`end`
439
440			`always@(posedge wb_clk_i or posedge wb_rst_i)`
441			`begin`
442			`if ( wb_rst_i )`
443			`wb_ack_o <= #1 1'b0 ;`
444			`else if ( wb_ack_o )`
445			`wb_ack_o <= #1 1'b0 ;`
446			`else`
447			`wb_ack_o <= #1 cyc_i_previous && stb_i_previous ;`
448			`end`
449
450			`reg [31:0] wb_dat_o ;`
451			`wire wb_read = read_input_buffer_reg \|\| read_status_register_reg ;`
452
453			`wire [7:0] output_data = read_status_register_reg ? status_byte : input_buffer ;`
454			`always@(posedge wb_clk_i or posedge wb_rst_i)`
455			`begin`
456			`if ( wb_rst_i )`
457			`wb_dat_o <= #1 32'h0 ;`
458			`else if ( wb_read )`
459			`wb_dat_o <= #1 {4{output_data}} ;`
460			`end`
461
462			`always@(posedge wb_clk_i or posedge wb_rst_i)`
463			`begin`
464			`if ( wb_rst_i )`
465			`output_buffer_full <= #1 1'b0 ;`
466	13	mihad	`else if ( output_buffer_full && tx_kbd_write_ack_i \|\| enable1)`
467			`output_buffer_full <= #1 1'b0 ;`
468			`else`
469	2	mihad	`output_buffer_full <= #1 write_output_buffer_reg && (!current_command_valid \|\| (!current_command_gets_parameter && !current_command_gets_null_terminated_string)) ;`
470			`end`
471
472	13	mihad	`ifdef PS2_AUX
473	2	mihad	`always@(posedge wb_clk_i or posedge wb_rst_i)`
474			`begin`
475			`if ( wb_rst_i )`
476	13	mihad	`aux_output_buffer_full <= #1 1'b0 ;`
477			`else if ( aux_output_buffer_full && tx_aux_write_ack_i \|\| enable2)`
478			`aux_output_buffer_full <= #1 1'b0 ;`
479			`else`
480			`aux_output_buffer_full <= #1 write_output_buffer_reg && current_command_valid && (current_command == 8'hD4) ;`
481			`end`
482			`endif
483
484			`always@(posedge wb_clk_i or posedge wb_rst_i)`
485			`begin`
486			`if ( wb_rst_i )`
487	2	mihad	`output_buffer <= #1 8'h00 ;`
488			`else if ( write_output_buffer_reg )`
489	13	mihad	`output_buffer <= #1 wb_dat_i_sampled ;`
490	2	mihad	`end`
491
492			`always@(posedge wb_clk_i or posedge wb_rst_i)`
493			`begin`
494			`if ( wb_rst_i )`
495			`begin`
496			`translate_o <= #1 1'b0 ;`
497			`system <= #1 1'b0 ;`
498			`interrupt1 <= #1 1'b0 ;`
499	13	mihad	`ifdef PS2_AUX
500			`interrupt2 <= #1 1'b0 ;`

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