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[/] [ps2_host_controller/] [trunk/] [hdl/] [ps2_host_rx.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ps2_host_rx.v                                               ////
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////                                                              ////
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////  Description                                                 ////
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////  Receiver part, gathering bits from the ps2_data line        ////
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////                                                              ////
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////  Author:                                                     ////
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////      - Piotr Foltyn, piotr.foltyn@gmail.com                  ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2011 Author                                    ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module ps2_host_rx(
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  input  wire sys_clk,
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  input  wire sys_rst,
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  input  wire ps2_clk_negedge,
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  input  wire ps2_data,
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  output wire [7:0] rx_data,
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  output wire ready,
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  output wire error
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);
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// Read in 11 bit long frame. 12th bit marks end of frame.
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reg [11:0] frame;
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always @(posedge sys_clk)
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begin
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  if (sys_rst | ready) begin
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    frame <= 1;
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  end
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  else begin
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    frame <= (ps2_clk_negedge) ? {frame[10:0], ps2_data} : frame;
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  end
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end
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// Return rx_data in most significant bit first order.
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assign rx_data = {frame[2], frame[3], frame[4], frame[5],
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                  frame[6], frame[7], frame[8], frame[9]};
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// 12th bit marks end of frame.
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assign ready = frame[11];
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// Check that 1st bit is 0, odd parity bit is correct and last bit is 1.
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assign error = ~(~frame[10] & (~frame[1] == ^frame[9:2]) & frame[0]);
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endmodule

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