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Subversion Repositories ps2_keyboard_interface

[/] [ps2_keyboard_interface/] [Keyboard_Controller.syr] - Blame information for rev 2

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Release 12.3 - xst M.70d (lin64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
 
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
 
-->
Reading design: Keyboard_Controller.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Keyboard_Controller.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "Keyboard_Controller"
Output Format                      : NGC
Target Device                      : xc3s200-5-ft256
 
---- Source Options
Top Module Name                    : Keyboard_Controller
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/omar/Mano/Mano/SevenSegment.vhd" in Library work.
Architecture behavioral of Entity sevensegment is up to date.
Compiling vhdl file "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd" in Library work.
Entity  compiled.
Entity  (Architecture ) compiled.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "/home/omar/Mano/Mano/SevenSegment.vhd".
    Found 16x8-bit ROM for signal .
    Found 1-of-4 decoder for signal .
    Found 4-bit 4-to-1 multiplexer for signal .
    Found 13-bit up counter for signal .
    Summary:
        inferred   1 ROM(s).
        inferred   1 Counter(s).
        inferred   4 Multiplexer(s).
        inferred   1 Decoder(s).
Unit  synthesized.
 
 
Synthesizing Unit .
    Related source file is "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd".
WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 5-bit up counter for signal .
    Found 21-bit register for signal >.
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit up counter for signal .
    Summary:
        inferred   2 Counter(s).
        inferred  37 D-type flip-flop(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1
# Counters                                             : 3
 13-bit up counter                                     : 1
 5-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 23
 1-bit register                                        : 21
 8-bit register                                        : 2
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-4 decoder                                        : 1
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# ROMs                                                 : 1
 16x8-bit ROM                                          : 1
# Counters                                             : 3
 13-bit up counter                                     : 1
 5-bit up counter                                      : 1
 8-bit up counter                                      : 1
# Registers                                            : 37
 Flip-Flops                                            : 37
# Multiplexers                                         : 1
 4-bit 4-to-1 multiplexer                              : 1
# Decoders                                             : 1
 1-of-4 decoder                                        : 1
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Keyboard_Controller, actual ratio is 2.
 
Final Macro Processing ...
 
Processing Unit  :
        Found 3-bit shift register for signal .
        Found 4-bit shift register for signal .
Unit  processed.
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 56
 Flip-Flops                                            : 56
# Shift Registers                                      : 2
 3-bit shift register                                  : 1
 4-bit shift register                                  : 1
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : Keyboard_Controller.ngr
Top Level Output File Name         : Keyboard_Controller
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 23
 
Cell Usage :
# BELS                             : 97
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 19
#      LUT2                        : 5
#      LUT2_D                      : 1
#      LUT3                        : 10
#      LUT3_L                      : 1
#      LUT4                        : 11
#      MUXCY                       : 19
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 21
# FlipFlops/Latches                : 58
#      FD                          : 13
#      FD_1                        : 16
#      FDE                         : 8
#      FDE_1                       : 16
#      FDR                         : 5
# Shift Registers                  : 2
#      SRL16_1                     : 2
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 21
#      IBUF                        : 1
#      OBUF                        : 20
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s200ft256-5
 
 Number of Slices:                       40  out of   1920     2%
 Number of Slice Flip Flops:             58  out of   3840     1%
 Number of 4 input LUTs:                 53  out of   3840     1%
    Number used as logic:                51
    Number used as Shift registers:       2
 Number of IOs:                          23
 Number of bonded IOBs:                  23  out of    173    13%
 Number of GCLKs:                         2  out of      8    25%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 47    |
Clk2                               | BUFGP                  | 13    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -5
 
   Minimum period: 5.006ns (Maximum Frequency: 199.770MHz)
   Minimum input arrival time before clock: 1.778ns
   Maximum output required time after clock: 9.978ns
   Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
  Clock period: 5.006ns (frequency: 199.770MHz)
  Total number of paths / destination ports: 229 / 75
-------------------------------------------------------------------------
Delay:               5.006ns (Levels of Logic = 2)
  Source:            Counter_1 (FF)
  Destination:       OutByte1_0 (FF)
  Source Clock:      Clk falling
  Destination Clock: Clk falling
 
  Data Path: Counter_1 to OutByte1_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   0.626   1.078  Counter_1 (Counter_1)
     LUT2_D:I0->O          2   0.479   0.768  OutByte1_cmp_eq0000_SW0 (N14)
     LUT4:I3->O           16   0.479   1.051  OutByte1_cmp_eq0000_1 (OutByte1_cmp_eq00001)
     FDE_1:CE                  0.524          OutByte2_0
    ----------------------------------------
    Total                      5.006ns (2.108ns logic, 2.898ns route)
                                       (42.1% logic, 57.9% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'Clk2'
  Clock period: 4.033ns (frequency: 247.964MHz)
  Total number of paths / destination ports: 91 / 13
-------------------------------------------------------------------------
Delay:               4.033ns (Levels of Logic = 13)
  Source:            Inst_SevenSegment/Counter_1 (FF)
  Destination:       Inst_SevenSegment/Counter_12 (FF)
  Source Clock:      Clk2 rising
  Destination Clock: Clk2 rising
 
  Data Path: Inst_SevenSegment/Counter_1 to Inst_SevenSegment/Counter_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.626   0.976  Inst_SevenSegment/Counter_1 (Inst_SevenSegment/Counter_1)
     LUT1:I0->O            1   0.479   0.000  Inst_SevenSegment/Mcount_Counter_cy<1>_rt (Inst_SevenSegment/Mcount_Counter_cy<1>_rt)
     MUXCY:S->O            1   0.435   0.000  Inst_SevenSegment/Mcount_Counter_cy<1> (Inst_SevenSegment/Mcount_Counter_cy<1>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<2> (Inst_SevenSegment/Mcount_Counter_cy<2>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<3> (Inst_SevenSegment/Mcount_Counter_cy<3>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<4> (Inst_SevenSegment/Mcount_Counter_cy<4>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<5> (Inst_SevenSegment/Mcount_Counter_cy<5>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<6> (Inst_SevenSegment/Mcount_Counter_cy<6>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<7> (Inst_SevenSegment/Mcount_Counter_cy<7>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<8> (Inst_SevenSegment/Mcount_Counter_cy<8>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<9> (Inst_SevenSegment/Mcount_Counter_cy<9>)
     MUXCY:CI->O           1   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<10> (Inst_SevenSegment/Mcount_Counter_cy<10>)
     MUXCY:CI->O           0   0.056   0.000  Inst_SevenSegment/Mcount_Counter_cy<11> (Inst_SevenSegment/Mcount_Counter_cy<11>)
     XORCY:CI->O           1   0.786   0.000  Inst_SevenSegment/Mcount_Counter_xor<12> (Result<12>)
     FD:D                      0.176          Inst_SevenSegment/Counter_12
    ----------------------------------------
    Total                      4.033ns (3.057ns logic, 0.976ns route)
                                       (75.8% logic, 24.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              1.778ns (Levels of Logic = 1)
  Source:            DataIn (PAD)
  Destination:       Mshreg_data_2 (FF)
  Destination Clock: Clk falling
 
  Data Path: DataIn to Mshreg_data_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  DataIn_IBUF (DataIn_IBUF)
     SRL16_1:D                 0.382          Mshreg_data_2
    ----------------------------------------
    Total                      1.778ns (1.097ns logic, 0.681ns route)
                                       (61.7% logic, 38.3% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk2'
  Total number of paths / destination ports: 92 / 11
-------------------------------------------------------------------------
Offset:              9.978ns (Levels of Logic = 4)
  Source:            Inst_SevenSegment/Counter_11 (FF)
  Destination:       Segments<6> (PAD)
  Source Clock:      Clk2 rising
 
  Data Path: Inst_SevenSegment/Counter_11 to Segments<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              13   0.626   1.290  Inst_SevenSegment/Counter_11 (Inst_SevenSegment/Counter_11)
     LUT3:I0->O            1   0.479   0.000  Inst_SevenSegment/Mmux_Chosen_3 (Inst_SevenSegment/Mmux_Chosen_3)
     MUXF5:I1->O           7   0.314   1.201  Inst_SevenSegment/Mmux_Chosen_2_f5 (Inst_SevenSegment/Chosen<0>)
     LUT4:I0->O            1   0.479   0.681  Inst_SevenSegment/Mrom_Segments111 (Segments_1_OBUF)
     OBUF:I->O                 4.909          Segments_1_OBUF (Segments<1>)
    ----------------------------------------
    Total                      9.978ns (6.807ns logic, 3.171ns route)
                                       (68.2% logic, 31.8% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
  Total number of paths / destination ports: 120 / 15
-------------------------------------------------------------------------
Offset:              9.540ns (Levels of Logic = 4)
  Source:            OutByte1_5 (FF)
  Destination:       Segments<6> (PAD)
  Source Clock:      Clk falling
 
  Data Path: OutByte1_5 to Segments<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   0.626   0.851  OutByte1_5 (OutByte1_5)
     LUT3:I1->O            1   0.479   0.000  Inst_SevenSegment/Mmux_Chosen_41 (Inst_SevenSegment/Mmux_Chosen_41)
     MUXF5:I0->O           7   0.314   1.201  Inst_SevenSegment/Mmux_Chosen_2_f5_0 (Inst_SevenSegment/Chosen<1>)
     LUT4:I0->O            1   0.479   0.681  Inst_SevenSegment/Mrom_Segments21 (Segments_2_OBUF)
     OBUF:I->O                 4.909          Segments_2_OBUF (Segments<2>)
    ----------------------------------------
    Total                      9.540ns (6.807ns logic, 2.733ns route)
                                       (71.4% logic, 28.6% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.77 secs
 
-->
 
 
Total memory usage is 339112 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 

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Subversion Repositories ps2_keyboard_interface

[/] [ps2_keyboard_interface/] [Keyboard_Controller.syr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	OmarMokhta	`Release 12.3 - xst M.70d (lin64)`
2			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`
3			`-->`
4			`Parameter TMPDIR set to xst/projnav.tmp`
5
6
7			`Total REAL time to Xst completion: 0.00 secs`
8			`Total CPU time to Xst completion: 0.04 secs`
9
10			`-->`
11			`Parameter xsthdpdir set to xst`
12
13
14			`Total REAL time to Xst completion: 0.00 secs`
15			`Total CPU time to Xst completion: 0.04 secs`
16
17			`-->`
18			`Reading design: Keyboard_Controller.prj`
19
20			`TABLE OF CONTENTS`
21			`1) Synthesis Options Summary`
22			`2) HDL Compilation`
23			`3) Design Hierarchy Analysis`
24			`4) HDL Analysis`
25			`5) HDL Synthesis`
26			`5.1) HDL Synthesis Report`
27			`6) Advanced HDL Synthesis`
28			`6.1) Advanced HDL Synthesis Report`
29			`7) Low Level Synthesis`
30			`8) Partition Report`
31			`9) Final Report`
32			`9.1) Device utilization summary`
33			`9.2) Partition Resource Summary`
34			`9.3) TIMING REPORT`
35
36
37			`=========================================================================`
38			`* Synthesis Options Summary *`
39			`=========================================================================`
40			`---- Source Parameters`
41			`Input File Name : "Keyboard_Controller.prj"`
42			`Input Format : mixed`
43			`Ignore Synthesis Constraint File : NO`
44
45			`---- Target Parameters`
46			`Output File Name : "Keyboard_Controller"`
47			`Output Format : NGC`
48			`Target Device : xc3s200-5-ft256`
49
50			`---- Source Options`
51			`Top Module Name : Keyboard_Controller`
52			`Automatic FSM Extraction : YES`
53			`FSM Encoding Algorithm : Auto`
54			`Safe Implementation : No`
55			`FSM Style : LUT`
56			`RAM Extraction : Yes`
57			`RAM Style : Auto`
58			`ROM Extraction : Yes`
59			`Mux Style : Auto`
60			`Decoder Extraction : YES`
61			`Priority Encoder Extraction : Yes`
62			`Shift Register Extraction : YES`
63			`Logical Shifter Extraction : YES`
64			`XOR Collapsing : YES`
65			`ROM Style : Auto`
66			`Mux Extraction : Yes`
67			`Resource Sharing : YES`
68			`Asynchronous To Synchronous : NO`
69			`Multiplier Style : Auto`
70			`Automatic Register Balancing : No`
71
72			`---- Target Options`
73			`Add IO Buffers : YES`
74			`Global Maximum Fanout : 500`
75			`Add Generic Clock Buffer(BUFG) : 8`
76			`Register Duplication : YES`
77			`Slice Packing : YES`
78			`Optimize Instantiated Primitives : NO`
79			`Use Clock Enable : Yes`
80			`Use Synchronous Set : Yes`
81			`Use Synchronous Reset : Yes`
82			`Pack IO Registers into IOBs : Auto`
83			`Equivalent register Removal : YES`
84
85			`---- General Options`
86			`Optimization Goal : Speed`
87			`Optimization Effort : 1`
88			`Keep Hierarchy : No`
89			`Netlist Hierarchy : As_Optimized`
90			`RTL Output : Yes`
91			`Global Optimization : AllClockNets`
92			`Read Cores : YES`
93			`Write Timing Constraints : NO`
94			`Cross Clock Analysis : NO`
95			`Hierarchy Separator : /`
96			`Bus Delimiter : <>`
97			`Case Specifier : Maintain`
98			`Slice Utilization Ratio : 100`
99			`BRAM Utilization Ratio : 100`
100			`Verilog 2001 : YES`
101			`Auto BRAM Packing : NO`
102			`Slice Utilization Ratio Delta : 5`
103
104			`=========================================================================`
105
106
107			`=========================================================================`
108			`* HDL Compilation *`
109			`=========================================================================`
110			`Compiling vhdl file "/home/omar/Mano/Mano/SevenSegment.vhd" in Library work.`
111			`Architecture behavioral of Entity sevensegment is up to date.`
112			`Compiling vhdl file "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd" in Library work.`
113			`Entity compiled.`
114			`Entity (Architecture ) compiled.`
115
116			`=========================================================================`
117			`* Design Hierarchy Analysis *`
118			`=========================================================================`
119			`Analyzing hierarchy for entity in library (architecture ).`
120
121			`Analyzing hierarchy for entity in library (architecture ).`
122
123
124			`=========================================================================`
125			`* HDL Analysis *`
126			`=========================================================================`
127			`Analyzing Entity in library (Architecture ).`
128			`Entity analyzed. Unit generated.`
129
130			`Analyzing Entity in library (Architecture ).`
131			`Entity analyzed. Unit generated.`
132
133
134			`=========================================================================`
135			`* HDL Synthesis *`
136			`=========================================================================`
137
138			`Performing bidirectional port resolution...`
139
140			`Synthesizing Unit .`
141			`Related source file is "/home/omar/Mano/Mano/SevenSegment.vhd".`
142			`Found 16x8-bit ROM for signal .`
143			`Found 1-of-4 decoder for signal .`
144			`Found 4-bit 4-to-1 multiplexer for signal .`
145			`Found 13-bit up counter for signal .`
146			`Summary:`
147			`inferred 1 ROM(s).`
148			`inferred 1 Counter(s).`
149			`inferred 4 Multiplexer(s).`
150			`inferred 1 Decoder(s).`
151			`Unit synthesized.`
152
153
154			`Synthesizing Unit .`
155			`Related source file is "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd".`
156			`WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.`
157			`Found 5-bit up counter for signal .`
158			`Found 21-bit register for signal >.`
159			`Found 8-bit register for signal .`
160			`Found 8-bit register for signal .`
161			`Found 8-bit up counter for signal .`
162			`Summary:`
163			`inferred 2 Counter(s).`
164			`inferred 37 D-type flip-flop(s).`
165			`Unit synthesized.`
166
167
168			`=========================================================================`
169			`HDL Synthesis Report`
170
171			`Macro Statistics`
172			`# ROMs : 1`
173			`16x8-bit ROM : 1`
174			`# Counters : 3`
175			`13-bit up counter : 1`
176			`5-bit up counter : 1`
177			`8-bit up counter : 1`
178			`# Registers : 23`
179			`1-bit register : 21`
180			`8-bit register : 2`
181			`# Multiplexers : 1`
182			`4-bit 4-to-1 multiplexer : 1`
183			`# Decoders : 1`
184			`1-of-4 decoder : 1`
185
186			`=========================================================================`
187
188			`=========================================================================`
189			`* Advanced HDL Synthesis *`
190			`=========================================================================`
191
192
193			`=========================================================================`
194			`Advanced HDL Synthesis Report`
195
196			`Macro Statistics`
197			`# ROMs : 1`
198			`16x8-bit ROM : 1`
199			`# Counters : 3`
200			`13-bit up counter : 1`
201			`5-bit up counter : 1`
202			`8-bit up counter : 1`
203			`# Registers : 37`
204			`Flip-Flops : 37`
205			`# Multiplexers : 1`
206			`4-bit 4-to-1 multiplexer : 1`
207			`# Decoders : 1`
208			`1-of-4 decoder : 1`
209
210			`=========================================================================`
211
212			`=========================================================================`
213			`* Low Level Synthesis *`
214			`=========================================================================`
215
216			`Optimizing unit ...`
217
218			`Mapping all equations...`
219			`Building and optimizing final netlist ...`
220			`Found area constraint ratio of 100 (+ 5) on block Keyboard_Controller, actual ratio is 2.`
221
222			`Final Macro Processing ...`
223
224			`Processing Unit :`
225			`Found 3-bit shift register for signal .`
226			`Found 4-bit shift register for signal .`
227			`Unit processed.`
228
229			`=========================================================================`
230			`Final Register Report`
231
232			`Macro Statistics`
233			`# Registers : 56`
234			`Flip-Flops : 56`
235			`# Shift Registers : 2`
236			`3-bit shift register : 1`
237			`4-bit shift register : 1`
238
239			`=========================================================================`
240
241			`=========================================================================`
242			`* Partition Report *`
243			`=========================================================================`
244
245			`Partition Implementation Status`
246			`-------------------------------`
247
248			`No Partitions were found in this design.`
249
250			`-------------------------------`
251
252			`=========================================================================`
253			`* Final Report *`
254			`=========================================================================`
255			`Final Results`
256			`RTL Top Level Output File Name : Keyboard_Controller.ngr`
257			`Top Level Output File Name : Keyboard_Controller`
258			`Output Format : NGC`
259			`Optimization Goal : Speed`
260			`Keep Hierarchy : No`
261
262			`Design Statistics`
263			`# IOs : 23`
264
265			`Cell Usage :`
266			`# BELS : 97`
267			`# GND : 1`
268			`# INV : 4`
269			`# LUT1 : 19`
270			`# LUT2 : 5`
271			`# LUT2_D : 1`
272			`# LUT3 : 10`
273			`# LUT3_L : 1`
274			`# LUT4 : 11`
275			`# MUXCY : 19`
276			`# MUXF5 : 4`
277			`# VCC : 1`
278			`# XORCY : 21`
279			`# FlipFlops/Latches : 58`
280			`# FD : 13`
281			`# FD_1 : 16`
282			`# FDE : 8`
283			`# FDE_1 : 16`
284			`# FDR : 5`
285			`# Shift Registers : 2`
286			`# SRL16_1 : 2`
287			`# Clock Buffers : 2`
288			`# BUFGP : 2`
289			`# IO Buffers : 21`
290			`# IBUF : 1`
291			`# OBUF : 20`
292			`=========================================================================`
293
294			`Device utilization summary:`
295			`---------------------------`
296
297			`Selected Device : 3s200ft256-5`
298
299			`Number of Slices: 40 out of 1920 2%`
300			`Number of Slice Flip Flops: 58 out of 3840 1%`
301			`Number of 4 input LUTs: 53 out of 3840 1%`
302			`Number used as logic: 51`
303			`Number used as Shift registers: 2`
304			`Number of IOs: 23`
305			`Number of bonded IOBs: 23 out of 173 13%`
306			`Number of GCLKs: 2 out of 8 25%`
307
308			`---------------------------`
309			`Partition Resource Summary:`
310			`---------------------------`
311
312			`No Partitions were found in this design.`
313
314			`---------------------------`
315
316
317			`=========================================================================`
318			`TIMING REPORT`
319
320			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
321			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
322			`GENERATED AFTER PLACE-and-ROUTE.`
323
324			`Clock Information:`
325			`------------------`
326			`-----------------------------------+------------------------+-------+`
327			`Clock Signal \| Clock buffer(FF name) \| Load \|`
328			`-----------------------------------+------------------------+-------+`
329			`Clk \| BUFGP \| 47 \|`
330			`Clk2 \| BUFGP \| 13 \|`
331			`-----------------------------------+------------------------+-------+`
332
333			`Asynchronous Control Signals Information:`
334			`----------------------------------------`
335			`No asynchronous control signals found in this design`
336
337			`Timing Summary:`
338			`---------------`
339			`Speed Grade: -5`
340
341			`Minimum period: 5.006ns (Maximum Frequency: 199.770MHz)`
342			`Minimum input arrival time before clock: 1.778ns`
343			`Maximum output required time after clock: 9.978ns`
344			`Maximum combinational path delay: No path found`
345
346			`Timing Detail:`
347			`--------------`
348			`All values displayed in nanoseconds (ns)`
349
350			`=========================================================================`
351			`Timing constraint: Default period analysis for Clock 'Clk'`
352			`Clock period: 5.006ns (frequency: 199.770MHz)`
353			`Total number of paths / destination ports: 229 / 75`
354			`-------------------------------------------------------------------------`
355			`Delay: 5.006ns (Levels of Logic = 2)`
356			`Source: Counter_1 (FF)`
357			`Destination: OutByte1_0 (FF)`
358			`Source Clock: Clk falling`
359			`Destination Clock: Clk falling`
360
361			`Data Path: Counter_1 to OutByte1_0`
362			`Gate Net`
363			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
364			`---------------------------------------- ------------`
365			`FDR:C->Q 5 0.626 1.078 Counter_1 (Counter_1)`
366			`LUT2_D:I0->O 2 0.479 0.768 OutByte1_cmp_eq0000_SW0 (N14)`
367			`LUT4:I3->O 16 0.479 1.051 OutByte1_cmp_eq0000_1 (OutByte1_cmp_eq00001)`
368			`FDE_1:CE 0.524 OutByte2_0`
369			`----------------------------------------`
370			`Total 5.006ns (2.108ns logic, 2.898ns route)`
371			`(42.1% logic, 57.9% route)`
372
373			`=========================================================================`
374			`Timing constraint: Default period analysis for Clock 'Clk2'`
375			`Clock period: 4.033ns (frequency: 247.964MHz)`
376			`Total number of paths / destination ports: 91 / 13`
377			`-------------------------------------------------------------------------`
378			`Delay: 4.033ns (Levels of Logic = 13)`
379			`Source: Inst_SevenSegment/Counter_1 (FF)`
380			`Destination: Inst_SevenSegment/Counter_12 (FF)`
381			`Source Clock: Clk2 rising`
382			`Destination Clock: Clk2 rising`
383
384			`Data Path: Inst_SevenSegment/Counter_1 to Inst_SevenSegment/Counter_12`
385			`Gate Net`
386			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
387			`---------------------------------------- ------------`
388			`FD:C->Q 1 0.626 0.976 Inst_SevenSegment/Counter_1 (Inst_SevenSegment/Counter_1)`
389			`LUT1:I0->O 1 0.479 0.000 Inst_SevenSegment/Mcount_Counter_cy<1>_rt (Inst_SevenSegment/Mcount_Counter_cy<1>_rt)`
390			`MUXCY:S->O 1 0.435 0.000 Inst_SevenSegment/Mcount_Counter_cy<1> (Inst_SevenSegment/Mcount_Counter_cy<1>)`
391			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<2> (Inst_SevenSegment/Mcount_Counter_cy<2>)`
392			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<3> (Inst_SevenSegment/Mcount_Counter_cy<3>)`
393			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<4> (Inst_SevenSegment/Mcount_Counter_cy<4>)`
394			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<5> (Inst_SevenSegment/Mcount_Counter_cy<5>)`
395			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<6> (Inst_SevenSegment/Mcount_Counter_cy<6>)`
396			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<7> (Inst_SevenSegment/Mcount_Counter_cy<7>)`
397			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<8> (Inst_SevenSegment/Mcount_Counter_cy<8>)`
398			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<9> (Inst_SevenSegment/Mcount_Counter_cy<9>)`
399			`MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<10> (Inst_SevenSegment/Mcount_Counter_cy<10>)`
400			`MUXCY:CI->O 0 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<11> (Inst_SevenSegment/Mcount_Counter_cy<11>)`
401			`XORCY:CI->O 1 0.786 0.000 Inst_SevenSegment/Mcount_Counter_xor<12> (Result<12>)`
402			`FD:D 0.176 Inst_SevenSegment/Counter_12`
403			`----------------------------------------`
404			`Total 4.033ns (3.057ns logic, 0.976ns route)`
405			`(75.8% logic, 24.2% route)`
406
407			`=========================================================================`
408			`Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'`
409			`Total number of paths / destination ports: 1 / 1`
410			`-------------------------------------------------------------------------`
411			`Offset: 1.778ns (Levels of Logic = 1)`
412			`Source: DataIn (PAD)`
413			`Destination: Mshreg_data_2 (FF)`
414			`Destination Clock: Clk falling`
415
416			`Data Path: DataIn to Mshreg_data_2`
417			`Gate Net`
418			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
419			`---------------------------------------- ------------`
420			`IBUF:I->O 1 0.715 0.681 DataIn_IBUF (DataIn_IBUF)`
421			`SRL16_1:D 0.382 Mshreg_data_2`
422			`----------------------------------------`
423			`Total 1.778ns (1.097ns logic, 0.681ns route)`
424			`(61.7% logic, 38.3% route)`
425
426			`=========================================================================`
427			`Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk2'`
428			`Total number of paths / destination ports: 92 / 11`
429			`-------------------------------------------------------------------------`
430			`Offset: 9.978ns (Levels of Logic = 4)`
431			`Source: Inst_SevenSegment/Counter_11 (FF)`
432			`Destination: Segments<6> (PAD)`
433			`Source Clock: Clk2 rising`
434
435			`Data Path: Inst_SevenSegment/Counter_11 to Segments<6>`
436			`Gate Net`
437			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
438			`---------------------------------------- ------------`
439			`FD:C->Q 13 0.626 1.290 Inst_SevenSegment/Counter_11 (Inst_SevenSegment/Counter_11)`
440			`LUT3:I0->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_3 (Inst_SevenSegment/Mmux_Chosen_3)`
441			`MUXF5:I1->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5 (Inst_SevenSegment/Chosen<0>)`
442			`LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments111 (Segments_1_OBUF)`
443			`OBUF:I->O 4.909 Segments_1_OBUF (Segments<1>)`
444			`----------------------------------------`
445			`Total 9.978ns (6.807ns logic, 3.171ns route)`
446			`(68.2% logic, 31.8% route)`
447
448			`=========================================================================`
449			`Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'`
450			`Total number of paths / destination ports: 120 / 15`
451			`-------------------------------------------------------------------------`
452			`Offset: 9.540ns (Levels of Logic = 4)`
453			`Source: OutByte1_5 (FF)`
454			`Destination: Segments<6> (PAD)`
455			`Source Clock: Clk falling`
456
457			`Data Path: OutByte1_5 to Segments<6>`
458			`Gate Net`
459			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
460			`---------------------------------------- ------------`
461			`FDE_1:C->Q 1 0.626 0.851 OutByte1_5 (OutByte1_5)`
462			`LUT3:I1->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_41 (Inst_SevenSegment/Mmux_Chosen_41)`
463			`MUXF5:I0->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5_0 (Inst_SevenSegment/Chosen<1>)`
464			`LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments21 (Segments_2_OBUF)`
465			`OBUF:I->O 4.909 Segments_2_OBUF (Segments<2>)`
466			`----------------------------------------`
467			`Total 9.540ns (6.807ns logic, 2.733ns route)`
468			`(71.4% logic, 28.6% route)`
469
470			`=========================================================================`
471
472
473			`Total REAL time to Xst completion: 5.00 secs`
474			`Total CPU time to Xst completion: 4.77 secs`
475
476			`-->`
477
478
479			`Total memory usage is 339112 kilobytes`
480
481			`Number of errors : 0 ( 0 filtered)`
482			`Number of warnings : 1 ( 0 filtered)`
483			`Number of infos : 0 ( 0 filtered)`
484