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OmarMokhta |
Release 12.3 - xst M.70d (lin64)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.04 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.04 secs
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-->
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Reading design: Keyboard_Controller.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "Keyboard_Controller.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "Keyboard_Controller"
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Output Format : NGC
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Target Device : xc3s200-5-ft256
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---- Source Options
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Top Module Name : Keyboard_Controller
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/omar/Mano/Mano/SevenSegment.vhd" in Library work.
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Architecture behavioral of Entity sevensegment is up to date.
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Compiling vhdl file "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd" in Library work.
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Entity compiled.
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Entity (Architecture ) compiled.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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Analyzing Entity in library (Architecture ).
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Entity analyzed. Unit generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "/home/omar/Mano/Mano/SevenSegment.vhd".
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Found 16x8-bit ROM for signal .
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Found 1-of-4 decoder for signal .
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Found 4-bit 4-to-1 multiplexer for signal .
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Found 13-bit up counter for signal .
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Summary:
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inferred 1 ROM(s).
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inferred 1 Counter(s).
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inferred 4 Multiplexer(s).
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inferred 1 Decoder(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd".
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found 5-bit up counter for signal .
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Found 21-bit register for signal >.
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit up counter for signal .
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Summary:
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inferred 2 Counter(s).
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inferred 37 D-type flip-flop(s).
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# ROMs : 1
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16x8-bit ROM : 1
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# Counters : 3
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13-bit up counter : 1
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5-bit up counter : 1
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8-bit up counter : 1
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# Registers : 23
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1-bit register : 21
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8-bit register : 2
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# Multiplexers : 1
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4-bit 4-to-1 multiplexer : 1
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# Decoders : 1
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1-of-4 decoder : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# ROMs : 1
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16x8-bit ROM : 1
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# Counters : 3
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13-bit up counter : 1
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5-bit up counter : 1
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8-bit up counter : 1
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# Registers : 37
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Flip-Flops : 37
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# Multiplexers : 1
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4-bit 4-to-1 multiplexer : 1
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# Decoders : 1
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1-of-4 decoder : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block Keyboard_Controller, actual ratio is 2.
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Final Macro Processing ...
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Processing Unit :
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Found 3-bit shift register for signal .
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Found 4-bit shift register for signal .
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Unit processed.
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 56
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Flip-Flops : 56
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# Shift Registers : 2
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3-bit shift register : 1
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4-bit shift register : 1
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : Keyboard_Controller.ngr
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Top Level Output File Name : Keyboard_Controller
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 23
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Cell Usage :
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# BELS : 97
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# GND : 1
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# INV : 4
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# LUT1 : 19
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# LUT2 : 5
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# LUT2_D : 1
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# LUT3 : 10
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# LUT3_L : 1
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# LUT4 : 11
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# MUXCY : 19
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# MUXF5 : 4
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# VCC : 1
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# XORCY : 21
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# FlipFlops/Latches : 58
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# FD : 13
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# FD_1 : 16
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# FDE : 8
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# FDE_1 : 16
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# FDR : 5
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# Shift Registers : 2
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# SRL16_1 : 2
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# Clock Buffers : 2
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# BUFGP : 2
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# IO Buffers : 21
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# IBUF : 1
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# OBUF : 20
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=========================================================================
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Device utilization summary:
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---------------------------
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Selected Device : 3s200ft256-5
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Number of Slices: 40 out of 1920 2%
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Number of Slice Flip Flops: 58 out of 3840 1%
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Number of 4 input LUTs: 53 out of 3840 1%
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Number used as logic: 51
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Number used as Shift registers: 2
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Number of IOs: 23
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Number of bonded IOBs: 23 out of 173 13%
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Number of GCLKs: 2 out of 8 25%
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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TIMING REPORT
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------+------------------------+-------+
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Clk | BUFGP | 47 |
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Clk2 | BUFGP | 13 |
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-----------------------------------+------------------------+-------+
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -5
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Minimum period: 5.006ns (Maximum Frequency: 199.770MHz)
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Minimum input arrival time before clock: 1.778ns
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Maximum output required time after clock: 9.978ns
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Maximum combinational path delay: No path found
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Timing Detail:
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--------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'Clk'
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Clock period: 5.006ns (frequency: 199.770MHz)
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Total number of paths / destination ports: 229 / 75
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-------------------------------------------------------------------------
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Delay: 5.006ns (Levels of Logic = 2)
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Source: Counter_1 (FF)
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Destination: OutByte1_0 (FF)
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Source Clock: Clk falling
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Destination Clock: Clk falling
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Data Path: Counter_1 to OutByte1_0
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDR:C->Q 5 0.626 1.078 Counter_1 (Counter_1)
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LUT2_D:I0->O 2 0.479 0.768 OutByte1_cmp_eq0000_SW0 (N14)
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LUT4:I3->O 16 0.479 1.051 OutByte1_cmp_eq0000_1 (OutByte1_cmp_eq00001)
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FDE_1:CE 0.524 OutByte2_0
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----------------------------------------
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Total 5.006ns (2.108ns logic, 2.898ns route)
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(42.1% logic, 57.9% route)
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=========================================================================
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Timing constraint: Default period analysis for Clock 'Clk2'
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Clock period: 4.033ns (frequency: 247.964MHz)
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Total number of paths / destination ports: 91 / 13
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-------------------------------------------------------------------------
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Delay: 4.033ns (Levels of Logic = 13)
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Source: Inst_SevenSegment/Counter_1 (FF)
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Destination: Inst_SevenSegment/Counter_12 (FF)
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Source Clock: Clk2 rising
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Destination Clock: Clk2 rising
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Data Path: Inst_SevenSegment/Counter_1 to Inst_SevenSegment/Counter_12
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FD:C->Q 1 0.626 0.976 Inst_SevenSegment/Counter_1 (Inst_SevenSegment/Counter_1)
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LUT1:I0->O 1 0.479 0.000 Inst_SevenSegment/Mcount_Counter_cy<1>_rt (Inst_SevenSegment/Mcount_Counter_cy<1>_rt)
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MUXCY:S->O 1 0.435 0.000 Inst_SevenSegment/Mcount_Counter_cy<1> (Inst_SevenSegment/Mcount_Counter_cy<1>)
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MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<2> (Inst_SevenSegment/Mcount_Counter_cy<2>)
|
392 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<3> (Inst_SevenSegment/Mcount_Counter_cy<3>)
|
393 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<4> (Inst_SevenSegment/Mcount_Counter_cy<4>)
|
394 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<5> (Inst_SevenSegment/Mcount_Counter_cy<5>)
|
395 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<6> (Inst_SevenSegment/Mcount_Counter_cy<6>)
|
396 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<7> (Inst_SevenSegment/Mcount_Counter_cy<7>)
|
397 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<8> (Inst_SevenSegment/Mcount_Counter_cy<8>)
|
398 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<9> (Inst_SevenSegment/Mcount_Counter_cy<9>)
|
399 |
|
|
MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<10> (Inst_SevenSegment/Mcount_Counter_cy<10>)
|
400 |
|
|
MUXCY:CI->O 0 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<11> (Inst_SevenSegment/Mcount_Counter_cy<11>)
|
401 |
|
|
XORCY:CI->O 1 0.786 0.000 Inst_SevenSegment/Mcount_Counter_xor<12> (Result<12>)
|
402 |
|
|
FD:D 0.176 Inst_SevenSegment/Counter_12
|
403 |
|
|
----------------------------------------
|
404 |
|
|
Total 4.033ns (3.057ns logic, 0.976ns route)
|
405 |
|
|
(75.8% logic, 24.2% route)
|
406 |
|
|
|
407 |
|
|
=========================================================================
|
408 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
|
409 |
|
|
Total number of paths / destination ports: 1 / 1
|
410 |
|
|
-------------------------------------------------------------------------
|
411 |
|
|
Offset: 1.778ns (Levels of Logic = 1)
|
412 |
|
|
Source: DataIn (PAD)
|
413 |
|
|
Destination: Mshreg_data_2 (FF)
|
414 |
|
|
Destination Clock: Clk falling
|
415 |
|
|
|
416 |
|
|
Data Path: DataIn to Mshreg_data_2
|
417 |
|
|
Gate Net
|
418 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
419 |
|
|
---------------------------------------- ------------
|
420 |
|
|
IBUF:I->O 1 0.715 0.681 DataIn_IBUF (DataIn_IBUF)
|
421 |
|
|
SRL16_1:D 0.382 Mshreg_data_2
|
422 |
|
|
----------------------------------------
|
423 |
|
|
Total 1.778ns (1.097ns logic, 0.681ns route)
|
424 |
|
|
(61.7% logic, 38.3% route)
|
425 |
|
|
|
426 |
|
|
=========================================================================
|
427 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk2'
|
428 |
|
|
Total number of paths / destination ports: 92 / 11
|
429 |
|
|
-------------------------------------------------------------------------
|
430 |
|
|
Offset: 9.978ns (Levels of Logic = 4)
|
431 |
|
|
Source: Inst_SevenSegment/Counter_11 (FF)
|
432 |
|
|
Destination: Segments<6> (PAD)
|
433 |
|
|
Source Clock: Clk2 rising
|
434 |
|
|
|
435 |
|
|
Data Path: Inst_SevenSegment/Counter_11 to Segments<6>
|
436 |
|
|
Gate Net
|
437 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
438 |
|
|
---------------------------------------- ------------
|
439 |
|
|
FD:C->Q 13 0.626 1.290 Inst_SevenSegment/Counter_11 (Inst_SevenSegment/Counter_11)
|
440 |
|
|
LUT3:I0->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_3 (Inst_SevenSegment/Mmux_Chosen_3)
|
441 |
|
|
MUXF5:I1->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5 (Inst_SevenSegment/Chosen<0>)
|
442 |
|
|
LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments111 (Segments_1_OBUF)
|
443 |
|
|
OBUF:I->O 4.909 Segments_1_OBUF (Segments<1>)
|
444 |
|
|
----------------------------------------
|
445 |
|
|
Total 9.978ns (6.807ns logic, 3.171ns route)
|
446 |
|
|
(68.2% logic, 31.8% route)
|
447 |
|
|
|
448 |
|
|
=========================================================================
|
449 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
|
450 |
|
|
Total number of paths / destination ports: 120 / 15
|
451 |
|
|
-------------------------------------------------------------------------
|
452 |
|
|
Offset: 9.540ns (Levels of Logic = 4)
|
453 |
|
|
Source: OutByte1_5 (FF)
|
454 |
|
|
Destination: Segments<6> (PAD)
|
455 |
|
|
Source Clock: Clk falling
|
456 |
|
|
|
457 |
|
|
Data Path: OutByte1_5 to Segments<6>
|
458 |
|
|
Gate Net
|
459 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
460 |
|
|
---------------------------------------- ------------
|
461 |
|
|
FDE_1:C->Q 1 0.626 0.851 OutByte1_5 (OutByte1_5)
|
462 |
|
|
LUT3:I1->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_41 (Inst_SevenSegment/Mmux_Chosen_41)
|
463 |
|
|
MUXF5:I0->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5_0 (Inst_SevenSegment/Chosen<1>)
|
464 |
|
|
LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments21 (Segments_2_OBUF)
|
465 |
|
|
OBUF:I->O 4.909 Segments_2_OBUF (Segments<2>)
|
466 |
|
|
----------------------------------------
|
467 |
|
|
Total 9.540ns (6.807ns logic, 2.733ns route)
|
468 |
|
|
(71.4% logic, 28.6% route)
|
469 |
|
|
|
470 |
|
|
=========================================================================
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
Total REAL time to Xst completion: 5.00 secs
|
474 |
|
|
Total CPU time to Xst completion: 4.77 secs
|
475 |
|
|
|
476 |
|
|
-->
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
Total memory usage is 339112 kilobytes
|
480 |
|
|
|
481 |
|
|
Number of errors : 0 ( 0 filtered)
|
482 |
|
|
Number of warnings : 1 ( 0 filtered)
|
483 |
|
|
Number of infos : 0 ( 0 filtered)
|
484 |
|
|
|