Subversion Repositories ps2_keyboard_interface

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Release 12.3 Trace  (lin64)

Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

/home/omar/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3

-fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o

Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf

Design file:              Keyboard_Controller.ncd

Physical constraint file: Keyboard_Controller.pcf

Device,package,speed:     xc3s200,ft256,-5 (PRODUCTION 1.39 2010-09-15)

Report level:             verbose report

Environment Variable      Effect

--------------------      ------

NONE                      No environment variables were set

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INFO:Timing:2698 - No timing constraints found, doing default enumeration.

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

   option. All paths that are not constrained will be reported in the

   unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

   a 50 Ohm transmission line loading model.  For the details of this model,

   and for more information on accounting for different loading conditions,

   please see the device datasheet.

INFO:Timing:3390 - This architecture does not support a default System Jitter

   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock

   Uncertainty calculation.

INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and

   'Phase Error' calculations, these terms will be zero in the Clock

   Uncertainty calculation.  Please make appropriate modification to

   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase

   Error.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock Clk

------------+------------+------------+------------------+--------+

            |Max Setup to|Max Hold to |                  | Clock  |

Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |

------------+------------+------------+------------------+--------+

DataIn      |   -1.282(F)|    2.962(F)|Clk_BUFGP         |   0.000|

------------+------------+------------+------------------+--------+

Clock Clk to Pad

------------+------------+------------------+--------+

            | clk (edge) |                  | Clock  |

Destination |   to PAD   |Internal Clock(s) | Phase  |

------------+------------+------------------+--------+

Segments<0> |   15.527(F)|Clk_BUFGP         |   0.000|

Segments<1> |   15.547(F)|Clk_BUFGP         |   0.000|

Segments<2> |   14.902(F)|Clk_BUFGP         |   0.000|

Segments<3> |   14.832(F)|Clk_BUFGP         |   0.000|

Segments<4> |   14.881(F)|Clk_BUFGP         |   0.000|

Segments<5> |   15.667(F)|Clk_BUFGP         |   0.000|

Segments<6> |   14.621(F)|Clk_BUFGP         |   0.000|

pressed<0>  |   11.811(F)|Clk_BUFGP         |   0.000|

pressed<1>  |   10.757(F)|Clk_BUFGP         |   0.000|

pressed<2>  |   11.797(F)|Clk_BUFGP         |   0.000|

pressed<3>  |   11.135(F)|Clk_BUFGP         |   0.000|

pressed<4>  |   11.133(F)|Clk_BUFGP         |   0.000|

pressed<5>  |   10.677(F)|Clk_BUFGP         |   0.000|

pressed<6>  |   10.652(F)|Clk_BUFGP         |   0.000|

pressed<7>  |   10.781(F)|Clk_BUFGP         |   0.000|

------------+------------+------------------+--------+

Clock Clk2 to Pad

------------+------------+------------------+--------+

            | clk (edge) |                  | Clock  |

Destination |   to PAD   |Internal Clock(s) | Phase  |

------------+------------+------------------+--------+

Enables<0>  |   10.006(R)|Clk2_BUFGP        |   0.000|

Enables<1>  |    9.793(R)|Clk2_BUFGP        |   0.000|

Enables<2>  |    9.495(R)|Clk2_BUFGP        |   0.000|

Enables<3>  |   10.361(R)|Clk2_BUFGP        |   0.000|

Segments<0> |   12.189(R)|Clk2_BUFGP        |   0.000|

Segments<1> |   12.586(R)|Clk2_BUFGP        |   0.000|

Segments<2> |   11.867(R)|Clk2_BUFGP        |   0.000|

Segments<3> |   11.528(R)|Clk2_BUFGP        |   0.000|

Segments<4> |   11.497(R)|Clk2_BUFGP        |   0.000|

Segments<5> |   12.433(R)|Clk2_BUFGP        |   0.000|

Segments<6> |   11.330(R)|Clk2_BUFGP        |   0.000|

------------+------------+------------------+--------+

Clock to Setup on destination clock Clk

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

Clk            |         |         |         |    3.763|

---------------+---------+---------+---------+---------+

Clock to Setup on destination clock Clk2

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

Clk2           |    3.314|         |         |         |

---------------+---------+---------+---------+---------+

Analysis completed Fri Dec  3 00:08:32 2010

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Trace Settings:

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Trace Settings

Peak Memory Usage: 208 MB