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[/] [ps2core/] [trunk/] [sim/] [vhdl/] [ps2mouse_tb.vhd] - Blame information for rev 4

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1 2 danielqg 
-------------------------------------------------------------------------------
2 
-- Title      : PS/2 interface Testbench
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-- Project    :
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-------------------------------------------------------------------------------
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-- File       : ps2.vhd
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-- Author     : Daniel Quintero <danielqg@infonegocio.com>
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-- Company    : Itoo Software
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-- Created    : 2003-04-14
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-- Last update: 2003-10-30
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-- Platform   : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: PS/2 generic UART for mice/keyboard, Low level Testbench
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-------------------------------------------------------------------------------
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--  This code is distributed under the terms and conditions of the
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--  GNU General Public License
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2003-04-14  1.0      daniel  Created
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-------------------------------------------------------------------------------
21 
 
22 
library IEEE;
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use IEEE.std_logic_1164.all;
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use std.textio.all;
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entity ps2mouse_tb is
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end ps2mouse_tb;
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architecture sim of ps2mouse_tb is
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        procedure PS2SendByte(byte             : in    std_logic_vector(7 downto 0);
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                               signal PS2_clk  : inout std_logic;
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                               signal PS2_data : inout std_logic) is
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        begin
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                --wait until (PS2_clk = 'H');
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                for i in 0 to 10 loop
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                        if i = 0 then
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                                PS2_Data <= '0';
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                        elsif i = 9 then
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                                PS2_Data <= not (Byte(0) xor
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                                                 Byte(1) xor
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                                                 Byte(2) xor
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                                                 Byte(3) xor
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                                                 Byte(4) xor
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                                                 Byte(5) xor
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                                                 Byte(6) xor
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                                                 Byte(7));
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                        elsif i = 10 then
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                                PS2_Data <= 'H';
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                        else
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                                if Byte(i - 1) = '1' then
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                                        PS2_Data <= '1';
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                                else
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                                        PS2_Data <= '0';
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                                end if;
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                        end if;
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                        wait for 20 us;
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                        PS2_Clk <= '0';
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                        wait for 20 us;
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                        PS2_Clk <= '1';
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                end loop;
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                PS2_Clk <= 'H';
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        end;
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        procedure PS2RecvByte(byte             : out   std_logic_vector(7 downto 0);
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                               signal PS2_clk  : inout std_logic;
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                               signal PS2_data : inout std_logic) is
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                variable parity : std_logic;
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                variable buf    : std_logic_vector(7 downto 0);
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        begin
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                PS2_Data <= 'H';
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                for i in 0 to 10 loop
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                        wait for 20 us;
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                        PS2_Clk <= '0';
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                        if i = 0 then
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                                if PS2_data /= '0' then
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                                        write(output, string'("Warning, not start bit from Host"));
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                                end if;
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                        elsif i = 9 then
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                                parity := To_X01(PS2_data);
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                        elsif i = 10 then
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                                PS2_Data <= '0';  -- Ack
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                        else
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                                buf(i - 1) := To_X01(PS2_data);
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                        end if;
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                        wait for 20 us;
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                        PS2_Clk <= '1';
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                end loop;
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                if parity /= not (buf(0) xor buf(1) xor buf(2) xor buf(3) xor
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                                  buf(4) xor buf(5) xor buf(6) xor buf(7)) then
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                        write(output, string'("Waring, parity check error in host data"));
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                end if;
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                Byte     := buf;
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                PS2_Clk  <= 'H';
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                PS2_Data <= 'H';
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        end;
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        procedure PS2Write(signal req, rw : out std_logic;
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                            signal ack    : in  std_logic) is
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        begin
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                wait for 20 us;
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                req <= '1';
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                rw  <= '0';
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                wait until ack = '1';
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                req <= '0' after 10 ns;
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                rw  <= '1' after 10 ns;
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        end;
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        function stdvec_to_str(inp : std_logic_vector) return string is
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                variable temp : string(inp'left+1 downto 1) := (others => 'X');
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        begin
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                for i in inp'reverse_range loop
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                        if (inp(i) = '1') then
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                                temp(i+1) := '1';
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                        elsif (inp(i) = '0') then
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                                temp(i+1) := '0';
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                        end if;
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                end loop;
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                return temp;
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        end function stdvec_to_str;
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        signal stop   : boolean                      := false;
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        signal listen, read, send : boolean             := false;
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        signal clk    : std_logic                    := '0';
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        signal rst    : std_logic;
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        signal cmd_in : std_logic_vector(7 downto 0) := (others => '0');
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        signal PS2_clk  : std_logic := 'H';
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        signal PS2_data : std_logic := 'H';
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begin
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        u0 : entity mouse_test(rtl)
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                port map(clk_i      => clk, rst_i => rst,
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                         ps2_clk_io => PS2_Clk, ps2_data_io => PS2_Data);
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        -- Clk generation
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        process
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        begin
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                clk <= not clk;         -- 50Mhz clk
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                wait for 10 ns;
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                if stop then
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                        wait;
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                end if;
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        end process;
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        rst  <= '0', '1' after 1 ns;
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        stop <= true     after 25 ms;
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        process
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                variable data_in : std_logic_vector(7 downto 0) := (others => '0');
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                variable cmd     : integer;
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        begin
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                --wait for 100 us;
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                -- Send BAT cycle successful, 0xAA
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                --PS2SendByte("10101010", PS2_clk, PS2_data);
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                -- Send PS/2 device ID, 0x00
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                --PS2SendByte("00000000", PS2_clk, PS2_data);
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                wait for 10 us;
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                   listen <= true;
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                wait;
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        end process;
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        process
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                variable data_in : std_logic_vector(7 downto 0) := (others => '0');
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                variable cmd     : integer;
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        begin
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                wait on PS2_clk;
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                if PS2_clk = '0' then --and listen and not send then
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                        wait on PS2_clk;
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                    PS2RecvByte(data_in, PS2_clk, PS2_data);
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                    write(output, string'("Received data from host : "));
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                    write(output, stdvec_to_str(data_in));
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                        send <= true;
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        elsif PS2_clk /= '0' and send then
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                        wait for 1 ms;
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                        PS2SendByte("00001000", PS2_clk, PS2_data);
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                        PS2SendByte("00000100", PS2_clk, PS2_data);
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                        PS2SendByte("00000101", PS2_clk, PS2_data);
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                end if;
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                if stop then
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                        wait;
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                end if;
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        end process;
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end sim;

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