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[/] [ps2core/] [trunk/] [sim/] [vhdl/] [wb_test.vhd] - Blame information for rev 4

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--
--  Wishbone bus tester utilities.
--
--  (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
--
-- ELEMENTS:
--    procedure wr_chk_val: writes a value, reads it back an checks if it's the same
--    procedure wr_val: writes a value
--    procedure rd_val: reads a value
--    procedure chk_val: checks (after read) a value
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
package wb_test is
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in STD_LOGIC_VECTOR;
                constant data: in STD_LOGIC_VECTOR
        );
 
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        );
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        );
end wb_test;
 
 
package body wb_test is
    procedure wr_chk_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        stb_i <= '0';
        we_i <= '0';
        cyc_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= data;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '1';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        assert dat_o = data report "Value does not match!" severity ERROR;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end;
 
    procedure wr_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        stb_i <= '0';
        we_i <= '0';
        cyc_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= data;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '1';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
    end;
 
    procedure rd_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        variable data: out STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        data := dat_o;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end;
 
    procedure chk_val(
        signal clk_i: in STD_LOGIC;
        signal adr_i: out STD_LOGIC_VECTOR;
        signal dat_o: in STD_LOGIC_VECTOR;
        signal dat_i: out STD_LOGIC_VECTOR;
        signal we_i: out STD_LOGIC;
        signal cyc_i: out std_logic;
        signal stb_i: out STD_LOGIC;
        signal ack_o: in STD_LOGIC;
        constant addr: in STD_LOGIC_VECTOR;
        constant data: in STD_LOGIC_VECTOR
    ) is
        variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
        variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
        adr_i <= adr_zero;
        dat_i <= dat_undef;
        cyc_i <= '0';
        stb_i <= '0';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        wait until clk_i'EVENT and clk_i = '1';
        adr_i <= addr;
        dat_i <= dat_undef;
        cyc_i <= '1';
        stb_i <= '1';
        we_i <= '0';
        wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
        assert dat_o = data report "Value does not match!" severity ERROR;
        adr_i <= adr_zero;
        stb_i <= '0';
        cyc_i <= '0';
    end;
 
        procedure wr_chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure wr_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure rd_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                variable data: out STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
        procedure chk_val(
                signal clk_i: in STD_LOGIC;
                signal adr_i: out STD_LOGIC_VECTOR;
                signal dat_o: in STD_LOGIC_VECTOR;
                signal dat_i: out STD_LOGIC_VECTOR;
                signal we_i: out STD_LOGIC;
                signal cyc_i: out std_logic;
                signal stb_i: out STD_LOGIC;
                signal ack_o: in STD_LOGIC;
                constant addr: in integer;
                constant data: in STD_LOGIC_VECTOR
        ) is
            variable sadr: std_logic_vector(adr_i'RANGE);
        begin
            sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
            chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
        end;
 
end;

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Subversion Repositories ps2core

[/] [ps2core/] [trunk/] [sim/] [vhdl/] [wb_test.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	danielqg	`--`
2			`-- Wishbone bus tester utilities.`
3			`--`
4			`-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17`
5			`-- This code is distributed under the terms and conditions of the GNU General Public Lince.`
6			`--`
7			`--`
8			`-- ELEMENTS:`
9			`-- procedure wr_chk_val: writes a value, reads it back an checks if it's the same`
10			`-- procedure wr_val: writes a value`
11			`-- procedure rd_val: reads a value`
12			`-- procedure chk_val: checks (after read) a value`
13
14			`library IEEE;`
15			`use IEEE.std_logic_1164.all;`
16			`use IEEE.std_logic_arith.all;`
17
18			`package wb_test is`
19			`procedure wr_chk_val(`
20			`signal clk_i: in STD_LOGIC;`
21			`signal adr_i: out STD_LOGIC_VECTOR;`
22			`signal dat_o: in STD_LOGIC_VECTOR;`
23			`signal dat_i: out STD_LOGIC_VECTOR;`
24			`signal we_i: out STD_LOGIC;`
25			`signal cyc_i: out std_logic;`
26			`signal stb_i: out STD_LOGIC;`
27			`signal ack_o: in STD_LOGIC;`
28			`constant addr: in STD_LOGIC_VECTOR;`
29			`constant data: in STD_LOGIC_VECTOR`
30			`);`
31			`procedure wr_val(`
32			`signal clk_i: in STD_LOGIC;`
33			`signal adr_i: out STD_LOGIC_VECTOR;`
34			`signal dat_o: in STD_LOGIC_VECTOR;`
35			`signal dat_i: out STD_LOGIC_VECTOR;`
36			`signal we_i: out STD_LOGIC;`
37			`signal cyc_i: out std_logic;`
38			`signal stb_i: out STD_LOGIC;`
39			`signal ack_o: in STD_LOGIC;`
40			`constant addr: in STD_LOGIC_VECTOR;`
41			`constant data: in STD_LOGIC_VECTOR`
42			`);`
43			`procedure rd_val(`
44			`signal clk_i: in STD_LOGIC;`
45			`signal adr_i: out STD_LOGIC_VECTOR;`
46			`signal dat_o: in STD_LOGIC_VECTOR;`
47			`signal dat_i: out STD_LOGIC_VECTOR;`
48			`signal we_i: out STD_LOGIC;`
49			`signal cyc_i: out std_logic;`
50			`signal stb_i: out STD_LOGIC;`
51			`signal ack_o: in STD_LOGIC;`
52			`constant addr: in STD_LOGIC_VECTOR;`
53			`variable data: out STD_LOGIC_VECTOR`
54			`);`
55			`procedure chk_val(`
56			`signal clk_i: in STD_LOGIC;`
57			`signal adr_i: out STD_LOGIC_VECTOR;`
58			`signal dat_o: in STD_LOGIC_VECTOR;`
59			`signal dat_i: out STD_LOGIC_VECTOR;`
60			`signal we_i: out STD_LOGIC;`
61			`signal cyc_i: out std_logic;`
62			`signal stb_i: out STD_LOGIC;`
63			`signal ack_o: in STD_LOGIC;`
64			`constant addr: in STD_LOGIC_VECTOR;`
65			`constant data: in STD_LOGIC_VECTOR`
66			`);`
67
68
69			`procedure wr_chk_val(`
70			`signal clk_i: in STD_LOGIC;`
71			`signal adr_i: out STD_LOGIC_VECTOR;`
72			`signal dat_o: in STD_LOGIC_VECTOR;`
73			`signal dat_i: out STD_LOGIC_VECTOR;`
74			`signal we_i: out STD_LOGIC;`
75			`signal cyc_i: out std_logic;`
76			`signal stb_i: out STD_LOGIC;`
77			`signal ack_o: in STD_LOGIC;`
78			`constant addr: in integer;`
79			`constant data: in STD_LOGIC_VECTOR`
80			`);`
81			`procedure wr_val(`
82			`signal clk_i: in STD_LOGIC;`
83			`signal adr_i: out STD_LOGIC_VECTOR;`
84			`signal dat_o: in STD_LOGIC_VECTOR;`
85			`signal dat_i: out STD_LOGIC_VECTOR;`
86			`signal we_i: out STD_LOGIC;`
87			`signal cyc_i: out std_logic;`
88			`signal stb_i: out STD_LOGIC;`
89			`signal ack_o: in STD_LOGIC;`
90			`constant addr: in integer;`
91			`constant data: in STD_LOGIC_VECTOR`
92			`);`
93			`procedure rd_val(`
94			`signal clk_i: in STD_LOGIC;`
95			`signal adr_i: out STD_LOGIC_VECTOR;`
96			`signal dat_o: in STD_LOGIC_VECTOR;`
97			`signal dat_i: out STD_LOGIC_VECTOR;`
98			`signal we_i: out STD_LOGIC;`
99			`signal cyc_i: out std_logic;`
100			`signal stb_i: out STD_LOGIC;`
101			`signal ack_o: in STD_LOGIC;`
102			`constant addr: in integer;`
103			`variable data: out STD_LOGIC_VECTOR`
104			`);`
105			`procedure chk_val(`
106			`signal clk_i: in STD_LOGIC;`
107			`signal adr_i: out STD_LOGIC_VECTOR;`
108			`signal dat_o: in STD_LOGIC_VECTOR;`
109			`signal dat_i: out STD_LOGIC_VECTOR;`
110			`signal we_i: out STD_LOGIC;`
111			`signal cyc_i: out std_logic;`
112			`signal stb_i: out STD_LOGIC;`
113			`signal ack_o: in STD_LOGIC;`
114			`constant addr: in integer;`
115			`constant data: in STD_LOGIC_VECTOR`
116			`);`
117			`end wb_test;`
118
119
120			`package body wb_test is`
121			`procedure wr_chk_val(`
122			`signal clk_i: in STD_LOGIC;`
123			`signal adr_i: out STD_LOGIC_VECTOR;`
124			`signal dat_o: in STD_LOGIC_VECTOR;`
125			`signal dat_i: out STD_LOGIC_VECTOR;`
126			`signal we_i: out STD_LOGIC;`
127			`signal cyc_i: out std_logic;`
128			`signal stb_i: out STD_LOGIC;`
129			`signal ack_o: in STD_LOGIC;`
130			`constant addr: in STD_LOGIC_VECTOR;`
131			`constant data: in STD_LOGIC_VECTOR`
132			`) is`
133			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
134			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
135			`begin`
136			`adr_i <= adr_zero;`
137			`dat_i <= dat_undef;`
138			`stb_i <= '0';`
139			`we_i <= '0';`
140			`cyc_i <= '0';`
141			`wait until clk_i'EVENT and clk_i = '1';`
142			`wait until clk_i'EVENT and clk_i = '1';`
143			`wait until clk_i'EVENT and clk_i = '1';`
144			`adr_i <= addr;`
145			`dat_i <= data;`
146			`cyc_i <= '1';`
147			`stb_i <= '1';`
148			`we_i <= '1';`
149			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
150			`adr_i <= adr_zero;`
151			`dat_i <= dat_undef;`
152			`cyc_i <= '0';`
153			`stb_i <= '0';`
154			`we_i <= '0';`
155			`wait until clk_i'EVENT and clk_i = '1';`
156			`adr_i <= addr;`
157			`dat_i <= dat_undef;`
158			`cyc_i <= '1';`
159			`stb_i <= '1';`
160			`we_i <= '0';`
161			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
162			`assert dat_o = data report "Value does not match!" severity ERROR;`
163			`adr_i <= adr_zero;`
164			`stb_i <= '0';`
165			`cyc_i <= '0';`
166			`end;`
167
168			`procedure wr_val(`
169			`signal clk_i: in STD_LOGIC;`
170			`signal adr_i: out STD_LOGIC_VECTOR;`
171			`signal dat_o: in STD_LOGIC_VECTOR;`
172			`signal dat_i: out STD_LOGIC_VECTOR;`
173			`signal we_i: out STD_LOGIC;`
174			`signal cyc_i: out std_logic;`
175			`signal stb_i: out STD_LOGIC;`
176			`signal ack_o: in STD_LOGIC;`
177			`constant addr: in STD_LOGIC_VECTOR;`
178			`constant data: in STD_LOGIC_VECTOR`
179			`) is`
180			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
181			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
182			`begin`
183			`adr_i <= adr_zero;`
184			`dat_i <= dat_undef;`
185			`stb_i <= '0';`
186			`we_i <= '0';`
187			`cyc_i <= '0';`
188			`wait until clk_i'EVENT and clk_i = '1';`
189			`wait until clk_i'EVENT and clk_i = '1';`
190			`wait until clk_i'EVENT and clk_i = '1';`
191			`adr_i <= addr;`
192			`dat_i <= data;`
193			`cyc_i <= '1';`
194			`stb_i <= '1';`
195			`we_i <= '1';`
196			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
197			`adr_i <= adr_zero;`
198			`dat_i <= dat_undef;`
199			`cyc_i <= '0';`
200			`stb_i <= '0';`
201			`we_i <= '0';`
202			`end;`
203
204			`procedure rd_val(`
205			`signal clk_i: in STD_LOGIC;`
206			`signal adr_i: out STD_LOGIC_VECTOR;`
207			`signal dat_o: in STD_LOGIC_VECTOR;`
208			`signal dat_i: out STD_LOGIC_VECTOR;`
209			`signal we_i: out STD_LOGIC;`
210			`signal cyc_i: out std_logic;`
211			`signal stb_i: out STD_LOGIC;`
212			`signal ack_o: in STD_LOGIC;`
213			`constant addr: in STD_LOGIC_VECTOR;`
214			`variable data: out STD_LOGIC_VECTOR`
215			`) is`
216			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
217			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
218			`begin`
219			`adr_i <= adr_zero;`
220			`dat_i <= dat_undef;`
221			`cyc_i <= '0';`
222			`stb_i <= '0';`
223			`we_i <= '0';`
224			`wait until clk_i'EVENT and clk_i = '1';`
225			`wait until clk_i'EVENT and clk_i = '1';`
226			`wait until clk_i'EVENT and clk_i = '1';`
227			`adr_i <= addr;`
228			`dat_i <= dat_undef;`
229			`cyc_i <= '1';`
230			`stb_i <= '1';`
231			`we_i <= '0';`
232			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
233			`data := dat_o;`
234			`adr_i <= adr_zero;`
235			`stb_i <= '0';`
236			`cyc_i <= '0';`
237			`end;`
238
239			`procedure chk_val(`
240			`signal clk_i: in STD_LOGIC;`
241			`signal adr_i: out STD_LOGIC_VECTOR;`
242			`signal dat_o: in STD_LOGIC_VECTOR;`
243			`signal dat_i: out STD_LOGIC_VECTOR;`
244			`signal we_i: out STD_LOGIC;`
245			`signal cyc_i: out std_logic;`
246			`signal stb_i: out STD_LOGIC;`
247			`signal ack_o: in STD_LOGIC;`
248			`constant addr: in STD_LOGIC_VECTOR;`
249			`constant data: in STD_LOGIC_VECTOR`
250			`) is`
251			`variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');`
252			`variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');`
253			`begin`
254			`adr_i <= adr_zero;`
255			`dat_i <= dat_undef;`
256			`cyc_i <= '0';`
257			`stb_i <= '0';`
258			`we_i <= '0';`
259			`wait until clk_i'EVENT and clk_i = '1';`
260			`wait until clk_i'EVENT and clk_i = '1';`
261			`wait until clk_i'EVENT and clk_i = '1';`
262			`adr_i <= addr;`
263			`dat_i <= dat_undef;`
264			`cyc_i <= '1';`
265			`stb_i <= '1';`
266			`we_i <= '0';`
267			`wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';`
268			`assert dat_o = data report "Value does not match!" severity ERROR;`
269			`adr_i <= adr_zero;`
270			`stb_i <= '0';`
271			`cyc_i <= '0';`
272			`end;`
273
274			`procedure wr_chk_val(`
275			`signal clk_i: in STD_LOGIC;`
276			`signal adr_i: out STD_LOGIC_VECTOR;`
277			`signal dat_o: in STD_LOGIC_VECTOR;`
278			`signal dat_i: out STD_LOGIC_VECTOR;`
279			`signal we_i: out STD_LOGIC;`
280			`signal cyc_i: out std_logic;`
281			`signal stb_i: out STD_LOGIC;`
282			`signal ack_o: in STD_LOGIC;`
283			`constant addr: in integer;`
284			`constant data: in STD_LOGIC_VECTOR`
285			`) is`
286			`variable sadr: std_logic_vector(adr_i'RANGE);`
287			`begin`
288			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
289			`wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
290			`end;`
291			`procedure wr_val(`
292			`signal clk_i: in STD_LOGIC;`
293			`signal adr_i: out STD_LOGIC_VECTOR;`
294			`signal dat_o: in STD_LOGIC_VECTOR;`
295			`signal dat_i: out STD_LOGIC_VECTOR;`
296			`signal we_i: out STD_LOGIC;`
297			`signal cyc_i: out std_logic;`
298			`signal stb_i: out STD_LOGIC;`
299			`signal ack_o: in STD_LOGIC;`
300			`constant addr: in integer;`
301			`constant data: in STD_LOGIC_VECTOR`
302			`) is`
303			`variable sadr: std_logic_vector(adr_i'RANGE);`
304			`begin`
305			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
306			`wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
307			`end;`
308			`procedure rd_val(`
309			`signal clk_i: in STD_LOGIC;`
310			`signal adr_i: out STD_LOGIC_VECTOR;`
311			`signal dat_o: in STD_LOGIC_VECTOR;`
312			`signal dat_i: out STD_LOGIC_VECTOR;`
313			`signal we_i: out STD_LOGIC;`
314			`signal cyc_i: out std_logic;`
315			`signal stb_i: out STD_LOGIC;`
316			`signal ack_o: in STD_LOGIC;`
317			`constant addr: in integer;`
318			`variable data: out STD_LOGIC_VECTOR`
319			`) is`
320			`variable sadr: std_logic_vector(adr_i'RANGE);`
321			`begin`
322			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
323			`rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
324			`end;`
325			`procedure chk_val(`
326			`signal clk_i: in STD_LOGIC;`
327			`signal adr_i: out STD_LOGIC_VECTOR;`
328			`signal dat_o: in STD_LOGIC_VECTOR;`
329			`signal dat_i: out STD_LOGIC_VECTOR;`
330			`signal we_i: out STD_LOGIC;`
331			`signal cyc_i: out std_logic;`
332			`signal stb_i: out STD_LOGIC;`
333			`signal ack_o: in STD_LOGIC;`
334			`constant addr: in integer;`
335			`constant data: in STD_LOGIC_VECTOR`
336			`) is`
337			`variable sadr: std_logic_vector(adr_i'RANGE);`
338			`begin`
339			`sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);`
340			`chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);`
341			`end;`
342
343			`end;`