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[/] [psg16/] [trunk/] [bench/] [PSG16_tb.v] - Blame information for rev 2

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`define PSG             64'hFFFF_FFFF_FFD5_0000
 
module PSG16_tb();
reg clk;
reg rst;
reg cyc;
reg stb;
wire ack;
reg we;
reg [63:0] adr;
reg [15:0] dat;
reg [7:0] state;
wire [17:0] out;
reg [31:0] cnt;
 
initial begin
        rst = 0;
        clk = 0;
        #100 rst = 1;
        #100 rst = 0;
end
 
always #1 clk = ~clk;
 
always @(posedge clk)
if (rst) begin
        state <= 8'd0;
        cyc <= 1'b0;
        stb <= 1'b0;
        we <= 1'b0;
end
else
case (state)
8'd0:   state <= 8'd1;
// Set master volume at 15
8'd1:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG+128;
                dat <= 16'd15;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                state <= 8'd2;
        end
// Set frequency to 800Hz
8'd2:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG;
                dat <= 16'd13422;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                state <= 8'd3;
        end
// Set ADSR
8'd3:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG + 6;
                dat <= 16'hCA12;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                state <= 8'd4;
        end
// Set gate,triangle wave,output enable
8'd4:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG + 4;
                dat <= 16'h1104;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                cnt <= 32'd0;
                state <= 8'd5;
        end
// wait 1 second
8'd5:
        if (cnt==32'd50000)
                state <= 8'd6;
        else
                cnt <= cnt + 1;
// Set gate off,triangle wave,output enable
8'd6:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG + 4;
                dat <= 16'h0104;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                cnt <= 32'd0;
                state <= 8'd7;
        end
// wait 1 second
8'd7:
        if (cnt==32'd50000)
                state <= 8'd8;
        else
                cnt <= cnt + 1;
// Set gate off,triangle wave,output enable
8'd8:
        if (!cyc) begin
                cyc <= 1'b1;
                stb <= 1'b1;
                we <= 1'b1;
                adr <= `PSG + 4;
                dat <= 16'h0000;
        end
        else if (ack) begin
                cyc <= 1'b0;
                stb <= 1'b0;
                we <= 1'b0;
                cnt <= 32'd0;
                state <= 8'd9;
        end
default:        ;
endcase
 
 
PSG16 #(.pClkDivide(50)) u1
(
        .rst_i(rst),
        .clk_i(clk),
        .cyc_i(cyc),
        .stb_i(stb),
        .ack_o(ack),
        .we_i(we),
        .sel_i(2'b11),
        .adr_i(adr),
        .dat_i(dat),
        .dat_o(),
        .vol_o(),
        .bg(),
        .m_cyc_o(),
        .m_stb_o(),
        .m_ack_i(),
        .m_we_o(),
        .m_sel_o(),
        .m_adr_o(),
        .m_dat_i(),
        .o(out)
);
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`define PSG 64'hFFFF_FFFF_FFD5_0000
2
3			`module PSG16_tb();`
4			`reg clk;`
5			`reg rst;`
6			`reg cyc;`
7			`reg stb;`
8			`wire ack;`
9			`reg we;`
10			`reg [63:0] adr;`
11			`reg [15:0] dat;`
12			`reg [7:0] state;`
13			`wire [17:0] out;`
14			`reg [31:0] cnt;`
15
16			`initial begin`
17			`rst = 0;`
18			`clk = 0;`
19			`#100 rst = 1;`
20			`#100 rst = 0;`
21			`end`
22
23			`always #1 clk = ~clk;`
24
25			`always @(posedge clk)`
26			`if (rst) begin`
27			`state <= 8'd0;`
28			`cyc <= 1'b0;`
29			`stb <= 1'b0;`
30			`we <= 1'b0;`
31			`end`
32			`else`
33			`case (state)`
34			`8'd0: state <= 8'd1;`
35			`// Set master volume at 15`
36			`8'd1:`
37			`if (!cyc) begin`
38			`cyc <= 1'b1;`
39			`stb <= 1'b1;`
40			`we <= 1'b1;`
41			adr <= `PSG+128;
42			`dat <= 16'd15;`
43			`end`
44			`else if (ack) begin`
45			`cyc <= 1'b0;`
46			`stb <= 1'b0;`
47			`we <= 1'b0;`
48			`state <= 8'd2;`
49			`end`
50			`// Set frequency to 800Hz`
51			`8'd2:`
52			`if (!cyc) begin`
53			`cyc <= 1'b1;`
54			`stb <= 1'b1;`
55			`we <= 1'b1;`
56			adr <= `PSG;
57			`dat <= 16'd13422;`
58			`end`
59			`else if (ack) begin`
60			`cyc <= 1'b0;`
61			`stb <= 1'b0;`
62			`we <= 1'b0;`
63			`state <= 8'd3;`
64			`end`
65			`// Set ADSR`
66			`8'd3:`
67			`if (!cyc) begin`
68			`cyc <= 1'b1;`
69			`stb <= 1'b1;`
70			`we <= 1'b1;`
71			adr <= `PSG + 6;
72			`dat <= 16'hCA12;`
73			`end`
74			`else if (ack) begin`
75			`cyc <= 1'b0;`
76			`stb <= 1'b0;`
77			`we <= 1'b0;`
78			`state <= 8'd4;`
79			`end`
80			`// Set gate,triangle wave,output enable`
81			`8'd4:`
82			`if (!cyc) begin`
83			`cyc <= 1'b1;`
84			`stb <= 1'b1;`
85			`we <= 1'b1;`
86			adr <= `PSG + 4;
87			`dat <= 16'h1104;`
88			`end`
89			`else if (ack) begin`
90			`cyc <= 1'b0;`
91			`stb <= 1'b0;`
92			`we <= 1'b0;`
93			`cnt <= 32'd0;`
94			`state <= 8'd5;`
95			`end`
96			`// wait 1 second`
97			`8'd5:`
98			`if (cnt==32'd50000)`
99			`state <= 8'd6;`
100			`else`
101			`cnt <= cnt + 1;`
102			`// Set gate off,triangle wave,output enable`
103			`8'd6:`
104			`if (!cyc) begin`
105			`cyc <= 1'b1;`
106			`stb <= 1'b1;`
107			`we <= 1'b1;`
108			adr <= `PSG + 4;
109			`dat <= 16'h0104;`
110			`end`
111			`else if (ack) begin`
112			`cyc <= 1'b0;`
113			`stb <= 1'b0;`
114			`we <= 1'b0;`
115			`cnt <= 32'd0;`
116			`state <= 8'd7;`
117			`end`
118			`// wait 1 second`
119			`8'd7:`
120			`if (cnt==32'd50000)`
121			`state <= 8'd8;`
122			`else`
123			`cnt <= cnt + 1;`
124			`// Set gate off,triangle wave,output enable`
125			`8'd8:`
126			`if (!cyc) begin`
127			`cyc <= 1'b1;`
128			`stb <= 1'b1;`
129			`we <= 1'b1;`
130			adr <= `PSG + 4;
131			`dat <= 16'h0000;`
132			`end`
133			`else if (ack) begin`
134			`cyc <= 1'b0;`
135			`stb <= 1'b0;`
136			`we <= 1'b0;`
137			`cnt <= 32'd0;`
138			`state <= 8'd9;`
139			`end`
140			`default: ;`
141			`endcase`
142
143
144			`PSG16 #(.pClkDivide(50)) u1`
145			`(`
146			`.rst_i(rst),`
147			`.clk_i(clk),`
148			`.cyc_i(cyc),`
149			`.stb_i(stb),`
150			`.ack_o(ack),`
151			`.we_i(we),`
152			`.sel_i(2'b11),`
153			`.adr_i(adr),`
154			`.dat_i(dat),`
155			`.dat_o(),`
156			`.vol_o(),`
157			`.bg(),`
158			`.m_cyc_o(),`
159			`.m_stb_o(),`
160			`.m_ack_i(),`
161			`.m_we_o(),`
162			`.m_sel_o(),`
163			`.m_adr_o(),`
164			`.m_dat_i(),`
165			`.o(out)`
166			`);`
167
168			`endmodule`

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[/] [psg16/] [trunk/] [bench/] [PSG16_tb.v] - Blame information for rev 2