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[/] [psg16/] [trunk/] [rtl/] [verilog/] [PSGMasterVolumeControl.v] - Blame information for rev 5
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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// (C) 2007,2012 Robert Finch
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// All rights reserved.
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// robfinch<remove>@opencores.org
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//
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// PSGMasterVolumeControl.v
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// Controls the PSG's output volume.
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//============================================================================ */
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module PSGMasterVolumeControl(rst_i, clk_i, i, volume, o);
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input rst_i;
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input clk_i;
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input [15:0] i;
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input [3:0] volume;
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output [19:0] o;
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reg [19:0] o;
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// Multiply 16x4 bits
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wire [19:0] v1 = volume[0] ? i : 20'd0;
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wire [19:0] v2 = volume[1] ? {i,1'b0} + v1: v1;
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wire [19:0] v3 = volume[2] ? {i,2'b0} + v2: v2;
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wire [19:0] vo = volume[3] ? {i,3'b0} + v3: v3;
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always @(posedge clk_i)
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if (rst_i)
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o <= 20'b0; // Force the output volume to zero on reset
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else
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o <= vo;
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endmodule
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