OpenCores
URL https://opencores.org/ocsvn/pss/pss/trunk

Subversion Repositories pss

[/] [pss/] [trunk/] [pss/] [SW/] [onboard/] [Interrupts/] [Interrupts.c] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 AlexAntono
#define IO_GPR                  (*(volatile unsigned int *)(0x8A000000))
2
 
3
#define REG_CPU_CONTROL         (*(volatile unsigned int *)(0x40000000))
4
#define REG_CPU_PC              (*(volatile unsigned int *)(0x40000004))
5
#define REG_CPU_A31             (*(volatile unsigned int *)(0x40000008))
6
#define REG_DBG_A31             (*(volatile unsigned int *)(0x4000000C))
7
 
8
#define REG_INTC_CONTROL        (*(volatile unsigned int *)(0x40000010))
9
#define REG_INTC_MASK           (*(volatile unsigned int *)(0x40000014))
10
#define REG_INTC_REQ            (*(volatile unsigned int *)(0x40000018))
11
#define REG_MEM_SIZE_KB         (*(volatile unsigned int *)(0x4000001C))
12
 
13
#define REG_DMA_CONTROL         (*(volatile unsigned int *)(0x40000020))
14
#define REG_DMA_SOURCEADDR      (*(volatile unsigned int *)(0x40000024))
15
#define REG_DMA_DESTADDR        (*(volatile unsigned int *)(0x40000028))
16
#define REG_DMA_SIZE            (*(volatile unsigned int *)(0x4000002C))
17
 
18
#define REG_SGI                 (*(volatile unsigned int *)(0x40000030))
19
 
20
#define REG_BUS_ERROR_ADDR      (*(volatile unsigned int *)(0x40000038))
21
#define REG_BUS_ERROR_PC        (*(volatile unsigned int *)(0x4000003C))
22
 
23
#define REG_TRAP_CONTROL        (*(volatile unsigned int *)(0x40000040))
24
#define REG_TRAP_ADDR           (*(volatile unsigned int *)(0x40000044))
25
 
26
#define REG_INTC_CONTROL        (*(volatile unsigned int *)(0x40000010))
27
#define REG_INTC_MASK           (*(volatile unsigned int *)(0x40000014))
28
#define REG_INTC_REQ            (*(volatile unsigned int *)(0x40000018))
29
 
30
int inc_data;
31
 
32
void _zpu_interrupt(void)
33
{
34
    inc_data++;
35
        IO_GPR = inc_data;
36
 
37
    REG_INTC_REQ = 0xFF;                        // deasserting requests
38
}
39
 
40
int main()
41
{
42
    inc_data = 0x81;
43
    IO_GPR = inc_data;
44
 
45
    REG_INTC_MASK = 0xFF;
46
 
47
    REG_INTC_CONTROL = 0x01;        // enabling IE
48
 
49
    while (1)
50
    {
51
        REG_INTC_CONTROL = 0x01;        // enabling IE
52
    }
53
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.