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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.9
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module uart_rx
(
        input clk_i, rst_i,
 
        input rx_i,
        output reg rx_done_tick_o,
        output reg [7:0] dout_bo,
 
        output reg locked_o,
        output reg [28:0] bitperiod_o
);
 
localparam ST_NOSYNC                    = 4'h0;
localparam ST_NOSYNC_WAIT1_1    = 4'h1;
localparam ST_NOSYNC_WAIT0_2    = 4'h2;
localparam ST_NOSYNC_WAIT1_3    = 4'h3;
localparam ST_NOSYNC_WAIT0_4    = 4'h4;
localparam ST_NOSYNC_WAIT1_5    = 4'h5;
localparam ST_NOSYNC_WAIT0_6    = 4'h6;
localparam ST_NOSYNC_WAIT1_7    = 4'h7;
localparam ST_NOSYNC_WAIT0_8    = 4'h8;
localparam ST_NOSYNC_WAIT_STOP  = 4'h9;
localparam ST_SYNC                              = 4'hA;
localparam ST_SYNC_WAIT_START   = 4'hB;
localparam ST_SYNC_RX_DATA              = 4'hC;
localparam ST_SYNC_WAIT_STOP    = 4'hD;
 
reg [4:0]        state;
reg [31:0]       clk_counter;
reg [2:0]        bit_counter;
 
reg rx_buf;
always @(posedge clk_i)
        begin
        if (rst_i) rx_buf <= 1'b1;
        else rx_buf <= rx_i;
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                state <= ST_NOSYNC;
                clk_counter <= 32'h0;
                bit_counter <= 3'h0;
                locked_o <= 1'b0;
                bitperiod_o <= 32'h0;
                rx_done_tick_o <= 1'b0;
                dout_bo <= 8'h0;
                end
        else
                begin
 
                rx_done_tick_o <= 1'b0;
 
                case (state)
 
                        ST_NOSYNC:
                                begin
                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_1;
                                end
 
                        ST_NOSYNC_WAIT1_1:
                                begin
                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_2;
                                end
 
                        ST_NOSYNC_WAIT0_2:
                                begin
                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_3;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT1_3:
                                begin
                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_4;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT0_4:
                                begin
                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_5;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT1_5:
                                begin
                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_6;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT0_6:
                                begin
                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_7;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT1_7:
                                begin
                                if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_8;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT0_8:
                                begin
                                if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT_STOP;
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_NOSYNC_WAIT_STOP:
                                begin
                                if (rx_buf == 1'b1)
                                        begin
                                        state <= ST_SYNC;
                                        locked_o <= 1'b1;
                                        bitperiod_o <= clk_counter[31:3];               // clk_counter / 8
                                        dout_bo <= 32'h55;
                                        rx_done_tick_o <= 1'b1;
                                        end
                                clk_counter <= clk_counter + 32'h1;
                                end
 
                        ST_SYNC:
                                begin
                                if (rx_buf == 1'b0)
                                        begin
                                        state <= ST_SYNC_WAIT_START;
                                        clk_counter <= 32'h0;
                                        end
                                end
 
                        ST_SYNC_WAIT_START:
                                begin
                                clk_counter <= clk_counter + 32'h1;
                                if (clk_counter == {4'h0, bitperiod_o[28:1]})
                                        begin
                                        state <= ST_SYNC_RX_DATA;
                                        clk_counter <= 32'h0;
                                        bit_counter <= 3'h0;
                                        end
                                end
 
                        ST_SYNC_RX_DATA:
                                begin
                                clk_counter <= clk_counter + 32'h1;
                                if (clk_counter == {3'h0, bitperiod_o})
                                        begin
                                        dout_bo <= {rx_buf, dout_bo[7:1]};
                                        clk_counter <= 32'h0;
                                        bit_counter <= bit_counter + 3'h1;
                                        if (bit_counter == 3'h7)
                                                begin
                                                rx_done_tick_o <= 1'b1;
                                                state <= ST_SYNC_WAIT_STOP;
                                                end
                                        end
                                end
 
                        ST_SYNC_WAIT_STOP:
                                begin
                                if (rx_buf == 1'b1) state <= ST_SYNC;
                                end
 
                endcase
 
                end
        end
 
endmodule

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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [udm/] [uart_rx.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	AlexAntono	`/*`
2			`PSS`
3
4			`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
5			`All rights reserved.`
6
7			`Version 0.9`
8
9			`The FreeBSD license`
10
11			`Redistribution and use in source and binary forms, with or without`
12			`modification, are permitted provided that the following conditions`
13			`are met:`
14
15			`1. Redistributions of source code must retain the above copyright`
16			`notice, this list of conditions and the following disclaimer.`
17			`2. Redistributions in binary form must reproduce the above`
18			`copyright notice, this list of conditions and the following`
19			`disclaimer in the documentation and/or other materials`
20			`provided with the distribution.`
21
22			THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
23			`EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
24			`THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A`
25			`PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE`
26			`PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,`
27			`INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
28			`(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
29			`OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
30			`HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
31			`STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
32			`ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
33			`ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`*/`
35
36
37			`module uart_rx`
38			`(`
39			`input clk_i, rst_i,`
40
41			`input rx_i,`
42			`output reg rx_done_tick_o,`
43			`output reg [7:0] dout_bo,`
44
45			`output reg locked_o,`
46			`output reg [28:0] bitperiod_o`
47			`);`
48
49			`localparam ST_NOSYNC = 4'h0;`
50			`localparam ST_NOSYNC_WAIT1_1 = 4'h1;`
51			`localparam ST_NOSYNC_WAIT0_2 = 4'h2;`
52			`localparam ST_NOSYNC_WAIT1_3 = 4'h3;`
53			`localparam ST_NOSYNC_WAIT0_4 = 4'h4;`
54			`localparam ST_NOSYNC_WAIT1_5 = 4'h5;`
55			`localparam ST_NOSYNC_WAIT0_6 = 4'h6;`
56			`localparam ST_NOSYNC_WAIT1_7 = 4'h7;`
57			`localparam ST_NOSYNC_WAIT0_8 = 4'h8;`
58			`localparam ST_NOSYNC_WAIT_STOP = 4'h9;`
59			`localparam ST_SYNC = 4'hA;`
60			`localparam ST_SYNC_WAIT_START = 4'hB;`
61			`localparam ST_SYNC_RX_DATA = 4'hC;`
62			`localparam ST_SYNC_WAIT_STOP = 4'hD;`
63
64			`reg [4:0] state;`
65			`reg [31:0] clk_counter;`
66			`reg [2:0] bit_counter;`
67
68			`reg rx_buf;`
69			`always @(posedge clk_i)`
70			`begin`
71			`if (rst_i) rx_buf <= 1'b1;`
72			`else rx_buf <= rx_i;`
73			`end`
74
75			`always @(posedge clk_i)`
76			`begin`
77			`if (rst_i)`
78			`begin`
79			`state <= ST_NOSYNC;`
80			`clk_counter <= 32'h0;`
81			`bit_counter <= 3'h0;`
82			`locked_o <= 1'b0;`
83			`bitperiod_o <= 32'h0;`
84			`rx_done_tick_o <= 1'b0;`
85			`dout_bo <= 8'h0;`
86			`end`
87			`else`
88			`begin`
89
90			`rx_done_tick_o <= 1'b0;`
91
92			`case (state)`
93
94			`ST_NOSYNC:`
95			`begin`
96			`if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_1;`
97			`end`
98
99			`ST_NOSYNC_WAIT1_1:`
100			`begin`
101			`if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_2;`
102			`end`
103
104			`ST_NOSYNC_WAIT0_2:`
105			`begin`
106			`if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_3;`
107			`clk_counter <= clk_counter + 32'h1;`
108			`end`
109
110			`ST_NOSYNC_WAIT1_3:`
111			`begin`
112			`if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_4;`
113			`clk_counter <= clk_counter + 32'h1;`
114			`end`
115
116			`ST_NOSYNC_WAIT0_4:`
117			`begin`
118			`if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_5;`
119			`clk_counter <= clk_counter + 32'h1;`
120			`end`
121
122			`ST_NOSYNC_WAIT1_5:`
123			`begin`
124			`if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_6;`
125			`clk_counter <= clk_counter + 32'h1;`
126			`end`
127
128			`ST_NOSYNC_WAIT0_6:`
129			`begin`
130			`if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT1_7;`
131			`clk_counter <= clk_counter + 32'h1;`
132			`end`
133
134			`ST_NOSYNC_WAIT1_7:`
135			`begin`
136			`if (rx_buf == 1'b1) state <= ST_NOSYNC_WAIT0_8;`
137			`clk_counter <= clk_counter + 32'h1;`
138			`end`
139
140			`ST_NOSYNC_WAIT0_8:`
141			`begin`
142			`if (rx_buf == 1'b0) state <= ST_NOSYNC_WAIT_STOP;`
143			`clk_counter <= clk_counter + 32'h1;`
144			`end`
145
146			`ST_NOSYNC_WAIT_STOP:`
147			`begin`
148			`if (rx_buf == 1'b1)`
149			`begin`
150			`state <= ST_SYNC;`
151			`locked_o <= 1'b1;`
152			`bitperiod_o <= clk_counter[31:3]; // clk_counter / 8`
153			`dout_bo <= 32'h55;`
154			`rx_done_tick_o <= 1'b1;`
155			`end`
156			`clk_counter <= clk_counter + 32'h1;`
157			`end`
158
159			`ST_SYNC:`
160			`begin`
161			`if (rx_buf == 1'b0)`
162			`begin`
163			`state <= ST_SYNC_WAIT_START;`
164			`clk_counter <= 32'h0;`
165			`end`
166			`end`
167
168			`ST_SYNC_WAIT_START:`
169			`begin`
170			`clk_counter <= clk_counter + 32'h1;`
171			`if (clk_counter == {4'h0, bitperiod_o[28:1]})`
172			`begin`
173			`state <= ST_SYNC_RX_DATA;`
174			`clk_counter <= 32'h0;`
175			`bit_counter <= 3'h0;`
176			`end`
177			`end`
178
179			`ST_SYNC_RX_DATA:`
180			`begin`
181			`clk_counter <= clk_counter + 32'h1;`
182			`if (clk_counter == {3'h0, bitperiod_o})`
183			`begin`
184			`dout_bo <= {rx_buf, dout_bo[7:1]};`
185			`clk_counter <= 32'h0;`
186			`bit_counter <= bit_counter + 3'h1;`
187			`if (bit_counter == 3'h7)`
188			`begin`
189			`rx_done_tick_o <= 1'b1;`
190			`state <= ST_SYNC_WAIT_STOP;`
191			`end`
192			`end`
193			`end`
194
195			`ST_SYNC_WAIT_STOP:`
196			`begin`
197			`if (rx_buf == 1'b1) state <= ST_SYNC;`
198			`end`
199
200			`endcase`
201
202			`end`
203			`end`
204
205			`endmodule`