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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_edge_detector.v] - Blame information for rev 5

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1 5 AlexAntono 
/*
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 PSS
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 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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 All rights reserved.
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 Version 0.99
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 The FreeBSD license
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 Redistribution and use in source and binary forms, with or without
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 modification, are permitted provided that the following conditions
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 are met:
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 1. Redistributions of source code must retain the above copyright
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    notice, this list of conditions and the following disclaimer.
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 2. Redistributions in binary form must reproduce the above
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    copyright notice, this list of conditions and the following
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    disclaimer in the documentation and/or other materials
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    provided with the distribution.
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 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module pss_edge_detector
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(
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        input clk_i, rst_i,
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        input in,
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        output reg out
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);
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reg edge_inv;
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reg inbuf0, inbuf1, inbuf2;
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always @(posedge in, posedge rst_i)
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        begin
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        if (rst_i)
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                edge_inv <= 1'b0;
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        else
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                edge_inv <= ~edge_inv;
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        end
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always @(posedge clk_i)
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        begin
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        if (rst_i)
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                begin
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                inbuf0 <= 1'b0;
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                inbuf1 <= 1'b0;
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                inbuf2 <= 1'b0;
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                out <= 1'b0;
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                end
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        else
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                begin
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                inbuf0 <= edge_inv;
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                inbuf1 <= inbuf0;
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                inbuf2 <= inbuf1;
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                if (inbuf1 != inbuf2)
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                        out <= 1'b1;
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                else
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                        out <= 1'b0;
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                end
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        end
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endmodule

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