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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.9
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module PSS_IC
#(
        parameter MEM_SIZE_KB = 1
)
(
        input clk_i,
        input rst_i,
 
        //// Masters ////
        input m0_enb_i,
        input m0_we_i,
        input [31:0] m0_addr_bi,
        input [31:0] m0_wdata_bi,
        input [3:0] m0_writemask_bi,
        output reg m0_ack_o,
        output reg [31:0] m0_rdata_bo,
 
        input m1_enb_i,
        input m1_we_i,
        input [31:0] m1_addr_bi,
        input [31:0] m1_wdata_bi,
        input [3:0] m1_writemask_bi,
        output reg m1_ack_o,
        output reg [31:0] m1_rdata_bo,
 
        //// Slaves ////
        output reg s0_enb_o,
        output reg s0_we_o,
        output reg [31:0] s0_addr_bo,
        output reg [31:0] s0_wdata_bo,
        output reg [3:0] s0_writemask_bo,
        input s0_ack_i,
        input [31:0] s0_rdata_bi,
 
        output reg s1_enb_o,
        output reg s1_we_o,
        output reg [31:0] s1_addr_bo,
        output reg [31:0] s1_wdata_bo,
        output reg [3:0] s1_writemask_bo,
        input s1_ack_i,
        input [31:0] s1_rdata_bi,
 
        output reg s2_enb_o,
        output reg s2_we_o,
        output reg [31:0] s2_addr_bo,
        output reg [31:0] s2_wdata_bo,
        output reg [3:0] s2_writemask_bo,
        input s2_ack_i,
        input [31:0] s2_rdata_bi,
 
        output reg error_o,
        output reg [31:0] error_addr_bo
);
 
reg m0_s0_enb, m0_s1_enb, m0_s2_enb, m0_err_enb;
reg m1_s0_enb, m1_s1_enb, m1_s2_enb, m1_err_enb;
 
always @*
        begin
        m0_s0_enb = 1'b0;
        m0_s1_enb = 1'b0;
        m0_s2_enb = 1'b0;
        m0_err_enb = 1'b0;
 
        if (m0_enb_i == 1'b1)
                begin
                if (m0_addr_bi[31:10] < MEM_SIZE_KB)
                        m0_s0_enb = 1'b1;
                else if (m0_addr_bi[31:16] == 16'h4000)
                        m0_s1_enb = 1'b1;
                else if (m0_addr_bi[31] == 1'b1)
                        m0_s2_enb = 1'b1;
                else m0_err_enb = 1'b1;
                end
        end
 
always @*
        begin
        m1_s0_enb = 1'b0;
        m1_s1_enb = 1'b0;
        m1_s2_enb = 1'b0;
        m1_err_enb = 1'b0;
 
        if (m1_enb_i == 1'b1)
                begin
                if (m1_addr_bi[31:10] < MEM_SIZE_KB)
                        m1_s0_enb = 1'b1;
                else if (m1_addr_bi[31:16] == 16'h4000)
                        m1_s1_enb = 1'b1;
                else if (m1_addr_bi[31] == 1'b1)
                        m1_s2_enb = 1'b1;
                else m1_err_enb = 1'b1;
                end
        end
 
reg s0_pending, s1_pending, s2_pending;
reg s0_curmaster, s1_curmaster, s2_curmaster;
 
// Transaction drivers
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                s0_pending <= 1'b0;
                s0_curmaster <= 1'bx;
                end
        else
                begin
                if ((s0_pending == 1'b0) && (s0_ack_i == 1'b0))
                        begin
                        if (m0_s0_enb == 1'b1)
                                begin
                                s0_pending <= 1'b1;
                                s0_curmaster <= 1'b0;
                                end
                        else if (m1_s0_enb == 1'b1)
                                begin
                                s0_pending <= 1'b1;
                                s0_curmaster <= 1'b1;
                                end
                        end
                else
                        begin
                        if (s0_ack_i == 1'b1)
                                begin
                                s0_pending <= 1'b0;
                                s0_curmaster <= 1'bx;
                                end
                        end
                end
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                s1_pending <= 1'b0;
                s1_curmaster <= 1'bx;
                end
        else
                begin
                if ((s1_pending == 1'b0) && (s1_ack_i == 1'b0))
                        begin
                        if (m0_s1_enb == 1'b1)
                                begin
                                s1_pending <= 1'b1;
                                s1_curmaster <= 1'b0;
                                end
                        else if (m1_s1_enb == 1'b1)
                                begin
                                s1_pending <= 1'b1;
                                s1_curmaster <= 1'b1;
                                end
                        end
                else
                        begin
                        if (s1_ack_i == 1'b1)
                                begin
                                s1_pending <= 1'b0;
                                s1_curmaster <= 1'bx;
                                end
                        end
                end
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                s2_pending <= 1'b0;
                s2_curmaster <= 1'bx;
                end
        else
                begin
                if ((s2_pending == 1'b0) && (s2_ack_i == 1'b0))
                        begin
                        if (m0_s2_enb == 1'b1)
                                begin
                                s2_pending <= 1'b1;
                                s2_curmaster <= 1'b0;
                                end
                        else if (m1_s2_enb == 1'b1)
                                begin
                                s2_pending <= 1'b1;
                                s2_curmaster <= 1'b1;
                                end
                        end
                else
                        begin
                        if (s2_ack_i == 1'b1)
                                begin
                                s2_pending <= 1'b0;
                                s2_curmaster <= 1'bx;
                                end
                        end
                end
        end
 
// Slave drivers
always @*
        begin
        s0_enb_o = 1'b0;
        s0_we_o = 1'b0;
        s0_addr_bo = 32'hx;
        s0_wdata_bo = 32'hx;
        s0_writemask_bo = 4'hx;
        if (s0_pending == 1'b1)
                begin
                if (s0_curmaster == 1'b0)
                        begin
                        s0_enb_o = m0_enb_i;
                        s0_we_o = m0_we_i;
                        s0_addr_bo = m0_addr_bi;
                        s0_wdata_bo = m0_wdata_bi;
                        s0_writemask_bo = m0_writemask_bi;
                        end
                else
                        begin
                        s0_enb_o = m1_enb_i;
                        s0_we_o = m1_we_i;
                        s0_addr_bo = m1_addr_bi;
                        s0_wdata_bo = m1_wdata_bi;
                        s0_writemask_bo = m1_writemask_bi;
                        end
                end
        else if (m0_s0_enb == 1'b1)
                begin
                s0_enb_o = m0_enb_i;
                s0_we_o = m0_we_i;
                s0_addr_bo = m0_addr_bi;
                s0_wdata_bo = m0_wdata_bi;
                s0_writemask_bo = m0_writemask_bi;
                end
        else if (m1_s0_enb == 1'b1)
                begin
                s0_enb_o = m1_enb_i;
                s0_we_o = m1_we_i;
                s0_addr_bo = m1_addr_bi;
                s0_wdata_bo = m1_wdata_bi;
                s0_writemask_bo = m1_writemask_bi;
                end
        end
 
always @*
        begin
        s1_enb_o = 1'b0;
        s1_we_o = 1'b0;
        s1_addr_bo = 32'hx;
        s1_wdata_bo = 32'hx;
        s1_writemask_bo = 4'hx;
        if (s1_pending == 1'b1)
                begin
                if (s1_curmaster == 1'b0)
                        begin
                        s1_enb_o = m0_enb_i;
                        s1_we_o = m0_we_i;
                        s1_addr_bo = m0_addr_bi;
                        s1_wdata_bo = m0_wdata_bi;
                        s1_writemask_bo = m0_writemask_bi;
                        end
                else
                        begin
                        s1_enb_o = m1_enb_i;
                        s1_we_o = m1_we_i;
                        s1_addr_bo = m1_addr_bi;
                        s1_wdata_bo = m1_wdata_bi;
                        s1_writemask_bo = m1_writemask_bi;
                        end
                end
        else if (m0_s1_enb == 1'b1)
                begin
                s1_enb_o = m0_enb_i;
                s1_we_o = m0_we_i;
                s1_addr_bo = m0_addr_bi;
                s1_wdata_bo = m0_wdata_bi;
                s1_writemask_bo = m0_writemask_bi;
                end
        else if (m1_s1_enb == 1'b1)
                begin
                s1_enb_o = m1_enb_i;
                s1_we_o = m1_we_i;
                s1_addr_bo = m1_addr_bi;
                s1_wdata_bo = m1_wdata_bi;
                s1_writemask_bo = m1_writemask_bi;
                end
        end
 
always @*
        begin
        s2_enb_o = 1'b0;
        s2_we_o = 1'b0;
        s2_addr_bo = 32'hx;
        s2_wdata_bo = 32'hx;
        s2_writemask_bo = 4'hx;
        if (s2_pending == 1'b1)
                begin
                if (s2_curmaster == 1'b0)
                        begin
                        s2_enb_o = m0_enb_i;
                        s2_we_o = m0_we_i;
                        s2_addr_bo = m0_addr_bi;
                        s2_wdata_bo = m0_wdata_bi;
                        s2_writemask_bo = m0_writemask_bi;
                        end
                else
                        begin
                        s2_enb_o = m1_enb_i;
                        s2_we_o = m1_we_i;
                        s2_addr_bo = m1_addr_bi;
                        s2_wdata_bo = m1_wdata_bi;
                        s2_writemask_bo = m1_writemask_bi;
                        end
                end
        else if (m0_s2_enb == 1'b1)
                begin
                s2_enb_o = m0_enb_i;
                s2_we_o = m0_we_i;
                s2_addr_bo = m0_addr_bi;
                s2_wdata_bo = m0_wdata_bi;
                s2_writemask_bo = m0_writemask_bi;
                end
        else if (m1_s2_enb == 1'b1)
                begin
                s2_enb_o = m1_enb_i;
                s2_we_o = m1_we_i;
                s2_addr_bo = m1_addr_bi;
                s2_wdata_bo = m1_wdata_bi;
                s2_writemask_bo = m1_writemask_bi;
                end
        end
 
// Master drivers
always @*
        begin
        m0_ack_o = 1'b0;
        m0_rdata_bo = 32'hx;
        if ((s0_pending == 1'b1) && (s0_curmaster == 1'b0))
                begin
                m0_ack_o = s0_ack_i;
                m0_rdata_bo = s0_rdata_bi;
                end
        else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b0))
                begin
                m0_ack_o = s1_ack_i;
                m0_rdata_bo = s1_rdata_bi;
                end
        else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b0))
                begin
                m0_ack_o = s2_ack_i;
                m0_rdata_bo = s2_rdata_bi;
                end
        else if (m0_s0_enb == 1'b1)
                begin
                m0_ack_o = s0_ack_i;
                m0_rdata_bo = s0_rdata_bi;
                end
        else if (m0_s1_enb == 1'b1)
                begin
                m0_ack_o = s1_ack_i;
                m0_rdata_bo = s1_rdata_bi;
                end
        else if (m0_s2_enb == 1'b1)
                begin
                m0_ack_o = s2_ack_i;
                m0_rdata_bo = s2_rdata_bi;
                end
        end
 
always @*
        begin
        m1_ack_o = 1'b0;
        m1_rdata_bo = 32'hx;
        if ((s0_pending == 1'b1) && (s0_curmaster == 1'b1))
                begin
                m1_ack_o = s0_ack_i;
                m1_rdata_bo = s0_rdata_bi;
                end
        else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b1))
                begin
                m1_ack_o = s1_ack_i;
                m1_rdata_bo = s1_rdata_bi;
                end
        else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b1))
                begin
                m1_ack_o = s2_ack_i;
                m1_rdata_bo = s2_rdata_bi;
                end
        else if (m1_s0_enb == 1'b1)
                begin
                m1_ack_o = s0_ack_i;
                m1_rdata_bo = s0_rdata_bi;
                end
        else if (m1_s1_enb == 1'b1)
                begin
                m1_ack_o = s1_ack_i;
                m1_rdata_bo = s1_rdata_bi;
                end
        else if (m1_s2_enb == 1'b1)
                begin
                m1_ack_o = s2_ack_i;
                m1_rdata_bo = s2_rdata_bi;
                end
        end
 
endmodule

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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_ic.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	AlexAntono	`/*`
2			`PSS`
3
4			`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
5			`All rights reserved.`
6
7			`Version 0.9`
8
9			`The FreeBSD license`
10
11			`Redistribution and use in source and binary forms, with or without`
12			`modification, are permitted provided that the following conditions`
13			`are met:`
14
15			`1. Redistributions of source code must retain the above copyright`
16			`notice, this list of conditions and the following disclaimer.`
17			`2. Redistributions in binary form must reproduce the above`
18			`copyright notice, this list of conditions and the following`
19			`disclaimer in the documentation and/or other materials`
20			`provided with the distribution.`
21
22			THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
23			`EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
24			`THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A`
25			`PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE`
26			`PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,`
27			`INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
28			`(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
29			`OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
30			`HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
31			`STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
32			`ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
33			`ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`*/`
35
36
37			`module PSS_IC`
38			`#(`
39			`parameter MEM_SIZE_KB = 1`
40			`)`
41			`(`
42			`input clk_i,`
43			`input rst_i,`
44
45			`//// Masters ////`
46			`input m0_enb_i,`
47			`input m0_we_i,`
48			`input [31:0] m0_addr_bi,`
49			`input [31:0] m0_wdata_bi,`
50			`input [3:0] m0_writemask_bi,`
51			`output reg m0_ack_o,`
52			`output reg [31:0] m0_rdata_bo,`
53
54			`input m1_enb_i,`
55			`input m1_we_i,`
56			`input [31:0] m1_addr_bi,`
57			`input [31:0] m1_wdata_bi,`
58			`input [3:0] m1_writemask_bi,`
59			`output reg m1_ack_o,`
60			`output reg [31:0] m1_rdata_bo,`
61
62			`//// Slaves ////`
63			`output reg s0_enb_o,`
64			`output reg s0_we_o,`
65			`output reg [31:0] s0_addr_bo,`
66			`output reg [31:0] s0_wdata_bo,`
67			`output reg [3:0] s0_writemask_bo,`
68			`input s0_ack_i,`
69			`input [31:0] s0_rdata_bi,`
70
71			`output reg s1_enb_o,`
72			`output reg s1_we_o,`
73			`output reg [31:0] s1_addr_bo,`
74			`output reg [31:0] s1_wdata_bo,`
75			`output reg [3:0] s1_writemask_bo,`
76			`input s1_ack_i,`
77			`input [31:0] s1_rdata_bi,`
78
79			`output reg s2_enb_o,`
80			`output reg s2_we_o,`
81			`output reg [31:0] s2_addr_bo,`
82			`output reg [31:0] s2_wdata_bo,`
83			`output reg [3:0] s2_writemask_bo,`
84			`input s2_ack_i,`
85			`input [31:0] s2_rdata_bi,`
86
87			`output reg error_o,`
88			`output reg [31:0] error_addr_bo`
89			`);`
90
91			`reg m0_s0_enb, m0_s1_enb, m0_s2_enb, m0_err_enb;`
92			`reg m1_s0_enb, m1_s1_enb, m1_s2_enb, m1_err_enb;`
93
94			`always @*`
95			`begin`
96			`m0_s0_enb = 1'b0;`
97			`m0_s1_enb = 1'b0;`
98			`m0_s2_enb = 1'b0;`
99			`m0_err_enb = 1'b0;`
100
101			`if (m0_enb_i == 1'b1)`
102			`begin`
103			`if (m0_addr_bi[31:10] < MEM_SIZE_KB)`
104			`m0_s0_enb = 1'b1;`
105			`else if (m0_addr_bi[31:16] == 16'h4000)`
106			`m0_s1_enb = 1'b1;`
107			`else if (m0_addr_bi[31] == 1'b1)`
108			`m0_s2_enb = 1'b1;`
109			`else m0_err_enb = 1'b1;`
110			`end`
111			`end`
112
113			`always @*`
114			`begin`
115			`m1_s0_enb = 1'b0;`
116			`m1_s1_enb = 1'b0;`
117			`m1_s2_enb = 1'b0;`
118			`m1_err_enb = 1'b0;`
119
120			`if (m1_enb_i == 1'b1)`
121			`begin`
122			`if (m1_addr_bi[31:10] < MEM_SIZE_KB)`
123			`m1_s0_enb = 1'b1;`
124			`else if (m1_addr_bi[31:16] == 16'h4000)`
125			`m1_s1_enb = 1'b1;`
126			`else if (m1_addr_bi[31] == 1'b1)`
127			`m1_s2_enb = 1'b1;`
128			`else m1_err_enb = 1'b1;`
129			`end`
130			`end`
131
132			`reg s0_pending, s1_pending, s2_pending;`
133			`reg s0_curmaster, s1_curmaster, s2_curmaster;`
134
135			`// Transaction drivers`
136			`always @(posedge clk_i)`
137			`begin`
138			`if (rst_i)`
139			`begin`
140			`s0_pending <= 1'b0;`
141			`s0_curmaster <= 1'bx;`
142			`end`
143			`else`
144			`begin`
145			`if ((s0_pending == 1'b0) && (s0_ack_i == 1'b0))`
146			`begin`
147			`if (m0_s0_enb == 1'b1)`
148			`begin`
149			`s0_pending <= 1'b1;`
150			`s0_curmaster <= 1'b0;`
151			`end`
152			`else if (m1_s0_enb == 1'b1)`
153			`begin`
154			`s0_pending <= 1'b1;`
155			`s0_curmaster <= 1'b1;`
156			`end`
157			`end`
158			`else`
159			`begin`
160			`if (s0_ack_i == 1'b1)`
161			`begin`
162			`s0_pending <= 1'b0;`
163			`s0_curmaster <= 1'bx;`
164			`end`
165			`end`
166			`end`
167			`end`
168
169			`always @(posedge clk_i)`
170			`begin`
171			`if (rst_i)`
172			`begin`
173			`s1_pending <= 1'b0;`
174			`s1_curmaster <= 1'bx;`
175			`end`
176			`else`
177			`begin`
178			`if ((s1_pending == 1'b0) && (s1_ack_i == 1'b0))`
179			`begin`
180			`if (m0_s1_enb == 1'b1)`
181			`begin`
182			`s1_pending <= 1'b1;`
183			`s1_curmaster <= 1'b0;`
184			`end`
185			`else if (m1_s1_enb == 1'b1)`
186			`begin`
187			`s1_pending <= 1'b1;`
188			`s1_curmaster <= 1'b1;`
189			`end`
190			`end`
191			`else`
192			`begin`
193			`if (s1_ack_i == 1'b1)`
194			`begin`
195			`s1_pending <= 1'b0;`
196			`s1_curmaster <= 1'bx;`
197			`end`
198			`end`
199			`end`
200			`end`
201
202			`always @(posedge clk_i)`
203			`begin`
204			`if (rst_i)`
205			`begin`
206			`s2_pending <= 1'b0;`
207			`s2_curmaster <= 1'bx;`
208			`end`
209			`else`
210			`begin`
211			`if ((s2_pending == 1'b0) && (s2_ack_i == 1'b0))`
212			`begin`
213			`if (m0_s2_enb == 1'b1)`
214			`begin`
215			`s2_pending <= 1'b1;`
216			`s2_curmaster <= 1'b0;`
217			`end`
218			`else if (m1_s2_enb == 1'b1)`
219			`begin`
220			`s2_pending <= 1'b1;`
221			`s2_curmaster <= 1'b1;`
222			`end`
223			`end`
224			`else`
225			`begin`
226			`if (s2_ack_i == 1'b1)`
227			`begin`
228			`s2_pending <= 1'b0;`
229			`s2_curmaster <= 1'bx;`
230			`end`
231			`end`
232			`end`
233			`end`
234
235			`// Slave drivers`
236			`always @*`
237			`begin`
238			`s0_enb_o = 1'b0;`
239			`s0_we_o = 1'b0;`
240			`s0_addr_bo = 32'hx;`
241			`s0_wdata_bo = 32'hx;`
242			`s0_writemask_bo = 4'hx;`
243			`if (s0_pending == 1'b1)`
244			`begin`
245			`if (s0_curmaster == 1'b0)`
246			`begin`
247			`s0_enb_o = m0_enb_i;`
248			`s0_we_o = m0_we_i;`
249			`s0_addr_bo = m0_addr_bi;`
250			`s0_wdata_bo = m0_wdata_bi;`
251			`s0_writemask_bo = m0_writemask_bi;`
252			`end`
253			`else`
254			`begin`
255			`s0_enb_o = m1_enb_i;`
256			`s0_we_o = m1_we_i;`
257			`s0_addr_bo = m1_addr_bi;`
258			`s0_wdata_bo = m1_wdata_bi;`
259			`s0_writemask_bo = m1_writemask_bi;`
260			`end`
261			`end`
262			`else if (m0_s0_enb == 1'b1)`
263			`begin`
264			`s0_enb_o = m0_enb_i;`
265			`s0_we_o = m0_we_i;`
266			`s0_addr_bo = m0_addr_bi;`
267			`s0_wdata_bo = m0_wdata_bi;`
268			`s0_writemask_bo = m0_writemask_bi;`
269			`end`
270			`else if (m1_s0_enb == 1'b1)`
271			`begin`
272			`s0_enb_o = m1_enb_i;`
273			`s0_we_o = m1_we_i;`
274			`s0_addr_bo = m1_addr_bi;`
275			`s0_wdata_bo = m1_wdata_bi;`
276			`s0_writemask_bo = m1_writemask_bi;`
277			`end`
278			`end`
279
280			`always @*`
281			`begin`
282			`s1_enb_o = 1'b0;`
283			`s1_we_o = 1'b0;`
284			`s1_addr_bo = 32'hx;`
285			`s1_wdata_bo = 32'hx;`
286			`s1_writemask_bo = 4'hx;`
287			`if (s1_pending == 1'b1)`
288			`begin`
289			`if (s1_curmaster == 1'b0)`
290			`begin`
291			`s1_enb_o = m0_enb_i;`
292			`s1_we_o = m0_we_i;`
293			`s1_addr_bo = m0_addr_bi;`
294			`s1_wdata_bo = m0_wdata_bi;`
295			`s1_writemask_bo = m0_writemask_bi;`
296			`end`
297			`else`
298			`begin`
299			`s1_enb_o = m1_enb_i;`
300			`s1_we_o = m1_we_i;`
301			`s1_addr_bo = m1_addr_bi;`
302			`s1_wdata_bo = m1_wdata_bi;`
303			`s1_writemask_bo = m1_writemask_bi;`
304			`end`
305			`end`
306			`else if (m0_s1_enb == 1'b1)`
307			`begin`
308			`s1_enb_o = m0_enb_i;`
309			`s1_we_o = m0_we_i;`
310			`s1_addr_bo = m0_addr_bi;`
311			`s1_wdata_bo = m0_wdata_bi;`
312			`s1_writemask_bo = m0_writemask_bi;`
313			`end`
314			`else if (m1_s1_enb == 1'b1)`
315			`begin`
316			`s1_enb_o = m1_enb_i;`
317			`s1_we_o = m1_we_i;`
318			`s1_addr_bo = m1_addr_bi;`
319			`s1_wdata_bo = m1_wdata_bi;`
320			`s1_writemask_bo = m1_writemask_bi;`
321			`end`
322			`end`
323
324			`always @*`
325			`begin`
326			`s2_enb_o = 1'b0;`
327			`s2_we_o = 1'b0;`
328			`s2_addr_bo = 32'hx;`
329			`s2_wdata_bo = 32'hx;`
330			`s2_writemask_bo = 4'hx;`
331			`if (s2_pending == 1'b1)`
332			`begin`
333			`if (s2_curmaster == 1'b0)`
334			`begin`
335			`s2_enb_o = m0_enb_i;`
336			`s2_we_o = m0_we_i;`
337			`s2_addr_bo = m0_addr_bi;`
338			`s2_wdata_bo = m0_wdata_bi;`
339			`s2_writemask_bo = m0_writemask_bi;`
340			`end`
341			`else`
342			`begin`
343			`s2_enb_o = m1_enb_i;`
344			`s2_we_o = m1_we_i;`
345			`s2_addr_bo = m1_addr_bi;`
346			`s2_wdata_bo = m1_wdata_bi;`
347			`s2_writemask_bo = m1_writemask_bi;`
348			`end`
349			`end`
350			`else if (m0_s2_enb == 1'b1)`
351			`begin`
352			`s2_enb_o = m0_enb_i;`
353			`s2_we_o = m0_we_i;`
354			`s2_addr_bo = m0_addr_bi;`
355			`s2_wdata_bo = m0_wdata_bi;`
356			`s2_writemask_bo = m0_writemask_bi;`
357			`end`
358			`else if (m1_s2_enb == 1'b1)`
359			`begin`
360			`s2_enb_o = m1_enb_i;`
361			`s2_we_o = m1_we_i;`
362			`s2_addr_bo = m1_addr_bi;`
363			`s2_wdata_bo = m1_wdata_bi;`
364			`s2_writemask_bo = m1_writemask_bi;`
365			`end`
366			`end`
367
368			`// Master drivers`
369			`always @*`
370			`begin`
371			`m0_ack_o = 1'b0;`
372			`m0_rdata_bo = 32'hx;`
373			`if ((s0_pending == 1'b1) && (s0_curmaster == 1'b0))`
374			`begin`
375			`m0_ack_o = s0_ack_i;`
376			`m0_rdata_bo = s0_rdata_bi;`
377			`end`
378			`else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b0))`
379			`begin`
380			`m0_ack_o = s1_ack_i;`
381			`m0_rdata_bo = s1_rdata_bi;`
382			`end`
383			`else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b0))`
384			`begin`
385			`m0_ack_o = s2_ack_i;`
386			`m0_rdata_bo = s2_rdata_bi;`
387			`end`
388			`else if (m0_s0_enb == 1'b1)`
389			`begin`
390			`m0_ack_o = s0_ack_i;`
391			`m0_rdata_bo = s0_rdata_bi;`
392			`end`
393			`else if (m0_s1_enb == 1'b1)`
394			`begin`
395			`m0_ack_o = s1_ack_i;`
396			`m0_rdata_bo = s1_rdata_bi;`
397			`end`
398			`else if (m0_s2_enb == 1'b1)`
399			`begin`
400			`m0_ack_o = s2_ack_i;`
401			`m0_rdata_bo = s2_rdata_bi;`
402			`end`
403			`end`
404
405			`always @*`
406			`begin`
407			`m1_ack_o = 1'b0;`
408			`m1_rdata_bo = 32'hx;`
409			`if ((s0_pending == 1'b1) && (s0_curmaster == 1'b1))`
410			`begin`
411			`m1_ack_o = s0_ack_i;`
412			`m1_rdata_bo = s0_rdata_bi;`
413			`end`
414			`else if ((s1_pending == 1'b1) && (s1_curmaster == 1'b1))`
415			`begin`
416			`m1_ack_o = s1_ack_i;`
417			`m1_rdata_bo = s1_rdata_bi;`
418			`end`
419			`else if ((s2_pending == 1'b1) && (s2_curmaster == 1'b1))`
420			`begin`
421			`m1_ack_o = s2_ack_i;`
422			`m1_rdata_bo = s2_rdata_bi;`
423			`end`
424			`else if (m1_s0_enb == 1'b1)`
425			`begin`
426			`m1_ack_o = s0_ack_i;`
427			`m1_rdata_bo = s0_rdata_bi;`
428			`end`
429			`else if (m1_s1_enb == 1'b1)`
430			`begin`
431			`m1_ack_o = s1_ack_i;`
432			`m1_rdata_bo = s1_rdata_bi;`
433			`end`
434			`else if (m1_s2_enb == 1'b1)`
435			`begin`
436			`m1_ack_o = s2_ack_i;`
437			`m1_rdata_bo = s2_rdata_bi;`
438			`end`
439			`end`
440
441			`endmodule`