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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_int_controller.v] - Blame information for rev 5

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1 5 AlexAntono 
/*
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 PSS
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 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
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 All rights reserved.
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 Version 0.99
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 The FreeBSD license
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 Redistribution and use in source and binary forms, with or without
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 modification, are permitted provided that the following conditions
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 are met:
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 1. Redistributions of source code must retain the above copyright
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    notice, this list of conditions and the following disclaimer.
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 2. Redistributions in binary form must reproduce the above
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    copyright notice, this list of conditions and the following
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    disclaimer in the documentation and/or other materials
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    provided with the distribution.
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 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
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 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module pss_int_controller
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(
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        input clk_i, rst_i,
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        input [7:0] interrupt_bi,
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        // control interface
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        output ie_o,
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        input ie_we_i,
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        input ie_data_i,
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        input [7:0] mask_bi,
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        output [7:0] pending_bo,
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        input clr_cmd_i,
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        input [7:0] clr_code_bi,
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        // cpu interface
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        output reg cpu_req_o,
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        input cpu_ack_i
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);
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reg [7:0] int_req, int_req_next;
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reg IE;
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wire [7:0] interrupt_masked;
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assign interrupt_masked = interrupt_bi & mask_bi;
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assign pending_bo = int_req;
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assign ie_o = IE;
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always @*
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        begin
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        // default
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        int_req_next = int_req;
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        // deasserting from cpu
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        if (clr_cmd_i == 1'b1) int_req_next = int_req_next & ~clr_code_bi;
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        // asserting from external interrupts
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        int_req_next = int_req_next | interrupt_masked;
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        end
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always @(posedge clk_i)
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        begin
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        if (rst_i)
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                int_req <= 8'h0;
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        else
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                int_req <= int_req_next;
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        end
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always @(posedge clk_i)
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        begin
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        if (rst_i)
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                begin
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                IE <= 1'b0;
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                cpu_req_o <= 1'b0;
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                end
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        else
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                begin
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                if (ie_we_i == 1'b1)
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                        IE <= ie_data_i;
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                if ((IE == 1'b1) && (int_req != 8'h0))
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                        begin
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                        cpu_req_o <= 1'b1;
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                        IE <= 1'b0;
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                        end
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                else if (cpu_ack_i == 1'b1)
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                        cpu_req_o <= 1'b0;
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                end
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        end
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endmodule

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