Subversion Repositories pss

/*

 PSS

 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>

 All rights reserved.

 Version 0.9.0

 The FreeBSD license

 Redistribution and use in source and binary forms, with or without

 modification, are permitted provided that the following conditions

 are met:

 1. Redistributions of source code must retain the above copyright

    notice, this list of conditions and the following disclaimer.

 2. Redistributions in binary form must reproduce the above

    copyright notice, this list of conditions and the following

    disclaimer in the documentation and/or other materials

    provided with the distribution.

 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY

 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,

 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,

 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*/

module PSS_MotherBlock

#(

        parameter A31_DEFAULT = 1,

        parameter CPU_RESET_DEFAULT = 1,

        parameter EXT_RESET_DEFAULT = 1,

        parameter MEM_SIZE_KB = 1

)

(

        input clk_i,

        input  arst_i,

        output srst_o,

        input  srst_i,

        output ext_rst_o,

        input [3:0] INT_bi,

        output cpu_ireq_o,

        input  cpu_iack_i,

        //// Masters ////

        // Debug bus //

        input dbg_enb_i,

        input dbg_we_i,

        input [31:0] dbg_addr_bi,

        input [31:0] dbg_wdata_bi,

        output dbg_ack_o,

        output [31:0] dbg_rdata_bo,

        // ZPU bus //

        input cpu_enb_i,

        input cpu_we_i,

        input [31:0] cpu_wdata_bi,

        input [31:0] cpu_addr_bi,

        input [3:0] cpu_writemask_bi,

        output cpu_ack_o,

        output [31:0] cpu_rdata_bo,

        //// Slaves ////

        // RAM0 bus //

        output [31:0] ram0_addr_bo,

        output ram0_we_o,

        output [31:0] ram0_wdata_bo,

        input [31:0] ram0_rdata_bi,

        // RAM1 bus //

        output [31:0] ram1_addr_bo,

        output ram1_we_o,

        output [31:0] ram1_wdata_bo,

        input  [31:0] ram1_rdata_bi,

        // Expansion bus //

        output reg xport_req_o,

        input  xport_ack_i,

        input  xport_err_i,

        output reg xport_we_o,

        output reg [31:0] xport_addr_bo,

        output reg [31:0] xport_wdata_bo,

        input xport_resp_i,

        input [31:0] xport_rdata_bi,

        input  cpu_present_i,

        input  [31:0] cpu_pc_bi,

        input  cpu_break_i,

        output cpu_reset_o,

        output cpu_enb_o

);

wire app_reset;

assign app_reset = srst_i | srst_o;

pss_reset_cntrl reset_cntrl

(

        .clk_i(clk_i),

        .arst_i(arst_i),

        .srst_o(srst_o)

);

// interrupts

wire [3:0]  INT;

wire            bus_error_int;

wire            trap_int;

wire            sgi_int;

wire            dma_int;

wire bus_error;

wire [31:0] bus_error_addr;

assign bus_error_int = bus_error;

// INTC programming interface

wire            intc_ie;

wire            intc_ie_we;

wire            intc_ie_data;

wire [7:0]  intc_mask;

wire [7:0]       intc_pending;

wire            intc_clr_cmd;

wire [7:0]       intc_clr_code;

pss_edge_detector edge_det0

( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[0]), .out(INT[0]) );

pss_edge_detector edge_det1

( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[1]), .out(INT[1]) );

pss_edge_detector edge_det2

( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[2]), .out(INT[2]) );

pss_edge_detector edge_det3

( .clk_i(clk_i), .rst_i(rst_i), .in(INT_bi[3]), .out(INT[3]) );

// Interrupt controller

pss_int_controller int_controller

(

        .clk_i(clk_i),

        .rst_i(rst_i),

        .interrupt_bi({INT, dma_int, sgi_int, trap_int, bus_error_int}),

        .ie_o(intc_ie),

        .ie_we_i(intc_ie_we),

        .ie_data_i(intc_ie_data),

        .mask_bi(intc_mask),

        .pending_bo(intc_pending),

        .clr_cmd_i(intc_clr_cmd),

        .clr_code_bi(intc_clr_code),

        .cpu_req_o(cpu_ireq_o),

        .cpu_ack_i(cpu_iack_i)

);

assign cpu_enb_o = 1'b1;

reg trap_enable;

reg [31:0] trap_addr;

wire dma_req, dma_cmd, dma_autoinc;

wire [31:0] dma_sourceaddr;

wire [31:0] dma_destaddr;

wire [31:0] dma_size;

wire a31;

wire dma_works, bb_works;

////////

wire sfr_enb;

wire sfr_we;

wire [31:0] sfr_wdata;

wire [31:0] sfr_addr;

wire [3:0] sfr_writemask;

wire sfr_ack;

wire [31:0] sfr_rdata;

wire ext_enb;

wire ext_we;

wire [31:0] ext_wdata;

wire [31:0] ext_addr;

wire [3:0] ext_writemask;

wire ext_ack;

wire [31:0] ext_rdata;

// RAM0 control //

wire ram0_enb;

reg ram0_ack, ram0_ack_rd;

always @(posedge clk_i)

        begin

        if (app_reset == 1'b1) ram0_ack_rd <= 1'b0;

        else if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b0) && (ram0_ack_rd == 1'b0)) ram0_ack_rd <= 1'b1;

        else ram0_ack_rd <= 1'b0;

        end

always @*

        begin

        if ((ram0_enb == 1'b1) && (ram0_we_o == 1'b1)) ram0_ack = 1'b1;

        else ram0_ack = ram0_ack_rd;

        end

PSS_IC

#(

        .MEM_SIZE_KB(MEM_SIZE_KB)

)

IC_fabric

(

        .clk_i(clk_i),

        .rst_i(app_reset),

        //// Masters ////

        .m0_enb_i(dbg_enb_i),

        .m0_we_i(dbg_we_i),

        .m0_addr_bi(dbg_addr_bi),

        .m0_wdata_bi(dbg_wdata_bi),

        .m0_writemask_bi(dbg_writemask_bi),

        .m0_ack_o(dbg_ack_o),

        .m0_rdata_bo(dbg_rdata_bo),

        .m1_enb_i(cpu_enb_i),

        .m1_we_i(cpu_we_i),

        .m1_addr_bi(cpu_addr_bi),

        .m1_wdata_bi(cpu_wdata_bi),

        .m1_writemask_bi(cpu_writemask_bi),

        .m1_ack_o(cpu_ack_o),

        .m1_rdata_bo(cpu_rdata_bo),

        //// Slaves ////

        .s0_enb_o(ram0_enb),

        .s0_we_o(ram0_we_o),

        .s0_addr_bo(ram0_addr_bo),

        .s0_wdata_bo(ram0_wdata_bo),

        .s0_writemask_bo(ram0_writemask_bo),

        .s0_ack_i(ram0_ack),

        .s0_rdata_bi(ram0_rdata_bi),

        .s1_enb_o(sfr_enb),

        .s1_we_o(sfr_we),

        .s1_addr_bo(sfr_addr),

        .s1_wdata_bo(sfr_wdata),

        .s1_writemask_bo(sfr_writemask),

        .s1_ack_i(sfr_ack),

        .s1_rdata_bi(sfr_rdata),

        .s2_enb_o(ext_enb),

        .s2_we_o(ext_we),

        .s2_addr_bo(ext_addr),

        .s2_wdata_bo(ext_wdata),

        .s2_writemask_bo(ext_writemask),

        .s2_ack_i(ext_ack),

        .s2_rdata_bi(ext_rdata),

        .error_o(bus_error),

        .error_addr_bo(bus_error_addr)

);

PSS_SFR

#(

        .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),

        .EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),

        .A31_DEFAULT(A31_DEFAULT),

        .MEM_SIZE_KB(MEM_SIZE_KB)

)

SFR

(

        .clk_i(clk_i),

        .rst_i(app_reset),

        .bus_enb_i(sfr_enb),

        .bus_we_i(sfr_we),

        .bus_wdata_bi(sfr_wdata),

        .bus_addr_bi(sfr_addr),

        .bus_writemask_bi(sfr_writemask),

        .bus_ack_o(sfr_ack),

        .bus_rdata_bo(sfr_rdata),

        .cpu_present_i(cpu_present_i),

        .cpu_break_i(cpu_break_i),

        .cpu_pc_bi(cpu_pc_bi),

        .trap_cpu_enb_i(cpu_enb_i),

        .trap_cpu_addr_bi(cpu_addr_bi),

        .cpu_reset_o(cpu_reset_o),

        .ext_reset_o(ext_rst_o),

        .a31_o(a31),

        .bus_error_i(bus_error),

        .bus_error_addr_bi(bus_error_addr),

        .sgi_int_o(sgi_int),

        .trap_int_o(trap_int),

        .intc_ie_i(intc_ie),

        .intc_pending_bi(intc_pending),

        .intc_ie_we_o(intc_ie_we),

        .intc_ie_data_o(intc_ie_data),

        .intc_mask_bo(intc_mask),

        .intc_clr_cmd_o(intc_clr_cmd),

        .intc_clr_code_bo(intc_clr_code),

        .dma_req_o(dma_req),

        .dma_cmd_o(dma_cmd),

        .dma_autoinc_o(dma_autoinc),

        .dma_size_bo(dma_size),

        .dma_sourceaddr_bo(dma_sourceaddr),

        .dma_destaddr_bo(dma_destaddr)

);

wire bb_xport_req;

reg  bb_xport_ack;

reg  bb_xport_err;

wire bb_xport_we;

wire [31:0] bb_xport_addr;

wire [31:0] bb_xport_wdata;

reg  bb_xport_resp;

reg [31:0] bb_xport_rdata;

wire dma_xport_req;

reg  dma_xport_ack;

reg  dma_xport_err;

wire dma_xport_we;

wire [31:0] dma_xport_addr;

wire [31:0] dma_xport_wdata;

reg  dma_xport_resp;

reg [31:0] dma_xport_rdata;

PSS_DMA DMA

(

        .clk_i(clk_i),

        .rst_i(app_reset),

        .xport_busy_i(bb_works),

        .xport_busy_o(dma_works),

        .dma_int_o(dma_int),

        .dma_req_i(dma_req),

        .dma_cmd_i(dma_cmd),

        .dma_autoinc_i(dma_autoinc),

        .dma_size_bi(REG_DMA_SIZE),

        .dma_sourceaddr_bi(REG_DMA_SOURCEADDR),

        .dma_destaddr_bi(REG_DMA_DESTADDR),

        .ram_addr_bo(ram1_addr_bo),

        .ram_we_o(ram1_we_o),

        .ram_wdata_bo(ram1_wdata_bo),

        .ram_rdata_bi(ram1_rdata_bi),

        .xport_req_o(dma_xport_req),

        .xport_ack_i(dma_xport_ack),

        .xport_err_i(dma_xport_err),

        .xport_we_o(dma_xport_we),

        .xport_addr_bo(dma_xport_addr),

        .xport_wdata_bo(dma_xport_wdata),

        .xport_resp_i(dma_xport_resp),

        .xport_rdata_bi(dma_xport_rdata)

);

PSS_BusBridge BusBridge

(

        .clk_i(clk_i),

        .rst_i(app_reset),

        .xport_busy_i(dma_works),

        .xport_busy_o(bb_works),

        .a31_i(a31),

        .bus_enb_i(ext_enb),

        .bus_we_i(ext_we),

        .bus_addr_bi(ext_addr),

        .bus_wdata_bi(ext_wdata),

        .bus_writemask_bi(ext_writemask),

        .bus_ack_o(ext_ack),

        .bus_rdata_bo(ext_rdata),

        // Expansion bus //

        .xport_req_o(bb_xport_req),

        .xport_ack_i(bb_xport_ack),

        .xport_err_i(bb_xport_err),

        .xport_we_o(bb_xport_we),

        .xport_addr_bo(bb_xport_addr),

        .xport_wdata_bo(bb_xport_wdata),

        .xport_resp_i(bb_xport_resp),

        .xport_rdata_bi(bb_xport_rdata)

);

// bus switch

always @*

        begin

        bb_xport_ack = 1'b0;

        bb_xport_err = 1'b0;

        bb_xport_resp = 1'b0;

        bb_xport_rdata = 32'bx;

        dma_xport_ack = 1'b0;

        dma_xport_err = 1'b0;

        dma_xport_resp = 1'b0;

        dma_xport_rdata = 32'bx;

        if (dma_works == 1'b0)          // switch to bus bridge

                begin

                bb_xport_ack = xport_ack_i;

                bb_xport_err = xport_err_i;

                bb_xport_resp = xport_resp_i;

                bb_xport_rdata = xport_rdata_bi;

                xport_req_o = bb_xport_req;

                xport_we_o = bb_xport_we;

                xport_addr_bo = bb_xport_addr;

                xport_wdata_bo = bb_xport_wdata;

                end

        else                                            // switch to dma

                begin

                dma_xport_ack = xport_ack_i;

                dma_xport_err = xport_err_i;

                dma_xport_resp = xport_resp_i;

                dma_xport_rdata = xport_rdata_bi;

                xport_req_o = dma_xport_req;

                xport_we_o = dma_xport_we;

                xport_addr_bo = dma_xport_addr;

                xport_wdata_bo = dma_xport_wdata;

                end

        end

endmodule