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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_sfr.v] - Blame information for rev 7

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module PSS_SFR
#(
        parameter CPU_RESET_DEFAULT = 1,
        parameter EXT_RESET_DEFAULT = 1,
        parameter A31_DEFAULT = 1,
        parameter MEM_SIZE_KB = 1
)
(
        input clk_i, rst_i,
 
        // bus controls
        input bus_enb_i,
        input bus_we_i,
        input [31:0] bus_wdata_bi,
        input [31:0] bus_addr_bi,
        input [3:0] bus_writemask_bi,
        output reg bus_ack_o,
        output reg [31:0] bus_rdata_bo,
 
        // special function signals
        input cpu_present_i,
        input cpu_break_i,
        input [31:0] cpu_pc_bi,
 
        input trap_cpu_enb_i,
        input [31:0] trap_cpu_addr_bi,
 
        output reg cpu_reset_o,
        output reg ext_reset_o,
        output cpu_enb_o,
        output reg a31_o,
 
        input bus_error_i,
        input [31:0] bus_error_addr_bi,
 
        // interrupts
        output reg bus_error_int_o,
        output reg sgi_int_o,
        output reg trap_int_o,
 
        // interrupt controller signals
        input intc_ie_i,
        input [7:0] intc_pending_bi,
        output reg intc_ie_we_o,
        output reg intc_ie_data_o,
        output reg [7:0] intc_mask_bo,
        output reg intc_clr_cmd_o,
        output reg [7:0] intc_clr_code_bo,
 
        // DMA controls
        output reg dma_req_o,
        output reg dma_cmd_o,
        output reg dma_autoinc_o,
        output reg [31:0] dma_size_bo,
        output reg [31:0] dma_sourceaddr_bo,
        output reg [31:0] dma_destaddr_bo
);
 
//// System registers ////
localparam REG_CPU_CONTROL_ADDR         = 8'h00;
localparam REG_CPU_PC_ADDR                      = 8'h04;
localparam REG_A31                                      = 8'h08;
 
localparam REG_INTC_CONTROL_ADDR        = 8'h10;
localparam REG_INTC_MASK_ADDR           = 8'h14;
localparam REG_INTC_REQ_ADDR            = 8'h18;
localparam REG_MEM_SIZE_KB                      = 8'h1C;
 
localparam REG_DMA_CONTROL_ADDR         = 8'h20;
localparam REG_DMA_SOURCEADDR_ADDR      = 8'h24;
localparam REG_DMA_DESTADDR_ADDR        = 8'h28;
localparam REG_DMA_SIZE_ADDR            = 8'h2C;
 
localparam REG_SGI_ADDR                         = 8'h30;
 
localparam REG_BUS_ERROR_ADDR_ADDR      = 8'h38;
localparam REG_BUS_ERROR_PC_ADDR        = 8'h3C;
 
localparam REG_TRAP_CONTROL_ADDR        = 8'h40;
localparam REG_TRAP_ADDR_ADDR           = 8'h44;
 
assign cpu_enb_o = 1'b1;
 
reg trap_enable;
reg [31:0] trap_addr;
 
reg [31:0] bus_error_pc;
reg [31:0] bus_error_addr;
 
reg bus_ack_rd;
always @(posedge clk_i)
        begin
        if (rst_i) bus_ack_rd <= 1'b0;
        else if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b0) && (bus_ack_rd == 1'b0)) bus_ack_rd <= 1'b1;
        else bus_ack_rd <= 1'b0;
        end
 
always @*
        begin
        if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b1)) bus_ack_o = 1'b1;
        else bus_ack_o = bus_ack_rd;
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
 
                cpu_reset_o <= CPU_RESET_DEFAULT;
                ext_reset_o <= EXT_RESET_DEFAULT;
                a31_o <= A31_DEFAULT;
 
                trap_enable <= 1'b0;
                trap_addr <= 32'h0;
 
                sgi_int_o <= 1'b0;
 
                dma_req_o <= 1'b0;
                dma_cmd_o <= 1'b0;
                dma_autoinc_o <= 1'b0;
 
                intc_ie_we_o <= 1'b0;
                intc_ie_data_o <= 1'bx;
                intc_mask_bo <= 8'h0;
                intc_clr_cmd_o <= 1'b0;
                intc_clr_code_bo <= 8'hx;
 
                dma_sourceaddr_bo <= 32'h0;
                dma_destaddr_bo <= 32'h0;
                dma_size_bo <= 32'h0;
                end
        else
                begin
 
                sgi_int_o <= 1'b0;
 
                intc_ie_we_o <= 1'b0;
                intc_clr_cmd_o <= 1'b0;
                bus_rdata_bo <= 32'hx;
 
                dma_req_o <= 1'b0;
 
                if (bus_enb_i == 1'b1)
                        begin
                        if (bus_we_i == 1'b0)
                                case (bus_addr_bi[7:0])
                                        REG_CPU_CONTROL_ADDR:           bus_rdata_bo <= {cpu_present_i, 28'h0, cpu_break_i, ext_reset_o, cpu_reset_o};
                                        REG_CPU_PC_ADDR:                        bus_rdata_bo <= cpu_pc_bi;
                                        REG_A31:                                        bus_rdata_bo <= {31'h0, a31_o};
 
                                        REG_INTC_CONTROL_ADDR:          bus_rdata_bo <= {31'h0, intc_ie_i};
                                        REG_INTC_MASK_ADDR:                     bus_rdata_bo <= {24'h0, intc_mask_bo};
                                        REG_INTC_REQ_ADDR:                      bus_rdata_bo <= {24'h0, intc_pending_bi};
                                        REG_MEM_SIZE_KB:                        bus_rdata_bo <= MEM_SIZE_KB;
 
                                        REG_DMA_SOURCEADDR_ADDR:        bus_rdata_bo <= dma_sourceaddr_bo;
                                        REG_DMA_DESTADDR_ADDR:          bus_rdata_bo <= dma_destaddr_bo;
                                        REG_DMA_SIZE_ADDR:                      bus_rdata_bo <= dma_size_bo;
 
                                        REG_TRAP_CONTROL_ADDR:          bus_rdata_bo <= {31'h0, trap_enable};
                                        REG_TRAP_ADDR_ADDR:                     bus_rdata_bo <= trap_addr;
 
                                        REG_BUS_ERROR_ADDR_ADDR:        bus_rdata_bo <= bus_error_addr;
                                        REG_BUS_ERROR_PC_ADDR:          bus_rdata_bo <= bus_error_pc;
                                endcase
                        else
                                case (bus_addr_bi[7:0])
                                        REG_CPU_CONTROL_ADDR:           begin cpu_reset_o <= bus_wdata_bi[0]; ext_reset_o <= bus_wdata_bi[1]; end
                                        REG_A31:                                        a31_o <= bus_wdata_bi[0];
 
                                        REG_INTC_CONTROL_ADDR:          begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end
                                        REG_INTC_MASK_ADDR:                     intc_mask_bo <= bus_wdata_bi[7:0];
                                        REG_INTC_REQ_ADDR:                      begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end
 
                                        REG_DMA_CONTROL_ADDR:           begin dma_req_o <= 1'b1; dma_cmd_o <= bus_wdata_bi[1]; dma_autoinc_o <= bus_wdata_bi[2]; end
                                        REG_DMA_SOURCEADDR_ADDR:        begin
                                                                                                        if (bus_wdata_bi[31] == 1'b1)
                                                                                                                dma_sourceaddr_bo <= {a31_o, bus_wdata_bi[30:0]};
                                                                                                        else
                                                                                                                dma_sourceaddr_bo <= bus_wdata_bi;
                                                                                                end
                                        REG_DMA_DESTADDR_ADDR:          begin
 
                                                                                                        if (bus_wdata_bi[31] == 1'b1)
                                                                                                                dma_destaddr_bo <= {a31_o, bus_wdata_bi[30:0]};
                                                                                                        else
                                                                                                                dma_destaddr_bo <= bus_wdata_bi;
                                                                                                end
                                        REG_DMA_SIZE_ADDR:                      dma_size_bo <= bus_wdata_bi;
 
                                        REG_SGI_ADDR:                           sgi_int_o <= 1'b1;
 
                                        REG_TRAP_CONTROL_ADDR:          trap_enable <= bus_wdata_bi[0];
                                        REG_TRAP_ADDR_ADDR:                     trap_addr <= bus_wdata_bi;
                                endcase
                        end
                end
        end
 
// trap logic
always @(posedge clk_i)
        begin
        if (rst_i)
                trap_int_o <= 1'b0;
        else
                begin
                trap_int_o <= 1'b0;
                if (trap_enable == 1'b1)
                        if (trap_cpu_enb_i == 1'b1)
                                if (trap_cpu_addr_bi == trap_addr)
                                        trap_int_o <= 1'b1;
                end
        end
 
always @(posedge clk_i)
        begin
        if (rst_i)
                begin
                bus_error_int_o <= 1'b0;
                bus_error_addr <= 32'h0;
                bus_error_pc <= 32'h0;
                end
        else
                begin
                bus_error_int_o <= 1'b0;
                if (bus_error_i == 1'b1)
                        begin
                        bus_error_int_o <= 1'b1;
                        bus_error_addr <= bus_error_addr_bi;
                        bus_error_pc <= cpu_pc_bi;
                        end
                end
        end
 
endmodule

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[/] [pss/] [trunk/] [pss/] [hdl/] [pss/] [zpu_uc/] [motherblock/] [pss_sfr.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	5	AlexAntono	`module PSS_SFR`
2			`#(`
3			`parameter CPU_RESET_DEFAULT = 1,`
4	7	AlexAntono	`parameter EXT_RESET_DEFAULT = 1,`
5	5	AlexAntono	`parameter A31_DEFAULT = 1,`
6			`parameter MEM_SIZE_KB = 1`
7			`)`
8			`(`
9			`input clk_i, rst_i,`
10
11			`// bus controls`
12			`input bus_enb_i,`
13			`input bus_we_i,`
14			`input [31:0] bus_wdata_bi,`
15			`input [31:0] bus_addr_bi,`
16			`input [3:0] bus_writemask_bi,`
17			`output reg bus_ack_o,`
18			`output reg [31:0] bus_rdata_bo,`
19
20			`// special function signals`
21			`input cpu_present_i,`
22			`input cpu_break_i,`
23			`input [31:0] cpu_pc_bi,`
24
25			`input trap_cpu_enb_i,`
26			`input [31:0] trap_cpu_addr_bi,`
27
28			`output reg cpu_reset_o,`
29	7	AlexAntono	`output reg ext_reset_o,`
30	5	AlexAntono	`output cpu_enb_o,`
31			`output reg a31_o,`
32
33			`input bus_error_i,`
34			`input [31:0] bus_error_addr_bi,`
35
36			`// interrupts`
37			`output reg bus_error_int_o,`
38			`output reg sgi_int_o,`
39			`output reg trap_int_o,`
40
41			`// interrupt controller signals`
42			`input intc_ie_i,`
43			`input [7:0] intc_pending_bi,`
44			`output reg intc_ie_we_o,`
45			`output reg intc_ie_data_o,`
46			`output reg [7:0] intc_mask_bo,`
47			`output reg intc_clr_cmd_o,`
48			`output reg [7:0] intc_clr_code_bo,`
49
50			`// DMA controls`
51			`output reg dma_req_o,`
52			`output reg dma_cmd_o,`
53			`output reg dma_autoinc_o,`
54			`output reg [31:0] dma_size_bo,`
55			`output reg [31:0] dma_sourceaddr_bo,`
56			`output reg [31:0] dma_destaddr_bo`
57			`);`
58
59			`//// System registers ////`
60			`localparam REG_CPU_CONTROL_ADDR = 8'h00;`
61			`localparam REG_CPU_PC_ADDR = 8'h04;`
62			`localparam REG_A31 = 8'h08;`
63
64			`localparam REG_INTC_CONTROL_ADDR = 8'h10;`
65			`localparam REG_INTC_MASK_ADDR = 8'h14;`
66			`localparam REG_INTC_REQ_ADDR = 8'h18;`
67			`localparam REG_MEM_SIZE_KB = 8'h1C;`
68
69			`localparam REG_DMA_CONTROL_ADDR = 8'h20;`
70			`localparam REG_DMA_SOURCEADDR_ADDR = 8'h24;`
71			`localparam REG_DMA_DESTADDR_ADDR = 8'h28;`
72			`localparam REG_DMA_SIZE_ADDR = 8'h2C;`
73
74			`localparam REG_SGI_ADDR = 8'h30;`
75
76			`localparam REG_BUS_ERROR_ADDR_ADDR = 8'h38;`
77			`localparam REG_BUS_ERROR_PC_ADDR = 8'h3C;`
78
79			`localparam REG_TRAP_CONTROL_ADDR = 8'h40;`
80			`localparam REG_TRAP_ADDR_ADDR = 8'h44;`
81
82			`assign cpu_enb_o = 1'b1;`
83
84			`reg trap_enable;`
85			`reg [31:0] trap_addr;`
86
87			`reg [31:0] bus_error_pc;`
88			`reg [31:0] bus_error_addr;`
89
90			`reg bus_ack_rd;`
91			`always @(posedge clk_i)`
92			`begin`
93			`if (rst_i) bus_ack_rd <= 1'b0;`
94			`else if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b0) && (bus_ack_rd == 1'b0)) bus_ack_rd <= 1'b1;`
95			`else bus_ack_rd <= 1'b0;`
96			`end`
97
98			`always @*`
99			`begin`
100			`if ((bus_enb_i == 1'b1) && (bus_we_i == 1'b1)) bus_ack_o = 1'b1;`
101			`else bus_ack_o = bus_ack_rd;`
102			`end`
103
104			`always @(posedge clk_i)`
105			`begin`
106			`if (rst_i)`
107			`begin`
108
109			`cpu_reset_o <= CPU_RESET_DEFAULT;`
110	7	AlexAntono	`ext_reset_o <= EXT_RESET_DEFAULT;`
111	5	AlexAntono	`a31_o <= A31_DEFAULT;`
112
113			`trap_enable <= 1'b0;`
114			`trap_addr <= 32'h0;`
115
116			`sgi_int_o <= 1'b0;`
117
118			`dma_req_o <= 1'b0;`
119			`dma_cmd_o <= 1'b0;`
120			`dma_autoinc_o <= 1'b0;`
121
122			`intc_ie_we_o <= 1'b0;`
123			`intc_ie_data_o <= 1'bx;`
124			`intc_mask_bo <= 8'h0;`
125			`intc_clr_cmd_o <= 1'b0;`
126			`intc_clr_code_bo <= 8'hx;`
127
128			`dma_sourceaddr_bo <= 32'h0;`
129			`dma_destaddr_bo <= 32'h0;`
130			`dma_size_bo <= 32'h0;`
131			`end`
132			`else`
133			`begin`
134
135			`sgi_int_o <= 1'b0;`
136
137			`intc_ie_we_o <= 1'b0;`
138			`intc_clr_cmd_o <= 1'b0;`
139			`bus_rdata_bo <= 32'hx;`
140
141			`dma_req_o <= 1'b0;`
142
143			`if (bus_enb_i == 1'b1)`
144			`begin`
145			`if (bus_we_i == 1'b0)`
146			`case (bus_addr_bi[7:0])`
147	7	AlexAntono	`REG_CPU_CONTROL_ADDR: bus_rdata_bo <= {cpu_present_i, 28'h0, cpu_break_i, ext_reset_o, cpu_reset_o};`
148	5	AlexAntono	`REG_CPU_PC_ADDR: bus_rdata_bo <= cpu_pc_bi;`
149			`REG_A31: bus_rdata_bo <= {31'h0, a31_o};`
150
151			`REG_INTC_CONTROL_ADDR: bus_rdata_bo <= {31'h0, intc_ie_i};`
152			`REG_INTC_MASK_ADDR: bus_rdata_bo <= {24'h0, intc_mask_bo};`
153			`REG_INTC_REQ_ADDR: bus_rdata_bo <= {24'h0, intc_pending_bi};`
154			`REG_MEM_SIZE_KB: bus_rdata_bo <= MEM_SIZE_KB;`
155
156			`REG_DMA_SOURCEADDR_ADDR: bus_rdata_bo <= dma_sourceaddr_bo;`
157			`REG_DMA_DESTADDR_ADDR: bus_rdata_bo <= dma_destaddr_bo;`
158			`REG_DMA_SIZE_ADDR: bus_rdata_bo <= dma_size_bo;`
159
160			`REG_TRAP_CONTROL_ADDR: bus_rdata_bo <= {31'h0, trap_enable};`
161			`REG_TRAP_ADDR_ADDR: bus_rdata_bo <= trap_addr;`
162
163			`REG_BUS_ERROR_ADDR_ADDR: bus_rdata_bo <= bus_error_addr;`
164			`REG_BUS_ERROR_PC_ADDR: bus_rdata_bo <= bus_error_pc;`
165			`endcase`
166			`else`
167			`case (bus_addr_bi[7:0])`
168	7	AlexAntono	`REG_CPU_CONTROL_ADDR: begin cpu_reset_o <= bus_wdata_bi[0]; ext_reset_o <= bus_wdata_bi[1]; end`
169	5	AlexAntono	`REG_A31: a31_o <= bus_wdata_bi[0];`
170
171			`REG_INTC_CONTROL_ADDR: begin intc_ie_we_o <= 1'b1; intc_ie_data_o <= bus_wdata_bi[0]; end`
172			`REG_INTC_MASK_ADDR: intc_mask_bo <= bus_wdata_bi[7:0];`
173			`REG_INTC_REQ_ADDR: begin intc_clr_cmd_o <= 1'b1; intc_clr_code_bo <= bus_wdata_bi[7:0]; end`
174
175			`REG_DMA_CONTROL_ADDR: begin dma_req_o <= 1'b1; dma_cmd_o <= bus_wdata_bi[1]; dma_autoinc_o <= bus_wdata_bi[2]; end`
176			`REG_DMA_SOURCEADDR_ADDR: begin`
177			`if (bus_wdata_bi[31] == 1'b1)`
178			`dma_sourceaddr_bo <= {a31_o, bus_wdata_bi[30:0]};`
179			`else`
180			`dma_sourceaddr_bo <= bus_wdata_bi;`
181			`end`
182			`REG_DMA_DESTADDR_ADDR: begin`
183
184			`if (bus_wdata_bi[31] == 1'b1)`
185			`dma_destaddr_bo <= {a31_o, bus_wdata_bi[30:0]};`
186			`else`
187			`dma_destaddr_bo <= bus_wdata_bi;`
188			`end`
189			`REG_DMA_SIZE_ADDR: dma_size_bo <= bus_wdata_bi;`
190
191			`REG_SGI_ADDR: sgi_int_o <= 1'b1;`
192
193			`REG_TRAP_CONTROL_ADDR: trap_enable <= bus_wdata_bi[0];`
194			`REG_TRAP_ADDR_ADDR: trap_addr <= bus_wdata_bi;`
195			`endcase`
196			`end`
197			`end`
198			`end`
199
200			`// trap logic`
201			`always @(posedge clk_i)`
202			`begin`
203			`if (rst_i)`
204			`trap_int_o <= 1'b0;`
205			`else`
206			`begin`
207			`trap_int_o <= 1'b0;`
208			`if (trap_enable == 1'b1)`
209			`if (trap_cpu_enb_i == 1'b1)`
210			`if (trap_cpu_addr_bi == trap_addr)`
211			`trap_int_o <= 1'b1;`
212			`end`
213			`end`
214
215			`always @(posedge clk_i)`
216			`begin`
217			`if (rst_i)`
218			`begin`
219			`bus_error_int_o <= 1'b0;`
220			`bus_error_addr <= 32'h0;`
221			`bus_error_pc <= 32'h0;`
222			`end`
223			`else`
224			`begin`
225			`bus_error_int_o <= 1'b0;`
226			`if (bus_error_i == 1'b1)`
227			`begin`
228			`bus_error_int_o <= 1'b1;`
229			`bus_error_addr <= bus_error_addr_bi;`
230			`bus_error_pc <= cpu_pc_bi;`
231			`end`
232			`end`
233			`end`
234
235			`endmodule`