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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.9.0
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
module ZPU_uC
#(
        parameter CPU_PRESENT = 1,
        parameter CPU_RESET_DEFAULT = 1,
        parameter EXT_RESET_DEFAULT = 1,
        parameter A31_DEFAULT = 1,
        parameter MEM_DATA = "data.bin",
        parameter MEM_SIZE_KB = 1
)
(
        input  clk_i,
 
        input  arst_i,
        output srst_o,
        input  srst_i,
        output ext_rst_o,
 
        input [3:0] INT_bi,
 
        // Expansion bus
        output xport_req_o,
        input  xport_ack_i,
        input  xport_err_i,
        output xport_we_o,
        output [31:0] xport_addr_bo,
        output [31:0] xport_wdata_bo,
        input  xport_resp_i,
        input  [31:0] xport_rdata_bi,
 
        //Debug interface
        input  dbg_enb_i,
        input  dbg_wr_i,
        input  [31:0] dbg_addr_bi,
        input  [31:0] dbg_data_bi,
        output dbg_resp_o,
        output [31:0] dbg_data_bo
);
 
wire app_reset;
assign app_reset = srst_i | srst_o;
 
// CPU system bus
wire            cpu_bus_enb;
wire            cpu_bus_we;
wire            cpu_bus_ack;
wire [31:0] cpu_bus_read;
wire [31:0] cpu_bus_write;
wire [31:0] cpu_bus_addr;
wire [3:0]  cpu_bus_writemask;
 
// MAU-RAM bus
wire [31:0] ram0_bus_addr;
wire            ram0_bus_we;
wire [31:0] ram0_bus_rddata;
wire [31:0] ram0_bus_wrdata;
 
wire [31:0] ram1_bus_addr;
wire            ram1_bus_we;
wire [31:0] ram1_bus_rddata;
wire [31:0] ram1_bus_wrdata;
 
// CPU control
wire cpu_present;
wire [63:0] zpu_status;
wire cpu_break;
wire [31:0] cpu_pc;
 
wire            cpu_interrupt;
wire            cpu_interrupt_ack;
wire            cpu_reset;
wire            cpu_enb;
 
generate
        if (CPU_PRESENT == 1)
 
// Processor core
zpu_core
#(
        .stack_address((MEM_SIZE_KB * 1024) - 8)
)
zpu_core
(
        .clk(clk_i),
        .sreset(app_reset | cpu_reset),
        .enable(cpu_enb),
        .cpu_present(cpu_present),
        .pc_bo(cpu_pc),
 
        .mem_req(cpu_bus_enb),
        .mem_we(cpu_bus_we),
        .mem_ack(cpu_bus_ack),
        .mem_read(cpu_bus_read),
        .mem_write(cpu_bus_write),
        .out_mem_addr(cpu_bus_addr),
        .mem_writeMask(cpu_bus_writemask),
 
        .interrupt(cpu_interrupt),
        .interrupt_ack(cpu_interrupt_ack),
        .break_o(cpu_break),
        .zpu_status(zpu_status)
);
 
        else
 
zpu_core_stub zpu_core
(
        .clk(clk_i),
        .sreset(app_reset | cpu_reset),
        .enable(cpu_enb),
        .cpu_present(cpu_present),
        .pc_bo(cpu_pc),
 
        .mem_req(cpu_bus_enb),
        .mem_we(cpu_bus_we),
        .mem_ack(cpu_bus_ack),
        .mem_read(cpu_bus_read),
        .mem_write(cpu_bus_write),
        .out_mem_addr(cpu_bus_addr),
        .mem_writeMask(cpu_bus_writemask),
 
        .interrupt(cpu_interrupt),
        .interrupt_ack(cpu_interrupt_ack),
        .break_o(cpu_break),
        .zpu_status(zpu_status)
);
 
endgenerate
 
 
PSS_MotherBlock
#(
        .A31_DEFAULT(A31_DEFAULT),
        .CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),
        .EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),
        .MEM_SIZE_KB(MEM_SIZE_KB)
)
MotherBlock
(
        .clk_i(clk_i),
 
        .arst_i(arst_i),
        .srst_o(srst_o),
        .srst_i(srst_i),
        .ext_rst_o(ext_rst_o),
 
        .INT_bi(INT_bi),
        .cpu_ireq_o(cpu_interrupt),
        .cpu_iack_i(cpu_interrupt_ack),
 
        //// Masters ////
        // Debug bus //
        .dbg_enb_i(dbg_enb_i),
        .dbg_we_i(dbg_wr_i),
        .dbg_addr_bi(dbg_addr_bi),
        .dbg_wdata_bi(dbg_data_bi),
        .dbg_ack_o(dbg_resp_o),
        .dbg_rdata_bo(dbg_data_bo),
 
        // ZPU bus //
        .cpu_enb_i(cpu_bus_enb),
        .cpu_we_i(cpu_bus_we),
        .cpu_ack_o(cpu_bus_ack),
        .cpu_rdata_bo(cpu_bus_read),
        .cpu_wdata_bi(cpu_bus_write),
        .cpu_addr_bi(cpu_bus_addr),
        .cpu_writemask_bi(cpu_bus_writemask),
 
        //// Slaves ////
        // RAM0 bus //
        .ram0_addr_bo(ram0_bus_addr),
        .ram0_we_o(ram0_bus_we),
        .ram0_wdata_bo(ram0_bus_wrdata),
        .ram0_rdata_bi(ram0_bus_rddata),
 
        // RAM1 bus //
        .ram1_addr_bo(ram1_bus_addr),
        .ram1_we_o(ram1_bus_we),
        .ram1_wdata_bo(ram1_bus_wrdata),
        .ram1_rdata_bi(ram1_bus_rddata),
 
        // Expansion port //
        .xport_req_o(xport_req_o),
        .xport_ack_i(xport_ack_i),
        .xport_err_i(xport_err_i),
        .xport_we_o(xport_we_o),
        .xport_addr_bo(xport_addr_bo),
        .xport_wdata_bo(xport_wdata_bo),
        .xport_resp_i(xport_resp_i),
        .xport_rdata_bi(xport_rdata_bi),
 
        .cpu_present_i(cpu_present),
        .cpu_pc_bi(cpu_pc),
        .cpu_break_i(cpu_break),
        .cpu_reset_o(cpu_reset),
        .cpu_enb_o(cpu_enb)
);
 
ram_dual
#(
        .mem_data(MEM_DATA),
        .dat_width(32),
        .adr_width(32),
        .mem_size((MEM_SIZE_KB * 1024) / 4 )
)
ram_dual_port
(
        .clk(clk_i),
 
        .dat0_i(ram0_bus_wrdata),
    .adr0_i({2'h0, ram0_bus_addr[31:2]}),
    .we0_i(ram0_bus_we),
    .dat0_o(ram0_bus_rddata),
 
    .dat1_i(ram1_bus_wrdata),
    .adr1_i({2'h0, ram1_bus_addr[31:2]}),
    .we1_i(ram1_bus_we),
    .dat1_o(ram1_bus_rddata)
);
 
endmodule

Line No.	Rev	Author	Line
1	2	AlexAntono	`/*`
2			`PSS`
3
4			`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
5			`All rights reserved.`
6
7	5	AlexAntono	`Version 0.9.0`
8	2	AlexAntono
9			`The FreeBSD license`
10
11			`Redistribution and use in source and binary forms, with or without`
12			`modification, are permitted provided that the following conditions`
13			`are met:`
14
15			`1. Redistributions of source code must retain the above copyright`
16			`notice, this list of conditions and the following disclaimer.`
17			`2. Redistributions in binary form must reproduce the above`
18			`copyright notice, this list of conditions and the following`
19			`disclaimer in the documentation and/or other materials`
20			`provided with the distribution.`
21
22			THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
23			`EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
24			`THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A`
25			`PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE`
26			`PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,`
27			`INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
28			`(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
29			`OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
30			`HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
31			`STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
32			`ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
33			`ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`*/`
35
36
37			`module ZPU_uC`
38			`#(`
39			`parameter CPU_PRESENT = 1,`
40			`parameter CPU_RESET_DEFAULT = 1,`
41	7	AlexAntono	`parameter EXT_RESET_DEFAULT = 1,`
42	5	AlexAntono	`parameter A31_DEFAULT = 1,`
43	2	AlexAntono	`parameter MEM_DATA = "data.bin",`
44			`parameter MEM_SIZE_KB = 1`
45			`)`
46			`(`
47	5	AlexAntono	`input clk_i,`
48	2	AlexAntono
49	5	AlexAntono	`input arst_i,`
50			`output srst_o,`
51			`input srst_i,`
52			`output ext_rst_o,`
53
54			`input [3:0] INT_bi,`
55
56	2	AlexAntono	`// Expansion bus`
57			`output xport_req_o,`
58			`input xport_ack_i,`
59			`input xport_err_i,`
60			`output xport_we_o,`
61			`output [31:0] xport_addr_bo,`
62			`output [31:0] xport_wdata_bo,`
63			`input xport_resp_i,`
64			`input [31:0] xport_rdata_bi,`
65
66			`//Debug interface`
67			`input dbg_enb_i,`
68			`input dbg_wr_i,`
69			`input [31:0] dbg_addr_bi,`
70			`input [31:0] dbg_data_bi,`
71			`output dbg_resp_o,`
72			`output [31:0] dbg_data_bo`
73			`);`
74
75	5	AlexAntono	`wire app_reset;`
76			`assign app_reset = srst_i \| srst_o;`
77
78			`// CPU system bus`
79	2	AlexAntono	`wire cpu_bus_enb;`
80			`wire cpu_bus_we;`
81			`wire cpu_bus_ack;`
82			`wire [31:0] cpu_bus_read;`
83			`wire [31:0] cpu_bus_write;`
84			`wire [31:0] cpu_bus_addr;`
85			`wire [3:0] cpu_bus_writemask;`
86
87			`// MAU-RAM bus`
88			`wire [31:0] ram0_bus_addr;`
89			`wire ram0_bus_we;`
90			`wire [31:0] ram0_bus_rddata;`
91			`wire [31:0] ram0_bus_wrdata;`
92
93			`wire [31:0] ram1_bus_addr;`
94			`wire ram1_bus_we;`
95			`wire [31:0] ram1_bus_rddata;`
96			`wire [31:0] ram1_bus_wrdata;`
97
98	5	AlexAntono	`// CPU control`
99	2	AlexAntono	`wire cpu_present;`
100			`wire [63:0] zpu_status;`
101			`wire cpu_break;`
102			`wire [31:0] cpu_pc;`
103
104			`wire cpu_interrupt;`
105			`wire cpu_interrupt_ack;`
106			`wire cpu_reset;`
107			`wire cpu_enb;`
108
109			`generate`
110			`if (CPU_PRESENT == 1)`
111
112			`// Processor core`
113			`zpu_core`
114			`#(`
115			`.stack_address((MEM_SIZE_KB * 1024) - 8)`
116			`)`
117			`zpu_core`
118			`(`
119			`.clk(clk_i),`
120	5	AlexAntono	`.sreset(app_reset \| cpu_reset),`
121	2	AlexAntono	`.enable(cpu_enb),`
122			`.cpu_present(cpu_present),`
123			`.pc_bo(cpu_pc),`
124
125			`.mem_req(cpu_bus_enb),`
126			`.mem_we(cpu_bus_we),`
127			`.mem_ack(cpu_bus_ack),`
128			`.mem_read(cpu_bus_read),`
129			`.mem_write(cpu_bus_write),`
130			`.out_mem_addr(cpu_bus_addr),`
131			`.mem_writeMask(cpu_bus_writemask),`
132
133			`.interrupt(cpu_interrupt),`
134			`.interrupt_ack(cpu_interrupt_ack),`
135			`.break_o(cpu_break),`
136			`.zpu_status(zpu_status)`
137			`);`
138
139			`else`
140
141			`zpu_core_stub zpu_core`
142			`(`
143			`.clk(clk_i),`
144	5	AlexAntono	`.sreset(app_reset \| cpu_reset),`
145	2	AlexAntono	`.enable(cpu_enb),`
146			`.cpu_present(cpu_present),`
147			`.pc_bo(cpu_pc),`
148
149			`.mem_req(cpu_bus_enb),`
150			`.mem_we(cpu_bus_we),`
151			`.mem_ack(cpu_bus_ack),`
152			`.mem_read(cpu_bus_read),`
153			`.mem_write(cpu_bus_write),`
154			`.out_mem_addr(cpu_bus_addr),`
155			`.mem_writeMask(cpu_bus_writemask),`
156
157			`.interrupt(cpu_interrupt),`
158			`.interrupt_ack(cpu_interrupt_ack),`
159			`.break_o(cpu_break),`
160			`.zpu_status(zpu_status)`
161			`);`
162
163			`endgenerate`
164
165
166	5	AlexAntono	`PSS_MotherBlock`
167	2	AlexAntono	`#(`
168	5	AlexAntono	`.A31_DEFAULT(A31_DEFAULT),`
169	2	AlexAntono	`.CPU_RESET_DEFAULT(CPU_RESET_DEFAULT),`
170	7	AlexAntono	`.EXT_RESET_DEFAULT(EXT_RESET_DEFAULT),`
171	2	AlexAntono	`.MEM_SIZE_KB(MEM_SIZE_KB)`
172			`)`
173	5	AlexAntono	`MotherBlock`
174	2	AlexAntono	`(`
175			`.clk_i(clk_i),`
176	5	AlexAntono
177			`.arst_i(arst_i),`
178			`.srst_o(srst_o),`
179			`.srst_i(srst_i),`
180			`.ext_rst_o(ext_rst_o),`
181	2	AlexAntono
182	5	AlexAntono	`.INT_bi(INT_bi),`
183			`.cpu_ireq_o(cpu_interrupt),`
184			`.cpu_iack_i(cpu_interrupt_ack),`
185
186	2	AlexAntono	`//// Masters ////`
187			`// Debug bus //`
188			`.dbg_enb_i(dbg_enb_i),`
189			`.dbg_we_i(dbg_wr_i),`
190			`.dbg_addr_bi(dbg_addr_bi),`
191			`.dbg_wdata_bi(dbg_data_bi),`
192			`.dbg_ack_o(dbg_resp_o),`
193			`.dbg_rdata_bo(dbg_data_bo),`
194
195			`// ZPU bus //`
196			`.cpu_enb_i(cpu_bus_enb),`
197			`.cpu_we_i(cpu_bus_we),`
198			`.cpu_ack_o(cpu_bus_ack),`
199			`.cpu_rdata_bo(cpu_bus_read),`
200			`.cpu_wdata_bi(cpu_bus_write),`
201			`.cpu_addr_bi(cpu_bus_addr),`
202			`.cpu_writemask_bi(cpu_bus_writemask),`
203
204			`//// Slaves ////`
205			`// RAM0 bus //`
206			`.ram0_addr_bo(ram0_bus_addr),`
207			`.ram0_we_o(ram0_bus_we),`
208			`.ram0_wdata_bo(ram0_bus_wrdata),`
209			`.ram0_rdata_bi(ram0_bus_rddata),`
210
211			`// RAM1 bus //`
212			`.ram1_addr_bo(ram1_bus_addr),`
213			`.ram1_we_o(ram1_bus_we),`
214			`.ram1_wdata_bo(ram1_bus_wrdata),`
215			`.ram1_rdata_bi(ram1_bus_rddata),`
216
217			`// Expansion port //`
218			`.xport_req_o(xport_req_o),`
219			`.xport_ack_i(xport_ack_i),`
220			`.xport_err_i(xport_err_i),`
221			`.xport_we_o(xport_we_o),`
222			`.xport_addr_bo(xport_addr_bo),`
223			`.xport_wdata_bo(xport_wdata_bo),`
224			`.xport_resp_i(xport_resp_i),`
225			`.xport_rdata_bi(xport_rdata_bi),`
226
227	5	AlexAntono	`.cpu_present_i(cpu_present),`
228	2	AlexAntono	`.cpu_pc_bi(cpu_pc),`
229			`.cpu_break_i(cpu_break),`
230			`.cpu_reset_o(cpu_reset),`
231	5	AlexAntono	`.cpu_enb_o(cpu_enb)`
232	2	AlexAntono	`);`
233
234			`ram_dual`
235			`#(`
236			`.mem_data(MEM_DATA),`
237			`.dat_width(32),`
238			`.adr_width(32),`
239			`.mem_size((MEM_SIZE_KB * 1024) / 4 )`
240			`)`
241			`ram_dual_port`
242			`(`
243			`.clk(clk_i),`
244
245			`.dat0_i(ram0_bus_wrdata),`
246			`.adr0_i({2'h0, ram0_bus_addr[31:2]}),`
247			`.we0_i(ram0_bus_we),`
248			`.dat0_o(ram0_bus_rddata),`
249
250			`.dat1_i(ram1_bus_wrdata),`
251			`.adr1_i({2'h0, ram1_bus_addr[31:2]}),`
252			`.we1_i(ram1_bus_we),`
253			`.dat1_o(ram1_bus_rddata)`
254			`);`
255
256			`endmodule`

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