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[/] [pss/] [trunk/] [pss/] [tb/] [PSS_SoC_tb.v] - Blame information for rev 10

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/*
 PSS
 
 Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>
 All rights reserved.
 
 Version 0.99
 
 The FreeBSD license
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions
 are met:
 
 1. Redistributions of source code must retain the above copyright
    notice, this list of conditions and the following disclaimer.
 2. Redistributions in binary form must reproduce the above
    copyright notice, this list of conditions and the following
    disclaimer in the documentation and/or other materials
    provided with the distribution.
 
 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
`timescale 1ns / 1ps
 
`define HALF_PERIOD                     10                                              //external 50 MHZ
`define DIVIDER_115200          32'd8680
`define DIVIDER_19200           32'd52083
`define DIVIDER_9600            32'd104166
`define DIVIDER_4800            32'd208333
`define DIVIDER_2400            32'd416666
 
// udm interface
`define SYNC_BYTE                       8'h55
`define ESCAPE_BYTE                     8'h5a
`define IDCODE_CMD                      8'h00   // check udm accessibility
`define RST_CMD                         8'h80   // Reset slave  
`define WR_CMD                          8'h81   // Write slave with autoincrement
`define RD_CMD                          8'h82   // Read slave with autoincrement
`define WR_CMD_NOINC            8'h83   // Write slave without autoincrement
`define RD_CMD_NOINC            8'h84   // Read slave without autoincrement
 
module PSS_SoC_tb ();
//
localparam REG_CPU_CONTROL_ADDR         = 32'h40000000;
localparam REG_CPU_PC_ADDR                      = 32'h40000004;
localparam REG_CPU_A31                          = 32'h40000008;
localparam REG_DBG_A31                          = 32'h4000000C;
 
localparam REG_INTC_CONTROL_ADDR        = 32'h40000010;
localparam REG_INTC_MASK_ADDR           = 32'h40000014;
localparam REG_INTC_REQ_ADDR            = 32'h40000018;
localparam REG_MEM_SIZE_KB                      = 32'h4000001C;
 
localparam REG_DMA_CONTROL_ADDR         = 32'h40000020;
localparam REG_DMA_SOURCEADDR_ADDR      = 32'h40000024;
localparam REG_DMA_DESTADDR_ADDR        = 32'h40000028;
localparam REG_DMA_SIZE_ADDR            = 32'h4000002C;
 
localparam REG_SGI_ADDR                         = 32'h40000030;
 
localparam REG_BUS_ERROR_ADDR_ADDR      = 32'h40000038;
localparam REG_BUS_ERROR_PC_ADDR        = 32'h4000003C;
 
localparam REG_TRAP_CONTROL_ADDR        = 32'h40000040;
localparam REG_TRAP_ADDR_ADDR           = 32'h40000044;
//
reg CLK_50MHZ, RST, rx;
reg [7:0] SW;
wire [7:0] LED;
 
//instantiating PSS
pss_soc_top DUT(
        .clk_i(CLK_50MHZ),
        .rst_i(RST),
        .rx_i(rx),
        .ext_int_i(0),
        .SW(SW),
        .LED(LED));
//////////////////////////
/////////tasks////////////
//////////////////////////
 
reg parity;
integer i, j, k;
 
reg [32:0] rate;
reg [1:0] configuration;
 
 
////wait////
task WAIT
        (
         input reg [15:0] periods
         );
begin
for (i=0; i<periods; i=i+1)
        begin
        #(`HALF_PERIOD*2);
        end
end
endtask
 
 
////reset all////
task RESET_ALL ();
begin
        CLK_50MHZ = 1'b0;
        RST = 1'b1;
        rx = 1'b1;
        #(`HALF_PERIOD/2);
        RST = 1;
        #(`HALF_PERIOD*6);
        RST = 0;
end
endtask
 
 
task UART_CFG
        (
                input reg [32:0] rate_i,
                input reg [1:0] configuration_i
        );
        begin
        rate = rate_i;
        configuration = configuration_i;
        end
endtask
 
////Send byte to UART////
 
task UART_SEND
        (
         input reg [7:0] send_byte
         );
        begin
        parity = 0;
        //start
        rx = 1'b0;
        #rate;
        //sending data
        for (i=0; i<8; i=i+1)
                begin
                rx = send_byte[0];
                #rate;
                parity = parity ^ send_byte[0];
                send_byte = send_byte >> 1;
                end
        //parity
        if (configuration != 2'b00)
                begin
                if (configuration == 2'b10)
                        begin
                        rx = parity;
                        #rate;
                        end
                else if (configuration == 2'b01)
                        begin
                        rx = ~parity;
                        #rate;
                        end
                end
        //stop;
                rx = 1'b1;
                #rate;
        end
endtask
 
 
task pss_hreset ();
        begin
        UART_SEND(`SYNC_BYTE);
        UART_SEND(`RST_CMD);
        end
endtask
 
task pss_sendbyte
        (
                input reg [7:0] databyte
        );
        begin
        if ((databyte == `SYNC_BYTE) || (databyte == `ESCAPE_BYTE))
                UART_SEND(`ESCAPE_BYTE);
        UART_SEND(databyte);
        end
endtask
 
 
task pss_sendword_le
        (
                input reg [31:0] dataword
        );
        begin
        pss_sendbyte(dataword[7:0]);
        pss_sendbyte(dataword[15:8]);
        pss_sendbyte(dataword[23:16]);
        pss_sendbyte(dataword[31:24]);
        end
endtask
 
 
task pss_sendword_be
        (
                input reg [31:0] dataword
        );
        begin
        pss_sendbyte(dataword[31:24]);
        pss_sendbyte(dataword[23:16]);
        pss_sendbyte(dataword[15:8]);
        pss_sendbyte(dataword[7:0]);
        end
endtask
 
 
task pss_wr_single
        (
                input reg [31:0] wr_addr,
                input reg [31:0] wr_data
        );
        begin
 
        // header
        UART_SEND(`SYNC_BYTE);
        UART_SEND(`WR_CMD);
 
        // address
        pss_sendword_le(wr_addr);
 
        // length
        pss_sendword_le(32'h4);
 
        // data
        pss_sendword_le(wr_data);
 
        end
endtask
 
 
task pss_rd_single
        (
                input reg [31:0] wr_addr
        );
        begin
 
        // header
        UART_SEND(`SYNC_BYTE);
        UART_SEND(`RD_CMD);
 
        // address
        pss_sendword_le(wr_addr);
 
        // length
        pss_sendword_le(32'h4);
 
        end
endtask
 
 
task pss_reset ();
        begin
        pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h1);
        end
endtask
 
 
task pss_start ();
        begin
        pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h0);
        end
endtask
 
 
task pss_restart ();
        begin
        pss_reset();
        pss_start();
        end
endtask
 
 
task pss_sgi ();
        begin
        pss_wr_single(REG_SGI_ADDR, 32'h0);
        end
endtask
 
 
task dma_test_wr ();
        begin
        // data
        pss_wr_single(32'h00000008, 32'h123455aa);
        pss_wr_single(32'h0000000C, 32'h07bb07bb);
        pss_wr_single(32'h00000010, 32'h23344556);
        pss_wr_single(32'h00000014, 32'h89abcdef);
 
        // source address
        pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h00000008);
 
        // dest address
        pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h8a000000);
 
        // size
        pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
 
        // command
        pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000006);
        end
endtask
 
 
task dma_test_rd ();
        begin
        // source address
        pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h8C000000);
 
        // dest address
        pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h00000010);
 
        // size
        pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);
 
        // command
        pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000004);
        end
endtask
 
 
//////////////////////////
//initial block
initial
begin
        $display ("### SIMULATION STARTED ###");
 
        SW = 8'h0;
        RESET_ALL();
        UART_CFG(`DIVIDER_115200, 2'b00);
        WAIT(50000);
        UART_SEND(`SYNC_BYTE);
        UART_SEND(`IDCODE_CMD);
        pss_hreset();
 
        //dma_test_rd();
 
        pss_restart();
        //pss_sgi();
        //pss_sgi();
        //pss_sgi();
        pss_wr_single(32'h8a000000, 32'h5aaa5aaa);
        WAIT(50000);
        $display ("### READING MEMORY ###");
        pss_rd_single(32'h00000000);
        pss_rd_single(32'h00000004);
        pss_rd_single(32'h00000008);
        pss_rd_single(32'h0000000C);
        WAIT(777);
        pss_rd_single(32'h00000000);
        pss_rd_single(32'h00000004);
        pss_rd_single(32'h00000008);
        pss_rd_single(32'h0000000C);
 
 
        WAIT(50000);
 
        $display ("### TEST PROCEDURE FINISHED ###");
        $stop;
end
//
always #`HALF_PERIOD CLK_50MHZ = ~CLK_50MHZ;
 
always #50000 SW = SW + 8'h1;
//
endmodule

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[/] [pss/] [trunk/] [pss/] [tb/] [PSS_SoC_tb.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	3	AlexAntono	`/*`
2			`PSS`
3
4			`Copyright (c) 2016 Alexander Antonov <153287@niuitmo.ru>`
5			`All rights reserved.`
6
7	6	AlexAntono	`Version 0.99`
8	3	AlexAntono
9			`The FreeBSD license`
10
11			`Redistribution and use in source and binary forms, with or without`
12			`modification, are permitted provided that the following conditions`
13			`are met:`
14
15			`1. Redistributions of source code must retain the above copyright`
16			`notice, this list of conditions and the following disclaimer.`
17			`2. Redistributions in binary form must reproduce the above`
18			`copyright notice, this list of conditions and the following`
19			`disclaimer in the documentation and/or other materials`
20			`provided with the distribution.`
21
22			THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
23			`EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
24			`THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A`
25			`PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE`
26			`PSS PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,`
27			`INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
28			`(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
29			`OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
30			`HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
31			`STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)`
32			`ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
33			`ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`*/`
35
36
37			`timescale 1ns / 1ps
38
39			`define HALF_PERIOD 10 //external 50 MHZ
40			`define DIVIDER_115200 32'd8680
41			`define DIVIDER_19200 32'd52083
42			`define DIVIDER_9600 32'd104166
43			`define DIVIDER_4800 32'd208333
44			`define DIVIDER_2400 32'd416666
45
46			`// udm interface`
47			`define SYNC_BYTE 8'h55
48			`define ESCAPE_BYTE 8'h5a
49			`define IDCODE_CMD 8'h00 // check udm accessibility
50			`define RST_CMD 8'h80 // Reset slave
51			`define WR_CMD 8'h81 // Write slave with autoincrement
52			`define RD_CMD 8'h82 // Read slave with autoincrement
53			`define WR_CMD_NOINC 8'h83 // Write slave without autoincrement
54			`define RD_CMD_NOINC 8'h84 // Read slave without autoincrement
55
56			`module PSS_SoC_tb ();`
57			`//`
58			`localparam REG_CPU_CONTROL_ADDR = 32'h40000000;`
59			`localparam REG_CPU_PC_ADDR = 32'h40000004;`
60			`localparam REG_CPU_A31 = 32'h40000008;`
61			`localparam REG_DBG_A31 = 32'h4000000C;`
62
63			`localparam REG_INTC_CONTROL_ADDR = 32'h40000010;`
64			`localparam REG_INTC_MASK_ADDR = 32'h40000014;`
65			`localparam REG_INTC_REQ_ADDR = 32'h40000018;`
66			`localparam REG_MEM_SIZE_KB = 32'h4000001C;`
67
68			`localparam REG_DMA_CONTROL_ADDR = 32'h40000020;`
69			`localparam REG_DMA_SOURCEADDR_ADDR = 32'h40000024;`
70			`localparam REG_DMA_DESTADDR_ADDR = 32'h40000028;`
71			`localparam REG_DMA_SIZE_ADDR = 32'h4000002C;`
72
73			`localparam REG_SGI_ADDR = 32'h40000030;`
74
75			`localparam REG_BUS_ERROR_ADDR_ADDR = 32'h40000038;`
76			`localparam REG_BUS_ERROR_PC_ADDR = 32'h4000003C;`
77
78			`localparam REG_TRAP_CONTROL_ADDR = 32'h40000040;`
79			`localparam REG_TRAP_ADDR_ADDR = 32'h40000044;`
80			`//`
81			`reg CLK_50MHZ, RST, rx;`
82			`reg [7:0] SW;`
83			`wire [7:0] LED;`
84
85			`//instantiating PSS`
86			`pss_soc_top DUT(`
87			`.clk_i(CLK_50MHZ),`
88			`.rst_i(RST),`
89			`.rx_i(rx),`
90			`.ext_int_i(0),`
91			`.SW(SW),`
92			`.LED(LED));`
93			`//////////////////////////`
94			`/////////tasks////////////`
95			`//////////////////////////`
96
97			`reg parity;`
98			`integer i, j, k;`
99
100			`reg [32:0] rate;`
101			`reg [1:0] configuration;`
102
103
104			`////wait////`
105			`task WAIT`
106			`(`
107			`input reg [15:0] periods`
108			`);`
109			`begin`
110			`for (i=0; i<periods; i=i+1)`
111			`begin`
112			#(`HALF_PERIOD*2);
113			`end`
114			`end`
115			`endtask`
116
117
118			`////reset all////`
119			`task RESET_ALL ();`
120			`begin`
121			`CLK_50MHZ = 1'b0;`
122			`RST = 1'b1;`
123			`rx = 1'b1;`
124			#(`HALF_PERIOD/2);
125			`RST = 1;`
126			#(`HALF_PERIOD*6);
127			`RST = 0;`
128			`end`
129			`endtask`
130
131
132			`task UART_CFG`
133			`(`
134			`input reg [32:0] rate_i,`
135			`input reg [1:0] configuration_i`
136			`);`
137			`begin`
138			`rate = rate_i;`
139			`configuration = configuration_i;`
140			`end`
141			`endtask`
142
143			`////Send byte to UART////`
144
145			`task UART_SEND`
146			`(`
147			`input reg [7:0] send_byte`
148			`);`
149			`begin`
150			`parity = 0;`
151			`//start`
152			`rx = 1'b0;`
153			`#rate;`
154			`//sending data`
155			`for (i=0; i<8; i=i+1)`
156			`begin`
157			`rx = send_byte[0];`
158			`#rate;`
159			`parity = parity ^ send_byte[0];`
160			`send_byte = send_byte >> 1;`
161			`end`
162			`//parity`
163			`if (configuration != 2'b00)`
164			`begin`
165			`if (configuration == 2'b10)`
166			`begin`
167			`rx = parity;`
168			`#rate;`
169			`end`
170			`else if (configuration == 2'b01)`
171			`begin`
172			`rx = ~parity;`
173			`#rate;`
174			`end`
175			`end`
176			`//stop;`
177			`rx = 1'b1;`
178			`#rate;`
179			`end`
180			`endtask`
181
182
183			`task pss_hreset ();`
184			`begin`
185			UART_SEND(`SYNC_BYTE);
186			UART_SEND(`RST_CMD);
187			`end`
188			`endtask`
189
190			`task pss_sendbyte`
191			`(`
192			`input reg [7:0] databyte`
193			`);`
194			`begin`
195			if ((databyte == `SYNC_BYTE) \|\| (databyte == `ESCAPE_BYTE))
196			UART_SEND(`ESCAPE_BYTE);
197	10	AlexAntono	`UART_SEND(databyte);`
198	3	AlexAntono	`end`
199			`endtask`
200
201
202			`task pss_sendword_le`
203			`(`
204			`input reg [31:0] dataword`
205			`);`
206			`begin`
207			`pss_sendbyte(dataword[7:0]);`
208			`pss_sendbyte(dataword[15:8]);`
209			`pss_sendbyte(dataword[23:16]);`
210			`pss_sendbyte(dataword[31:24]);`
211			`end`
212			`endtask`
213
214
215			`task pss_sendword_be`
216			`(`
217			`input reg [31:0] dataword`
218			`);`
219			`begin`
220			`pss_sendbyte(dataword[31:24]);`
221			`pss_sendbyte(dataword[23:16]);`
222			`pss_sendbyte(dataword[15:8]);`
223			`pss_sendbyte(dataword[7:0]);`
224			`end`
225			`endtask`
226
227
228			`task pss_wr_single`
229			`(`
230			`input reg [31:0] wr_addr,`
231			`input reg [31:0] wr_data`
232			`);`
233			`begin`
234
235			`// header`
236			UART_SEND(`SYNC_BYTE);
237			UART_SEND(`WR_CMD);
238
239			`// address`
240			`pss_sendword_le(wr_addr);`
241
242			`// length`
243			`pss_sendword_le(32'h4);`
244
245			`// data`
246			`pss_sendword_le(wr_data);`
247
248			`end`
249			`endtask`
250
251
252			`task pss_rd_single`
253			`(`
254			`input reg [31:0] wr_addr`
255			`);`
256			`begin`
257
258			`// header`
259			UART_SEND(`SYNC_BYTE);
260			UART_SEND(`RD_CMD);
261
262			`// address`
263			`pss_sendword_le(wr_addr);`
264
265			`// length`
266			`pss_sendword_le(32'h4);`
267
268			`end`
269			`endtask`
270
271
272			`task pss_reset ();`
273			`begin`
274			`pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h1);`
275			`end`
276			`endtask`
277
278
279			`task pss_start ();`
280			`begin`
281			`pss_wr_single(REG_CPU_CONTROL_ADDR, 32'h0);`
282			`end`
283			`endtask`
284
285
286			`task pss_restart ();`
287			`begin`
288			`pss_reset();`
289			`pss_start();`
290			`end`
291			`endtask`
292
293
294			`task pss_sgi ();`
295			`begin`
296			`pss_wr_single(REG_SGI_ADDR, 32'h0);`
297			`end`
298			`endtask`
299
300
301			`task dma_test_wr ();`
302			`begin`
303			`// data`
304			`pss_wr_single(32'h00000008, 32'h123455aa);`
305			`pss_wr_single(32'h0000000C, 32'h07bb07bb);`
306			`pss_wr_single(32'h00000010, 32'h23344556);`
307			`pss_wr_single(32'h00000014, 32'h89abcdef);`
308
309			`// source address`
310			`pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h00000008);`
311
312			`// dest address`
313			`pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h8a000000);`
314
315			`// size`
316			`pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);`
317
318			`// command`
319			`pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000006);`
320			`end`
321			`endtask`
322
323
324			`task dma_test_rd ();`
325			`begin`
326			`// source address`
327			`pss_wr_single(REG_DMA_SOURCEADDR_ADDR, 32'h8C000000);`
328
329			`// dest address`
330			`pss_wr_single(REG_DMA_DESTADDR_ADDR, 32'h00000010);`
331
332			`// size`
333			`pss_wr_single(REG_DMA_SIZE_ADDR, 32'd16);`
334
335			`// command`
336			`pss_wr_single(REG_DMA_CONTROL_ADDR, 32'h00000004);`
337			`end`
338			`endtask`
339
340
341			`//////////////////////////`
342			`//initial block`
343			`initial`
344			`begin`
345			`$display ("### SIMULATION STARTED ###");`
346
347			`SW = 8'h0;`
348			`RESET_ALL();`
349			UART_CFG(`DIVIDER_115200, 2'b00);
350			`WAIT(50000);`
351			UART_SEND(`SYNC_BYTE);
352			UART_SEND(`IDCODE_CMD);
353			`pss_hreset();`
354
355	6	AlexAntono	`//dma_test_rd();`
356
357	3	AlexAntono	`pss_restart();`
358	6	AlexAntono	`//pss_sgi();`
359			`//pss_sgi();`
360			`//pss_sgi();`
361	3	AlexAntono	`pss_wr_single(32'h8a000000, 32'h5aaa5aaa);`
362			`WAIT(50000);`
363			`$display ("### READING MEMORY ###");`
364			`pss_rd_single(32'h00000000);`
365			`pss_rd_single(32'h00000004);`
366			`pss_rd_single(32'h00000008);`
367			`pss_rd_single(32'h0000000C);`
368			`WAIT(777);`
369			`pss_rd_single(32'h00000000);`
370			`pss_rd_single(32'h00000004);`
371			`pss_rd_single(32'h00000008);`
372			`pss_rd_single(32'h0000000C);`
373
374	6	AlexAntono
375	3	AlexAntono	`WAIT(50000);`
376
377			`$display ("### TEST PROCEDURE FINISHED ###");`
378			`$stop;`
379			`end`
380			`//`
381			always #`HALF_PERIOD CLK_50MHZ = ~CLK_50MHZ;
382
383			`always #50000 SW = SW + 8'h1;`
384			`//`
385			`endmodule`