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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE PWM/Timer/Counter Definitions                      ////
////                                                              ////
////  This file is part of the PTC project                        ////
////  http://www.opencores.org/cores/ptc/                         ////
////                                                              ////
////  Description                                                 ////
////  PTC definitions.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/21 23:23:50  lampret
// Changed directory structure, defines and port names.
//
// Revision 1.2  2001/07/17 00:18:08  lampret
// Added new parameters however RTL still has some issues related to hrc_match and int_match
//
// Revision 1.1  2001/06/05 07:45:36  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
//
// Width of the PTC counter
//
//
`define PTC_CW  32
 
//
// Undefine this one if you don't want to remove PTC block from your design
// but you also don't need it. When it is undefined, all PTC ports still
// remain valid and the core can be synthesized however internally there is
// no PTC funationality.
//
// Defined by default (duhh !).
//
`define PTC_IMPLEMENTED
 
//
// Undefine if you don't need to read PTC registers.
// When it is undefined all reads of PTC registers return zero. This
// is usually useful if you want really small area (for example when
// implemented in FPGA).
//
// To follow PTC IP core specification document this one must be defined.
// Also to successfully run the test bench it must be defined. By default
// it is defined.
//
`define PTC_READREGS
 
//
// Full WISHBONE address decoding
//
// It is is undefined, partial WISHBONE address decoding is performed.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define PTC_FULL_DECODE
 
//
// Strict 32-bit WISHBONE access
//
// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define PTC_STRICT_32BIT_ACCESS
 
//
// WISHBONE address bits used for full decoding of PTC registers.
//
`define PTC_ADDRHH 15
`define PTC_ADDRHL 5
`define PTC_ADDRLH 1
`define PTC_ADDRLL 0
 
//
// Bits of WISHBONE address used for partial decoding of PTC registers.
//
// Default 4:2.
//
`define PTC_OFS_BITS    `PTC_ADDRHL-1:`PTC_ADDRLH+1
 
//
// Addresses of PTC registers
//
// To comply with PTC IP core specification document they must go from
// address 0 to address 0xC in the following order: RPTC_CNTR, RPTC_HRC,
// RPTC_LRC and RPTC_CTRL
//
// If particular alarm/ctrl register is not needed, it's address definition
// can be omitted and the register will not be implemented. Instead a fixed
// default value will
// be used.
//
`define PTC_RPTC_CNTR   2'h0    // Address 0x0
`define PTC_RPTC_HRC    2'h1    // Address 0x4
`define PTC_RPTC_LRC    2'h2    // Address 0x8
`define PTC_RPTC_CTRL   2'h3    // Address 0xc
 
//
// Default values for unimplemented PTC registers
//
`define PTC_DEF_RPTC_CNTR       `PTC_CW'b0
`define PTC_DEF_RPTC_HRC        `PTC_CW'b0
`define PTC_DEF_RPTC_LRC        `PTC_CW'b0
`define PTC_DEF_RPTC_CTRL       9'h01           // RPTC_CTRL[EN] = 1
 
//
// RPTC_CTRL bits
//
// To comply with the PTC IP core specification document they must go from
// bit 0 to bit 8 in the following order: EN, ECLK, NEC, OE, SINGLE, INTE,
// INT, CNTRRST, CAPTE
//
`define PTC_RPTC_CTRL_EN                0
`define PTC_RPTC_CTRL_ECLK              1
`define PTC_RPTC_CTRL_NEC               2
`define PTC_RPTC_CTRL_OE                3
`define PTC_RPTC_CTRL_SINGLE            4
`define PTC_RPTC_CTRL_INTE              5
`define PTC_RPTC_CTRL_INT               6
`define PTC_RPTC_CTRL_CNTRRST           7
`define PTC_RPTC_CTRL_CAPTE             8
 

Line No.	Rev	Author	Line
1	10	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE PWM/Timer/Counter Definitions ////`
4			`//// ////`
5			`//// This file is part of the PTC project ////`
6			`//// http://www.opencores.org/cores/ptc/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PTC definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.2 2001/08/21 23:23:50 lampret`
48			`// Changed directory structure, defines and port names.`
49			`//`
50			`// Revision 1.2 2001/07/17 00:18:08 lampret`
51			`// Added new parameters however RTL still has some issues related to hrc_match and int_match`
52			`//`
53			`// Revision 1.1 2001/06/05 07:45:36 lampret`
54			`// Added initial RTL and test benches. There are still some issues with these files.`
55			`//`
56			`//`
57
58			`//`
59			`// Width of the PTC counter`
60			`//`
61			`//`
62			`define PTC_CW 32
63
64			`//`
65			`// Undefine this one if you don't want to remove PTC block from your design`
66			`// but you also don't need it. When it is undefined, all PTC ports still`
67			`// remain valid and the core can be synthesized however internally there is`
68			`// no PTC funationality.`
69			`//`
70			`// Defined by default (duhh !).`
71			`//`
72			`define PTC_IMPLEMENTED
73
74			`//`
75			`// Undefine if you don't need to read PTC registers.`
76			`// When it is undefined all reads of PTC registers return zero. This`
77			`// is usually useful if you want really small area (for example when`
78			`// implemented in FPGA).`
79			`//`
80			`// To follow PTC IP core specification document this one must be defined.`
81			`// Also to successfully run the test bench it must be defined. By default`
82			`// it is defined.`
83			`//`
84			`define PTC_READREGS
85
86			`//`
87			`// Full WISHBONE address decoding`
88			`//`
89			`// It is is undefined, partial WISHBONE address decoding is performed.`
90			`// Undefine it if you need to save some area.`
91			`//`
92			`// By default it is defined.`
93			`//`
94			`define PTC_FULL_DECODE
95
96			`//`
97			`// Strict 32-bit WISHBONE access`
98			`//`
99			`// If this one is defined, all WISHBONE accesses must be 32-bit. If it is`
100			`// not defined, err_o is asserted whenever 8- or 16-bit access is made.`
101			`// Undefine it if you need to save some area.`
102			`//`
103			`// By default it is defined.`
104			`//`
105			`define PTC_STRICT_32BIT_ACCESS
106
107			`//`
108			`// WISHBONE address bits used for full decoding of PTC registers.`
109			`//`
110			`define PTC_ADDRHH 15
111			`define PTC_ADDRHL 5
112			`define PTC_ADDRLH 1
113			`define PTC_ADDRLL 0
114
115			`//`
116			`// Bits of WISHBONE address used for partial decoding of PTC registers.`
117			`//`
118			`// Default 4:2.`
119			`//`
120			`define PTC_OFS_BITS `PTC_ADDRHL-1:`PTC_ADDRLH+1
121
122			`//`
123			`// Addresses of PTC registers`
124			`//`
125			`// To comply with PTC IP core specification document they must go from`
126			`// address 0 to address 0xC in the following order: RPTC_CNTR, RPTC_HRC,`
127			`// RPTC_LRC and RPTC_CTRL`
128			`//`
129			`// If particular alarm/ctrl register is not needed, it's address definition`
130			`// can be omitted and the register will not be implemented. Instead a fixed`
131			`// default value will`
132			`// be used.`
133			`//`
134			`define PTC_RPTC_CNTR 2'h0 // Address 0x0
135			`define PTC_RPTC_HRC 2'h1 // Address 0x4
136			`define PTC_RPTC_LRC 2'h2 // Address 0x8
137			`define PTC_RPTC_CTRL 2'h3 // Address 0xc
138
139			`//`
140			`// Default values for unimplemented PTC registers`
141			`//`
142			`define PTC_DEF_RPTC_CNTR `PTC_CW'b0
143			`define PTC_DEF_RPTC_HRC `PTC_CW'b0
144			`define PTC_DEF_RPTC_LRC `PTC_CW'b0
145			`define PTC_DEF_RPTC_CTRL 9'h01 // RPTC_CTRL[EN] = 1
146
147			`//`
148			`// RPTC_CTRL bits`
149			`//`
150			`// To comply with the PTC IP core specification document they must go from`
151			`// bit 0 to bit 8 in the following order: EN, ECLK, NEC, OE, SINGLE, INTE,`
152			`// INT, CNTRRST, CAPTE`
153			`//`
154			`define PTC_RPTC_CTRL_EN 0
155			`define PTC_RPTC_CTRL_ECLK 1
156			`define PTC_RPTC_CTRL_NEC 2
157			`define PTC_RPTC_CTRL_OE 3
158			`define PTC_RPTC_CTRL_SINGLE 4
159			`define PTC_RPTC_CTRL_INTE 5
160			`define PTC_RPTC_CTRL_INT 6
161			`define PTC_RPTC_CTRL_CNTRRST 7
162			`define PTC_RPTC_CTRL_CAPTE 8
163

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[/] [ptc/] [trunk/] [rtl/] [verilog/] [ptc_defines.v] - Blame information for rev 13