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-----------------------------------------------------------------------------------------------
--
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
--              p.j.j.lemmens@rug.nl
--    http://www-panda.gsi.de
--
--    As a reference, please use:
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
--    Nuclear Inst. and Methods in Physics Research, A ....
--
--
--    This program is free software; you can redistribute it and/or modify
--    it under the terms of the GNU Lesser General Public License as published by
--    the Free Software Foundation; either version 3 of the License, or
--    (at your option) any later version.
--
--    This program is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU Lesser General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with this program; if not, write to the Free Software
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
--
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Company:                     KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    
-- Author:                      P.J.J. Lemmens
-- Design Name: Feature Extraction
-- Module Name: CF_process.vhd
-- Description: - baseline sampling, calculation & correction
--                                              - Constant Fraction pulse construction
--                                              - Zero-crossing detection
--                                              - event-detection
--                                              - baseline_sampling & event_detection gating/inhibition
--                                              - sub_sample timing calculation through interpolation
--                                              - time-stamp generation
--                                              - energy reading/peak-detection
--
-----------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.numeric_std.ALL;
 
entity CF_process is
        generic(        WIDTH                                                   :       natural := 1;
                                MAX_CF_PWR                                      :       natural :=      1;--                            CF_DELAY                                                :       natural := 1;--                         CF_PWR                                          :       natural :=      1;
                                MAX_BASELINE_PWR                        :       natural :=      1;
                                ZEROX_WINDOW_PWR                        :       natural :=      1;
                                ZEROX_THRESHOLD_PWR             :       natural :=      1;--                            INTEGRAL_PWR                            :       natural :=      1;--                            INTEGRAL_THRESHOLD_PWR  :       natural := 1;
                                INTERP_CYCLES                           :       natural :=      1
                        );
        Port (  rst                                                     : in STD_LOGIC;
                                clk                                                     : in STD_LOGIC;
                                enable                                          : in STD_LOGIC;
                                program                                         : in STD_LOGIC;
                                baseline_enable                 : in STD_LOGIC;
                                double_CF_in                            : in STD_LOGIC;
                                data_in                                         : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
                                threshold_in                            : in STD_LOGIC_VECTOR;
                                cf_pwr_in                                       : in STD_LOGIC_VECTOR;
                                cf_integral_pwr_in              : in STD_LOGIC_VECTOR;
                                baseline_pwr_in                 : in    STD_LOGIC_VECTOR;
                                baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
                                event_inhibit_cnt_in            : in STD_LOGIC_VECTOR;
                                baseline_out                            : out STD_LOGIC_VECTOR;
                                clamped_out                                     : out STD_LOGIC_VECTOR;
                                del_clamp_out                           : out STD_LOGIC_VECTOR;
                                CFdev_clamp_out                 : out STD_LOGIC_VECTOR;
                                cf_trace_out                            : out STD_LOGIC_VECTOR;
                                integral                                                : out STD_LOGIC_VECTOR;
                                sample_nr                                       : out STD_LOGIC_VECTOR;
                                zeroX_out                                       : out STD_LOGIC;
                                event_detect_out                        : out STD_LOGIC;
                                bl_gate_out                                     : out STD_LOGIC;
                                ed_gate_out                                     : out STD_LOGIC;
                                eventdata_valid                 : out STD_LOGIC;
                                eventnr_out                                     : out STD_LOGIC_VECTOR;
                                fraction                                                : out STD_LOGIC_VECTOR;
                                energy                                          : out STD_LOGIC_VECTOR
                        );
end CF_process;
 
architecture Behavioral of CF_process is
 
        constant        MAX_CF_DELAY            : natural := 2**MAX_CF_PWR;
        constant        PEAK_DET_BUF_PWR        : natural := 4;
        constant        PEAK_DET_BUFSIZE        : natural := 2**PEAK_DET_BUF_PWR;
--      constant        CFWINDOW_SIZE           : natural := 2**CF_WINDOW_PWR;
--      constant        INTEGRAL_SIZE           : natural := 2**INTEGRAL_PWR;
        constant FRACTION_SIZE          : natural := INTERP_CYCLES;     --      - ZEROX_WINDOW_PWR; --all  interp bits are fraction now !! interp between 2 samples
--      constant GATE_PWR                               : natural := BASELINE_PWR;
 
        component baseline_follower
        generic(        WINDOW_PWR                      :       natural := 1;           -- defines the maximum window in which event disturbance is seen
                                MAX_BASELINE_PWR        :       natural := 1            -- size of the baseline window
                                );
        Port (  rst                                     : in    STD_LOGIC;
                                clk                                     : in    STD_LOGIC;
                                enable                          : in    STD_LOGIC;
                                program                         : in    STD_LOGIC;
                                gate                                    : in    STD_LOGIC;
                                baseline_pwr_in : in    STD_LOGIC_VECTOR(7 downto 0);
                                buffer_size_in          : in    STD_LOGIC_VECTOR(7 downto 0);
                                data_in                         : in    STD_LOGIC_VECTOR;
                                data_out                                : out   STD_LOGIC_VECTOR;
                                buffer_data_valid       : out STD_LOGIC
                        );
        end component;
 
        component SISO_sub_a
                generic(        A_MINUS_B       :       boolean);
                port (
                        dataa           : IN STD_LOGIC_VECTOR;
                        datab           : IN STD_LOGIC_VECTOR;
                        result  : OUT STD_LOGIC_VECTOR
                );
        end component;
 
        component progdelay_pipeline
                generic (RAM_SIZE_PWR   : natural       := 1;
                                        FLEX_RAM_STYLE  : string                := "distributed");
                Port (clk                       : in  STD_LOGIC;
                                rst                     : in  STD_LOGIC;
                                enable          : in  STD_LOGIC;
                                program         : in  STD_LOGIC;
                                delay_in                : in    STD_LOGIC_VECTOR(7 downto 0);
                                data_in         : in    STD_LOGIC_VECTOR;
                                data_out                : out   STD_LOGIC_VECTOR;
                                data_valid      : out   std_logic
                        );
        end component;
 
        component CF_zeroX
                generic(        BASE_WINDOW_PWR         :       natural;
                                        ZEROX_WINDOW_PWR                :       natural;
                                        ZEROX_THRESHOLD_PWR     :       natural
                                        );
                port (  rst                     : in  STD_LOGIC;
                                        clk                     : in  STD_LOGIC;
                                        enable          : in    STD_LOGIC;
                                        data_in         : in  STD_LOGIC_VECTOR;
                                        zeroX_out       : out   STD_LOGIC
                                );
        end component;
 
        component moving_average_programmable
                generic(MEM_PWR         : natural);
                port (rst                               : in    std_logic;
                                clk                             : in    std_logic;
                                enable                  : in  std_logic;
                                program                 : in  std_logic;
                                avg_pwr_in              : in  std_logic_vector(7 downto 0);
                                data_in                 : in  std_logic_vector;
                                data_out                        : out std_logic_vector
                        );
        end component;
 
        component gate_generator
--              generic(        BASE_WINDOW_PWR :       natural :=      1;
--                                      EVENT_INHIB_PWR :       natural         := 1
--                              );
                Port (  rst                                                     : in  STD_LOGIC;
                                        clk                                                     : in  STD_LOGIC;
                                        enable                                          : in  STD_LOGIC;
                                        program                                         : in  STD_LOGIC;
                                        baseline_enable                 : in  STD_LOGIC;
                                        event_in                                                : in    STD_LOGIC;
                                        baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
                                        event_inhibit_cnt_in            : in STD_LOGIC_VECTOR;
                                        bl_gate_out                                     : out   STD_LOGIC;                      -- baseline gate-signal
                                        ed_gate_out                                     : out   STD_LOGIC                       -- baseline gating inhibited because of event
                                );
        end component;
 
        component timing_linear_interp
                generic(        INTERP_CYCLES           :       natural);
                Port (  rst                                     :       in              STD_LOGIC;
                                        clk                                     :       in              STD_LOGIC;
                                        enable                          :       in              STD_LOGIC;
                                        trigger                         :       in              STD_LOGIC;
                                        data_in                         :       in              STD_LOGIC_VECTOR;
                                        samplenr_in                     :       in              STD_LOGIC_VECTOR;
                                        eventnr_out                     :       out     STD_LOGIC_VECTOR;
                                        fraction_out            :       out     STD_LOGIC_VECTOR;
                                        eventdata_valid :       out     STD_LOGIC
                                );
        end component;
 
        component sample_counter
                Port (rst                               : in    STD_LOGIC;
                                clk                             : in    STD_LOGIC;
                                enable                  : in    STD_LOGIC := '1';
                                sample_nr_out   : out STD_LOGIC_VECTOR (63 downto 0)
                                );
        end component;
 
        component history_max
                generic(        MEM_PWR         :       natural :=      1;
                                        DEPTH                   :       natural := 1
                                        );
                Port (  rst                     : in  STD_LOGIC;
                                        clk                     : in  STD_LOGIC;
                                        enable          : in  STD_LOGIC := '1';
                                        trigger         : in    STD_LOGIC;
                                        data_in         : in  STD_LOGIC_VECTOR;
                                        max_valid       : out   STD_LOGIC;
                                        max_out         : out   STD_LOGIC_VECTOR
                                );
        end component;
 
        component event_detector
                Port (  clk                                     : in STD_LOGIC;
                                        enable                          : in STD_LOGIC := '1';
                                        gate_in                         : in STD_LOGIC;
                                        zeroX_in                                : in STD_LOGIC;
                                        threshold_in            : in STD_LOGIC_VECTOR;
                                        integral_in                     : in STD_LOGIC_VECTOR;
                                        event_detect_out        : out STD_LOGIC
                                );
        end component;
 
-----------------------------------------------------------------------
 
   signal rst_S                                                 : std_logic := '1';
        signal clk_S                                                    : std_logic := '0';
        signal enable_S                                         : std_logic := '0';
        signal program_S                                                : std_logic := '0';
        signal baseline_enable_S                        : STD_LOGIC     := '0';
        signal double_CF_S                                      : STD_LOGIC     := '0';
        signal data_in_S                                                : std_logic_vector (WIDTH - 1 downto 0)  := (others      => '0');
        signal baseline_S                                               : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal clamped_S                                                : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal CFdev_clamp_S                                    : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal del_clamp_S                                      : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal cf_trace_S                                               : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal threshold_S                                      : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal integral_S                                               : STD_LOGIC_VECTOR (WIDTH - 1 downto 0)  := (others      => '0');
        signal cf_pwr_S                                         : STD_LOGIC_VECTOR (7 downto 0)                          := conv_std_logic_vector(4,     8);     -- original default value
        signal cf_integral_pwr_S                        : STD_LOGIC_VECTOR (7 downto 0)                          := conv_std_logic_vector(4,     8);     -- original default value = (mwd_power - 1)
        signal cf_delay_S                                               : STD_LOGIC_VECTOR (7 downto 0)                          := conv_std_logic_vector(16,    8);
        signal baseline_pwr_S                           : STD_LOGIC_VECTOR (7 downto 0)                   := (others     => '0');
        signal baseline_delay_S                         : STD_LOGIC_VECTOR (7 downto 0)                   := (others     => '0');
        signal baseline_inhibit_cnt_S           : STD_LOGIC_VECTOR (7 downto 0)                          := conv_std_logic_vector(32,    8);     -- original default value
        signal event_inhibit_cnt_S                      : STD_LOGIC_VECTOR (7 downto 0)                          := conv_std_logic_vector(16,    8);     -- original default value
        signal event_detect_S                           : std_logic     := '0';
        signal zeroX_S                                                  : STD_LOGIC     := '0';
        signal bl_gate_S                                                : STD_LOGIC     := '0';
        signal ed_gate_S                                                : STD_LOGIC     := '0';
        signal sample_nr_S                                      : STD_LOGIC_VECTOR (63 downto 0) := (others      => '0');
        signal eventnr_S                                                : STD_LOGIC_VECTOR (63 downto 0) := (others      => '0');
        signal time_fraction_S                          : STD_LOGIC_VECTOR (FRACTION_SIZE - 1 downto 0) := (others       => '0');
        signal energy_S                                         : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others       => '0');
        signal eventdata_valid_S                        : STD_LOGIC     := '0';
        signal max_valid_S                                      : STD_LOGIC     := '0';
 
-----------------------------------------------------------------------
 
begin
 
        baseline : baseline_follower
                generic map(WINDOW_PWR                  =>      MAX_CF_PWR,
                                                MAX_BASELINE_PWR        =>      MAX_BASELINE_PWR
                                                )
                port map        (       rst                                     => rst_S,
                                                clk                                     =>      clk_S,
                                                enable                          =>      enable_S,
                                                program                         =>      program_S,
                                                gate                                    =>      bl_gate_S,
                                                baseline_pwr_in =>      baseline_pwr_S,
                                                buffer_size_in          =>      baseline_delay_S,
                                                data_in                         =>      data_in_S,
                                                data_out                                =>      baseline_S,
                                                buffer_data_valid       => open
                                        );
 
                remove_baseline : SISO_sub_a
                        GENERIC MAP(--WIDTH             => data_in_S'length,
                                                        A_MINUS_B       =>      true)
                        PORT MAP (      dataa    => data_in_S,
                                                        datab    => baseline_S,
                                                        result => clamped_S
                                                );
 
                clamped_pipe : progdelay_pipeline
                        generic map(RAM_SIZE_PWR        =>      MAX_CF_PWR,
                                                        FLEX_RAM_STYLE  => "distributed")
                        PORT MAP(rst                                    => rst_S,
                                                clk                                     => clk_S,
                                                enable                          => enable_S,
                                                program                         => program_S,
                                                delay_in                                => cf_delay_S,
                                                data_in                         => clamped_S,
                                                data_out                        => del_clamp_S,
                                                data_valid                      => open
                                        );
 
                CF_sub : SISO_sub_a
                        GENERIC MAP(--WIDTH             => cf_trace_S'length,
                                                        A_MINUS_B       =>      true)
                        PORT MAP (      dataa    => del_clamp_S,
                                                        datab    => CFdev_clamp_S,
                                                        result => cf_trace_S
                                                );
 
                zeroX : CF_zeroX
                        generic map(BASE_WINDOW_PWR             =>      MAX_CF_PWR,             --      CF_WINDOW_PWR,
                                                        ZEROX_WINDOW_PWR                =>      ZEROX_WINDOW_PWR,
                                                        ZEROX_THRESHOLD_PWR     =>      ZEROX_THRESHOLD_PWR
                                                        )
                        port map        (       rst                     => rst_S,
                                                        clk                     =>      clk_S,
                                                        enable          => enable_S,
                                                        data_in         =>      cf_trace_S,
                                                        zeroX_out       =>      zeroX_S
                                                );
 
                CF_integral : moving_average_programmable
                        generic map(MEM_PWR     =>      MAX_CF_PWR)
                        port map(       rst                     => rst_S,
                                                        clk                     =>      clk_S,
                                                        enable          =>      enable_S,
                                                        program         => program_S,
                                                        avg_pwr_in      => cf_integral_pwr_S,
                                                        data_in         =>      clamped_S,
                                                        data_out                => integral_S
                                                );
 
                gator : gate_generator
--                      generic map(BASE_WINDOW_PWR                     =>      GATE_PWR,
--                                                      EVENT_INHIB_PWR                 =>      MAX_CF_PWR              --CF_WINDOW_PWR
--                                                      )
                        port map        (       rst                                                     =>      rst_S,
                                                        clk                                                     =>      clk_S,
                                                        enable                                          => enable_S,
                                                        program                                         => program_S,
                                                        baseline_enable                 => baseline_enable_S,
                                                        event_in                                                =>      event_detect_S,
                                                        baseline_inhibit_cnt_in =>      baseline_inhibit_cnt_S,
                                                        event_inhibit_cnt_in            => event_inhibit_cnt_S,
                                                        bl_gate_out                                     => bl_gate_S,
                                                        ed_gate_out                                     => ed_gate_S
                                                );
 
                timing : timing_linear_interp
                        generic map(INTERP_CYCLES               =>      INTERP_CYCLES)
                        Port map(       rst                                     => rst_S,
                                                        clk                                     =>      clk_S,
                                                        enable                          => enable_S,
                                                        trigger                         =>      event_detect_S,
                                                        data_in                         =>      cf_trace_S,
                                                        samplenr_in                     =>      sample_nr_S,
                                                        eventnr_out                     => eventnr_S,
                                                        fraction_out            =>      time_fraction_S,
                                                        eventdata_valid => eventdata_valid_S
                                                );
 
                time_stamp : sample_counter
                        Port map(       rst                             => rst_S,
                                                        clk                             =>      clk_S,
                                                        enable                  => enable_S,
                                                        sample_nr_out   => sample_nr_S
                                                );
 
                peak_detect     : history_max
                        generic map(MEM_PWR                             =>      PEAK_DET_BUF_PWR,                               --CF_WINDOW_PWR,
                                                        DEPTH                                   =>      PEAK_DET_BUFSIZE)                               --CF_WINDOWSIZE -10
                        port map        (       rst                                     => rst_S,
                                                        clk                                     =>      clk_S,
                                                        enable                          => enable_S,
                                                        trigger                         =>      event_detect_S,
                                                        data_in                         =>      clamped_S,
                                                        max_valid                       =>      max_valid_S,
                                                        max_out                         => energy_S
                                                );
 
                eventdetect : event_detector
                        Port map(       clk                                     =>      clk_S,
                                                        enable                          => enable_S,
                                                        gate_in                         =>      ed_gate_S,
                                                        zeroX_in                                =>      zeroX_S,
                                                        threshold_in            =>      threshold_S,
                                                        integral_in                     =>      integral_S,
                                                        event_detect_out        =>      event_detect_S
                                                );
 
                rst_S                                                   <=      rst;
                clk_S                                                   <=      clk;
                enable_S                                                <=      enable;
                program_S                                       <=      program;
                baseline_enable_S                       <= baseline_enable;
                double_CF_S                                     <= double_CF_in;
                data_in_S                                       <=      data_in;        -- add a sign bit to avoid disaster
                cf_pwr_S                                                <= cf_pwr_in;
                cf_delay_S                                      <= conv_std_logic_vector((2**conv_integer(cf_pwr_S)), 8);
                baseline_delay_S                        <= conv_std_logic_vector((2**(conv_integer(cf_pwr_S)) + 16), 8);
                cf_integral_pwr_S                       <=      cf_integral_pwr_in;
                baseline_pwr_S                          <=      baseline_pwr_in;
                baseline_inhibit_cnt_S  <=      baseline_inhibit_cnt_in;
                event_inhibit_cnt_S             <=      event_inhibit_cnt_in;
                baseline_out                            <=      baseline_S;
                clamped_out                                     <=      clamped_S;
 
                CF_mux : process(double_CF_S, clamped_S)
                begin
                        case (double_CF_S) is
                                when '1' =>
                                        CFdev_clamp_S(CFdev_clamp_S'high)                                               <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S(CFdev_clamp_S'high - 1)                                   <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S((CFdev_clamp_S'high - 2) downto 0) <= clamped_S((clamped_S'high - 1) downto 1);
                                when '0' =>
                                        CFdev_clamp_S(CFdev_clamp_S'high)                                               <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S(CFdev_clamp_S'high - 1)                                   <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S(CFdev_clamp_S'high - 2)                                   <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);
                                when others =>
                                        CFdev_clamp_S(CFdev_clamp_S'high)                                               <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S(CFdev_clamp_S'high - 1)                                   <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S(CFdev_clamp_S'high - 2)                                   <= clamped_S(clamped_S'high);
                                        CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);
                        end case;
                end process;
 
                del_clamp_out                   <=      del_clamp_S;
                CFdev_clamp_out         <=      CFdev_clamp_S;
                cf_trace_out                    <=      cf_trace_S;
                threshold_S                             <=      threshold_in;
                integral                                        <= integral_S;
                sample_nr                               <= sample_nr_S;
                zeroX_out                               <=      zeroX_S;
                event_detect_out                <=      event_detect_S;
                bl_gate_out                             <=      bl_gate_S;
                ed_gate_out                             <=      ed_gate_S;
                eventdata_valid         <= eventdata_valid_S;
                eventnr_out                             <= eventnr_S;
                fraction                                        <= time_fraction_S;
                energy                                  <=      energy_S;
 
end Behavioral;

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[/] [pulse_processing_algorithm/] [CF_process.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	panda_emc	`-----------------------------------------------------------------------------------------------`
2			`--`
3			`-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration`
4			`-- p.j.j.lemmens@rug.nl`
5			`-- http://www-panda.gsi.de`
6			`--`
7			`-- As a reference, please use:`
8			`-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,`
9			`-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"`
10			`-- Nuclear Inst. and Methods in Physics Research, A ....`
11			`--`
12			`--`
13			`-- This program is free software; you can redistribute it and/or modify`
14			`-- it under the terms of the GNU Lesser General Public License as published by`
15			`-- the Free Software Foundation; either version 3 of the License, or`
16			`-- (at your option) any later version.`
17			`--`
18			`-- This program is distributed in the hope that it will be useful,`
19			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
20			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
21			`-- GNU Lesser General Public License for more details.`
22			`--`
23			`-- You should have received a copy of the GNU General Public License`
24			`-- along with this program; if not, write to the Free Software`
25			`-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA`
26			`--`
27			`-----------------------------------------------------------------------------------------------`
28			`-----------------------------------------------------------------------------------------------`
29			`-- Company: KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands`
30			`-- Author: P.J.J. Lemmens`
31			`-- Design Name: Feature Extraction`
32			`-- Module Name: CF_process.vhd`
33			`-- Description: - baseline sampling, calculation & correction`
34			`-- - Constant Fraction pulse construction`
35			`-- - Zero-crossing detection`
36			`-- - event-detection`
37			`-- - baseline_sampling & event_detection gating/inhibition`
38			`-- - sub_sample timing calculation through interpolation`
39			`-- - time-stamp generation`
40			`-- - energy reading/peak-detection`
41			`--`
42			`-----------------------------------------------------------------------------------------------`
43
44			`library IEEE;`
45			`use IEEE.STD_LOGIC_1164.ALL;`
46			`use IEEE.STD_LOGIC_ARITH.ALL;`
47			`use IEEE.STD_LOGIC_SIGNED.ALL;`
48			`use IEEE.numeric_std.ALL;`
49
50			`entity CF_process is`
51			`generic( WIDTH : natural := 1;`
52			`MAX_CF_PWR : natural := 1;-- CF_DELAY : natural := 1;-- CF_PWR : natural := 1;`
53			`MAX_BASELINE_PWR : natural := 1;`
54			`ZEROX_WINDOW_PWR : natural := 1;`
55			`ZEROX_THRESHOLD_PWR : natural := 1;-- INTEGRAL_PWR : natural := 1;-- INTEGRAL_THRESHOLD_PWR : natural := 1;`
56			`INTERP_CYCLES : natural := 1`
57			`);`
58			`Port ( rst : in STD_LOGIC;`
59			`clk : in STD_LOGIC;`
60			`enable : in STD_LOGIC;`
61			`program : in STD_LOGIC;`
62			`baseline_enable : in STD_LOGIC;`
63			`double_CF_in : in STD_LOGIC;`
64			`data_in : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);`
65			`threshold_in : in STD_LOGIC_VECTOR;`
66			`cf_pwr_in : in STD_LOGIC_VECTOR;`
67			`cf_integral_pwr_in : in STD_LOGIC_VECTOR;`
68			`baseline_pwr_in : in STD_LOGIC_VECTOR;`
69			`baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;`
70			`event_inhibit_cnt_in : in STD_LOGIC_VECTOR;`
71			`baseline_out : out STD_LOGIC_VECTOR;`
72			`clamped_out : out STD_LOGIC_VECTOR;`
73			`del_clamp_out : out STD_LOGIC_VECTOR;`
74			`CFdev_clamp_out : out STD_LOGIC_VECTOR;`
75			`cf_trace_out : out STD_LOGIC_VECTOR;`
76			`integral : out STD_LOGIC_VECTOR;`
77			`sample_nr : out STD_LOGIC_VECTOR;`
78			`zeroX_out : out STD_LOGIC;`
79			`event_detect_out : out STD_LOGIC;`
80			`bl_gate_out : out STD_LOGIC;`
81			`ed_gate_out : out STD_LOGIC;`
82			`eventdata_valid : out STD_LOGIC;`
83			`eventnr_out : out STD_LOGIC_VECTOR;`
84			`fraction : out STD_LOGIC_VECTOR;`
85			`energy : out STD_LOGIC_VECTOR`
86			`);`
87			`end CF_process;`
88
89			`architecture Behavioral of CF_process is`
90
91			`constant MAX_CF_DELAY : natural := 2**MAX_CF_PWR;`
92			`constant PEAK_DET_BUF_PWR : natural := 4;`
93			`constant PEAK_DET_BUFSIZE : natural := 2**PEAK_DET_BUF_PWR;`
94			`-- constant CFWINDOW_SIZE : natural := 2**CF_WINDOW_PWR;`
95			`-- constant INTEGRAL_SIZE : natural := 2**INTEGRAL_PWR;`
96			`constant FRACTION_SIZE : natural := INTERP_CYCLES; -- - ZEROX_WINDOW_PWR; --all interp bits are fraction now !! interp between 2 samples`
97			`-- constant GATE_PWR : natural := BASELINE_PWR;`
98
99			`component baseline_follower`
100			`generic( WINDOW_PWR : natural := 1; -- defines the maximum window in which event disturbance is seen`
101			`MAX_BASELINE_PWR : natural := 1 -- size of the baseline window`
102			`);`
103			`Port ( rst : in STD_LOGIC;`
104			`clk : in STD_LOGIC;`
105			`enable : in STD_LOGIC;`
106			`program : in STD_LOGIC;`
107			`gate : in STD_LOGIC;`
108			`baseline_pwr_in : in STD_LOGIC_VECTOR(7 downto 0);`
109			`buffer_size_in : in STD_LOGIC_VECTOR(7 downto 0);`
110			`data_in : in STD_LOGIC_VECTOR;`
111			`data_out : out STD_LOGIC_VECTOR;`
112			`buffer_data_valid : out STD_LOGIC`
113			`);`
114			`end component;`
115
116			`component SISO_sub_a`
117			`generic( A_MINUS_B : boolean);`
118			`port (`
119			`dataa : IN STD_LOGIC_VECTOR;`
120			`datab : IN STD_LOGIC_VECTOR;`
121			`result : OUT STD_LOGIC_VECTOR`
122			`);`
123			`end component;`
124
125			`component progdelay_pipeline`
126			`generic (RAM_SIZE_PWR : natural := 1;`
127			`FLEX_RAM_STYLE : string := "distributed");`
128			`Port (clk : in STD_LOGIC;`
129			`rst : in STD_LOGIC;`
130			`enable : in STD_LOGIC;`
131			`program : in STD_LOGIC;`
132			`delay_in : in STD_LOGIC_VECTOR(7 downto 0);`
133			`data_in : in STD_LOGIC_VECTOR;`
134			`data_out : out STD_LOGIC_VECTOR;`
135			`data_valid : out std_logic`
136			`);`
137			`end component;`
138
139			`component CF_zeroX`
140			`generic( BASE_WINDOW_PWR : natural;`
141			`ZEROX_WINDOW_PWR : natural;`
142			`ZEROX_THRESHOLD_PWR : natural`
143			`);`
144			`port ( rst : in STD_LOGIC;`
145			`clk : in STD_LOGIC;`
146			`enable : in STD_LOGIC;`
147			`data_in : in STD_LOGIC_VECTOR;`
148			`zeroX_out : out STD_LOGIC`
149			`);`
150			`end component;`
151
152			`component moving_average_programmable`
153			`generic(MEM_PWR : natural);`
154			`port (rst : in std_logic;`
155			`clk : in std_logic;`
156			`enable : in std_logic;`
157			`program : in std_logic;`
158			`avg_pwr_in : in std_logic_vector(7 downto 0);`
159			`data_in : in std_logic_vector;`
160			`data_out : out std_logic_vector`
161			`);`
162			`end component;`
163
164			`component gate_generator`
165			`-- generic( BASE_WINDOW_PWR : natural := 1;`
166			`-- EVENT_INHIB_PWR : natural := 1`
167			`-- );`
168			`Port ( rst : in STD_LOGIC;`
169			`clk : in STD_LOGIC;`
170			`enable : in STD_LOGIC;`
171			`program : in STD_LOGIC;`
172			`baseline_enable : in STD_LOGIC;`
173			`event_in : in STD_LOGIC;`
174			`baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;`
175			`event_inhibit_cnt_in : in STD_LOGIC_VECTOR;`
176			`bl_gate_out : out STD_LOGIC; -- baseline gate-signal`
177			`ed_gate_out : out STD_LOGIC -- baseline gating inhibited because of event`
178			`);`
179			`end component;`
180
181			`component timing_linear_interp`
182			`generic( INTERP_CYCLES : natural);`
183			`Port ( rst : in STD_LOGIC;`
184			`clk : in STD_LOGIC;`
185			`enable : in STD_LOGIC;`
186			`trigger : in STD_LOGIC;`
187			`data_in : in STD_LOGIC_VECTOR;`
188			`samplenr_in : in STD_LOGIC_VECTOR;`
189			`eventnr_out : out STD_LOGIC_VECTOR;`
190			`fraction_out : out STD_LOGIC_VECTOR;`
191			`eventdata_valid : out STD_LOGIC`
192			`);`
193			`end component;`
194
195			`component sample_counter`
196			`Port (rst : in STD_LOGIC;`
197			`clk : in STD_LOGIC;`
198			`enable : in STD_LOGIC := '1';`
199			`sample_nr_out : out STD_LOGIC_VECTOR (63 downto 0)`
200			`);`
201			`end component;`
202
203			`component history_max`
204			`generic( MEM_PWR : natural := 1;`
205			`DEPTH : natural := 1`
206			`);`
207			`Port ( rst : in STD_LOGIC;`
208			`clk : in STD_LOGIC;`
209			`enable : in STD_LOGIC := '1';`
210			`trigger : in STD_LOGIC;`
211			`data_in : in STD_LOGIC_VECTOR;`
212			`max_valid : out STD_LOGIC;`
213			`max_out : out STD_LOGIC_VECTOR`
214			`);`
215			`end component;`
216
217			`component event_detector`
218			`Port ( clk : in STD_LOGIC;`
219			`enable : in STD_LOGIC := '1';`
220			`gate_in : in STD_LOGIC;`
221			`zeroX_in : in STD_LOGIC;`
222			`threshold_in : in STD_LOGIC_VECTOR;`
223			`integral_in : in STD_LOGIC_VECTOR;`
224			`event_detect_out : out STD_LOGIC`
225			`);`
226			`end component;`
227
228			`-----------------------------------------------------------------------`
229
230			`signal rst_S : std_logic := '1';`
231			`signal clk_S : std_logic := '0';`
232			`signal enable_S : std_logic := '0';`
233			`signal program_S : std_logic := '0';`
234			`signal baseline_enable_S : STD_LOGIC := '0';`
235			`signal double_CF_S : STD_LOGIC := '0';`
236			`signal data_in_S : std_logic_vector (WIDTH - 1 downto 0) := (others => '0');`
237			`signal baseline_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
238			`signal clamped_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
239			`signal CFdev_clamp_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
240			`signal del_clamp_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
241			`signal cf_trace_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
242			`signal threshold_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
243			`signal integral_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
244			`signal cf_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value`
245			`signal cf_integral_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(4, 8); -- original default value = (mwd_power - 1)`
246			`signal cf_delay_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(16, 8);`
247			`signal baseline_pwr_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');`
248			`signal baseline_delay_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');`
249			`signal baseline_inhibit_cnt_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(32, 8); -- original default value`
250			`signal event_inhibit_cnt_S : STD_LOGIC_VECTOR (7 downto 0) := conv_std_logic_vector(16, 8); -- original default value`
251			`signal event_detect_S : std_logic := '0';`
252			`signal zeroX_S : STD_LOGIC := '0';`
253			`signal bl_gate_S : STD_LOGIC := '0';`
254			`signal ed_gate_S : STD_LOGIC := '0';`
255			`signal sample_nr_S : STD_LOGIC_VECTOR (63 downto 0) := (others => '0');`
256			`signal eventnr_S : STD_LOGIC_VECTOR (63 downto 0) := (others => '0');`
257			`signal time_fraction_S : STD_LOGIC_VECTOR (FRACTION_SIZE - 1 downto 0) := (others => '0');`
258			`signal energy_S : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others => '0');`
259			`signal eventdata_valid_S : STD_LOGIC := '0';`
260			`signal max_valid_S : STD_LOGIC := '0';`
261
262			`-----------------------------------------------------------------------`
263
264			`begin`
265
266			`baseline : baseline_follower`
267			`generic map(WINDOW_PWR => MAX_CF_PWR,`
268			`MAX_BASELINE_PWR => MAX_BASELINE_PWR`
269			`)`
270			`port map ( rst => rst_S,`
271			`clk => clk_S,`
272			`enable => enable_S,`
273			`program => program_S,`
274			`gate => bl_gate_S,`
275			`baseline_pwr_in => baseline_pwr_S,`
276			`buffer_size_in => baseline_delay_S,`
277			`data_in => data_in_S,`
278			`data_out => baseline_S,`
279			`buffer_data_valid => open`
280			`);`
281
282			`remove_baseline : SISO_sub_a`
283			`GENERIC MAP(--WIDTH => data_in_S'length,`
284			`A_MINUS_B => true)`
285			`PORT MAP ( dataa => data_in_S,`
286			`datab => baseline_S,`
287			`result => clamped_S`
288			`);`
289
290			`clamped_pipe : progdelay_pipeline`
291			`generic map(RAM_SIZE_PWR => MAX_CF_PWR,`
292			`FLEX_RAM_STYLE => "distributed")`
293			`PORT MAP(rst => rst_S,`
294			`clk => clk_S,`
295			`enable => enable_S,`
296			`program => program_S,`
297			`delay_in => cf_delay_S,`
298			`data_in => clamped_S,`
299			`data_out => del_clamp_S,`
300			`data_valid => open`
301			`);`
302
303			`CF_sub : SISO_sub_a`
304			`GENERIC MAP(--WIDTH => cf_trace_S'length,`
305			`A_MINUS_B => true)`
306			`PORT MAP ( dataa => del_clamp_S,`
307			`datab => CFdev_clamp_S,`
308			`result => cf_trace_S`
309			`);`
310
311			`zeroX : CF_zeroX`
312			`generic map(BASE_WINDOW_PWR => MAX_CF_PWR, -- CF_WINDOW_PWR,`
313			`ZEROX_WINDOW_PWR => ZEROX_WINDOW_PWR,`
314			`ZEROX_THRESHOLD_PWR => ZEROX_THRESHOLD_PWR`
315			`)`
316			`port map ( rst => rst_S,`
317			`clk => clk_S,`
318			`enable => enable_S,`
319			`data_in => cf_trace_S,`
320			`zeroX_out => zeroX_S`
321			`);`
322
323			`CF_integral : moving_average_programmable`
324			`generic map(MEM_PWR => MAX_CF_PWR)`
325			`port map( rst => rst_S,`
326			`clk => clk_S,`
327			`enable => enable_S,`
328			`program => program_S,`
329			`avg_pwr_in => cf_integral_pwr_S,`
330			`data_in => clamped_S,`
331			`data_out => integral_S`
332			`);`
333
334			`gator : gate_generator`
335			`-- generic map(BASE_WINDOW_PWR => GATE_PWR,`
336			`-- EVENT_INHIB_PWR => MAX_CF_PWR --CF_WINDOW_PWR`
337			`-- )`
338			`port map ( rst => rst_S,`
339			`clk => clk_S,`
340			`enable => enable_S,`
341			`program => program_S,`
342			`baseline_enable => baseline_enable_S,`
343			`event_in => event_detect_S,`
344			`baseline_inhibit_cnt_in => baseline_inhibit_cnt_S,`
345			`event_inhibit_cnt_in => event_inhibit_cnt_S,`
346			`bl_gate_out => bl_gate_S,`
347			`ed_gate_out => ed_gate_S`
348			`);`
349
350			`timing : timing_linear_interp`
351			`generic map(INTERP_CYCLES => INTERP_CYCLES)`
352			`Port map( rst => rst_S,`
353			`clk => clk_S,`
354			`enable => enable_S,`
355			`trigger => event_detect_S,`
356			`data_in => cf_trace_S,`
357			`samplenr_in => sample_nr_S,`
358			`eventnr_out => eventnr_S,`
359			`fraction_out => time_fraction_S,`
360			`eventdata_valid => eventdata_valid_S`
361			`);`
362
363			`time_stamp : sample_counter`
364			`Port map( rst => rst_S,`
365			`clk => clk_S,`
366			`enable => enable_S,`
367			`sample_nr_out => sample_nr_S`
368			`);`
369
370			`peak_detect : history_max`
371			`generic map(MEM_PWR => PEAK_DET_BUF_PWR, --CF_WINDOW_PWR,`
372			`DEPTH => PEAK_DET_BUFSIZE) --CF_WINDOWSIZE -10`
373			`port map ( rst => rst_S,`
374			`clk => clk_S,`
375			`enable => enable_S,`
376			`trigger => event_detect_S,`
377			`data_in => clamped_S,`
378			`max_valid => max_valid_S,`
379			`max_out => energy_S`
380			`);`
381
382			`eventdetect : event_detector`
383			`Port map( clk => clk_S,`
384			`enable => enable_S,`
385			`gate_in => ed_gate_S,`
386			`zeroX_in => zeroX_S,`
387			`threshold_in => threshold_S,`
388			`integral_in => integral_S,`
389			`event_detect_out => event_detect_S`
390			`);`
391
392			`rst_S <= rst;`
393			`clk_S <= clk;`
394			`enable_S <= enable;`
395			`program_S <= program;`
396			`baseline_enable_S <= baseline_enable;`
397			`double_CF_S <= double_CF_in;`
398			`data_in_S <= data_in; -- add a sign bit to avoid disaster`
399			`cf_pwr_S <= cf_pwr_in;`
400			`cf_delay_S <= conv_std_logic_vector((2**conv_integer(cf_pwr_S)), 8);`
401			`baseline_delay_S <= conv_std_logic_vector((2**(conv_integer(cf_pwr_S)) + 16), 8);`
402			`cf_integral_pwr_S <= cf_integral_pwr_in;`
403			`baseline_pwr_S <= baseline_pwr_in;`
404			`baseline_inhibit_cnt_S <= baseline_inhibit_cnt_in;`
405			`event_inhibit_cnt_S <= event_inhibit_cnt_in;`
406			`baseline_out <= baseline_S;`
407			`clamped_out <= clamped_S;`
408
409			`CF_mux : process(double_CF_S, clamped_S)`
410			`begin`
411			`case (double_CF_S) is`
412			`when '1' =>`
413			`CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);`
414			`CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);`
415			`CFdev_clamp_S((CFdev_clamp_S'high - 2) downto 0) <= clamped_S((clamped_S'high - 1) downto 1);`
416			`when '0' =>`
417			`CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);`
418			`CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);`
419			`CFdev_clamp_S(CFdev_clamp_S'high - 2) <= clamped_S(clamped_S'high);`
420			`CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);`
421			`when others =>`
422			`CFdev_clamp_S(CFdev_clamp_S'high) <= clamped_S(clamped_S'high);`
423			`CFdev_clamp_S(CFdev_clamp_S'high - 1) <= clamped_S(clamped_S'high);`
424			`CFdev_clamp_S(CFdev_clamp_S'high - 2) <= clamped_S(clamped_S'high);`
425			`CFdev_clamp_S((CFdev_clamp_S'high - 3) downto 0) <= clamped_S((clamped_S'high - 1) downto 2);`
426			`end case;`
427			`end process;`
428
429			`del_clamp_out <= del_clamp_S;`
430			`CFdev_clamp_out <= CFdev_clamp_S;`
431			`cf_trace_out <= cf_trace_S;`
432			`threshold_S <= threshold_in;`
433			`integral <= integral_S;`
434			`sample_nr <= sample_nr_S;`
435			`zeroX_out <= zeroX_S;`
436			`event_detect_out <= event_detect_S;`
437			`bl_gate_out <= bl_gate_S;`
438			`ed_gate_out <= ed_gate_S;`
439			`eventdata_valid <= eventdata_valid_S;`
440			`eventnr_out <= eventnr_S;`
441			`fraction <= time_fraction_S;`
442			`energy <= energy_S;`
443
444			`end Behavioral;`