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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : CF_zeroX
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-- Description : Zero-crossing detection
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-- Inputs :
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-- Outputs :
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-----------------------------------------------------------------------------------------------
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-- Generics :
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-- Parameters :
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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entity CF_zeroX is
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generic( BASE_WINDOW_PWR : natural := 1;
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ZEROX_WINDOW_PWR : natural := 1;
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ZEROX_THRESHOLD_PWR : natural := 1
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);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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data_in : in STD_LOGIC_VECTOR;
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zeroX_out : out STD_LOGIC
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);
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end CF_zeroX;
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architecture Behavioral of CF_zeroX is
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constant WIDTH : natural := data_in'length;
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constant ZEROX_WINDOW : natural := 2**ZEROX_WINDOW_PWR;
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constant INHIBIT_COUNT : natural := ZEROX_WINDOW; -- gating period after zero-cross-detection
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component pipeline
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generic( RAM_SIZE_PWR : natural;
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DEPTH : natural);
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port ( rst : IN STD_LOGIC ;
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clk : IN STD_LOGIC ;
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enable : IN STD_LOGIC := '1';
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data_in : IN STD_LOGIC_VECTOR;
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data_out : OUT STD_LOGIC_VECTOR
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);
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end component;
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component compare_a2b is
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Port ( clk : std_logic;
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a : in STD_LOGIC_VECTOR;
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b : in STD_LOGIC_VECTOR;
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lt : out STD_LOGIC;
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gt : out STD_LOGIC
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);
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end component;
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-----------------------------------------------------------------------
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal data_in_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal del1_data_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal del2_data_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal zeroX_S : std_logic := '0';
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signal front1_hi_enuf_S : std_logic := '0';
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signal front2_hi_enuf_S : std_logic := '0';
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signal end_lo_enuf_S : std_logic := '0';
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signal inhibited_S : std_logic := '0';
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signal inhibit_cnt_S : std_logic_vector(ZEROX_WINDOW_PWR + 1 downto 0) := conv_std_logic_vector(INHIBIT_COUNT,ZEROX_WINDOW_PWR + 2);
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signal p1_threshold_S : std_logic_vector(WIDTH - 1 downto 0) := conv_std_logic_vector(2,WIDTH); -- add a SIGN bit !!!
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signal p2_threshold_S : std_logic_vector(WIDTH - 1 downto 0) := conv_std_logic_vector(1,WIDTH); -- add a SIGN bit !!!
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signal n_threshold_S : std_logic_vector(WIDTH - 1 downto 0) := conv_std_logic_vector(-1,WIDTH); -- add a SIGN bit !!!
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---------------------------------------------------------------------------------------------------------
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begin
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zerox_win_proc : process(rst_S, clk_S, enable_S, data_in_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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del1_data_S <= (others => '0');
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del2_data_S <= (others => '0');
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else
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if (enable_S = '1') then
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del1_data_S <= data_in_S;
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del2_data_S <= del1_data_S;
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end if;
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end if;
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end if;
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end process;
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p1_threshold : compare_a2b -- check if data at the front of the zerox-window exceeds the positive threshold
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port map ( clk => clk_S,
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a => data_in_S,
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b => p1_threshold_S,
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lt => open,
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gt => front1_hi_enuf_S
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);
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p2_threshold : compare_a2b -- check if data at the front of the zerox-window exceeds the positive threshold
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port map ( clk => clk_S,
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a => del1_data_S,
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b => p2_threshold_S,
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lt => open,
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gt => front2_hi_enuf_S
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);
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n_threshold : compare_a2b -- check if data at the end of the zerox-window goes below the 1st negative threshold
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port map ( clk => clk_S,
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a => del2_data_S,
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b => n_threshold_S,
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lt => end_lo_enuf_S,
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gt => open
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);
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inhibit : compare_a2b -- check if data at the end of the zerox-window stays above the 2nd negative threshold
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port map ( clk => clk_S,
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a => inhibit_cnt_S,
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b => conv_std_logic_vector(0, inhibit_cnt_S'length),
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lt => open,
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gt => inhibited_S
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);
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clk_S <= clk; -- connect clk PORT to internal clk-signal
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rst_S <= rst;
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enable_S <= enable;
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data_in_S <= data_in;
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-- zeroX_S <= front1_hi_enuf_S and front2_hi_enuf_S and end_lo_enuf_S and not(inhibited_S);
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zeroX_out <= zerox_S;
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-- positive threshold = 4*negative threshold... constant-fraction of 4
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p1_threshold_S <= conv_std_logic_vector(2**(ZEROX_THRESHOLD_PWR + 1), WIDTH);
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p2_threshold_S <= conv_std_logic_vector(2**(ZEROX_THRESHOLD_PWR), WIDTH);
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n_threshold_S <= conv_std_logic_vector(-(2**ZEROX_THRESHOLD_PWR), WIDTH);
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zeroX_inhibit : process (clk_S, rst_S, enable_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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zeroX_S <= '0';
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else
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if (enable_S = '1') then
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--zeroX_out <= zeroX_S;
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zeroX_S <= front1_hi_enuf_S and front2_hi_enuf_S and end_lo_enuf_S and not(inhibited_S);
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end if;
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if (enable_S = '1') then
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if (zeroX_S = '1') then
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inhibit_cnt_S <= conv_std_logic_vector(INHIBIT_COUNT,ZEROX_WINDOW_PWR + 2);
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else
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if (inhibit_cnt_S > 0) then
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inhibit_cnt_S <= inhibit_cnt_S - 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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