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[/] [pulse_processing_algorithm/] [FeatureExtraction.vhd] - Blame information for rev 2

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1 2 panda_emc 
-----------------------------------------------------------------------------------------------
2 
--
3 
--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration
4 
--              p.j.j.lemmens@rug.nl
5 
--    http://www-panda.gsi.de
6 
--
7 
--    As a reference, please use:
8 
--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
9 
--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
10 
--    Nuclear Inst. and Methods in Physics Research, A ....
11 
--
12 
--
13 
--    This program is free software; you can redistribute it and/or modify
14 
--    it under the terms of the GNU Lesser General Public License as published by
15 
--    the Free Software Foundation; either version 3 of the License, or
16 
--    (at your option) any later version.
17 
--
18 
--    This program is distributed in the hope that it will be useful,
19 
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
20 
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21 
--    GNU Lesser General Public License for more details.
22 
--
23 
--    You should have received a copy of the GNU General Public License
24 
--    along with this program; if not, write to the Free Software
25 
--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
26 
--
27 
-----------------------------------------------------------------------------------------------
28 
-----------------------------------------------------------------------------------------------
29 
-- Company:                     KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands
30 
-- Author:                      P.J.J. Lemmens
31 
-- Design Name: Feature Extraction
32 
-- Module Name: Feature_Extraction
33 
-- Description: - VME interface for SIS3302 by Struck, modified by KVI
34 
--                                              - 2 channels Feature-extraction
35 
-----------------------------------------------------------------------------------------------
36 
--      Generics                :
37 
--      Parameters      :
38 
-----------------------------------------------------------------------------------------------
39 
 
40 
library IEEE;
41 
USE ieee.std_logic_1164.all ;
42 
use IEEE.std_logic_arith.all;
43 
use IEEE.std_logic_signed.all;
44 
 
45 
 
46 
entity Feature_Extraction is
47 
port(   uP_CLK                                                                  : in std_logic;
48 
                Reset                                                                           : in std_logic;
49 
                ADC_CLK                                                                 : in std_logic;
50 
                ADCin                                                                           : in std_logic_vector(15 downto 0);
51 
                invert_data_in                                                  : in std_logic;
52 
                externaltrigger                                         : in std_logic;
53 
                softwaretrigger                                         : in std_logic;
54 
 
55 
                cmd_output_select                                               : in std_logic_vector(3 downto 0);
56 
                cmd_start_adc                                                   : in std_logic;
57 
                cmd_enableFE                                                    : in std_logic;
58 
                cmd_baseline_enable                                     : in std_logic;
59 
                cmd_double_CF                                                   : in std_logic;
60 
                cmd_program_params                                      : in std_logic;
61 
                cmd_bypass_mwd                                                  : in std_logic;
62 
                cmd_bypass_reshape                                      : in std_logic;
63 
 
64 
                decay_correction_in                                     : in STD_LOGIC_VECTOR(31 downto 0);
65 
                reshape_correction_in                           : in STD_LOGIC_VECTOR(31 downto 0);
66 
                buffer_size                                                             : in std_logic_vector(31 downto 0);  -- number of samples to read from buffer
67 
                int_signal_threshold_in                         : in std_logic_vector(15 downto 0);  -- event-trigger threshold on the integrated input signal
68 
                mwd_pwr_in                                                              : in std_logic_vector(7 downto 0);  -- power of 2 for mwd size
69 
                cf_pwr_in                                                               : in std_logic_vector(7 downto 0);  -- power of 2 for cf delay
70 
                cf_integral_pwr_in                                      : in std_logic_vector(7 downto 0);  -- power of 2 for cf-generation
71 
                baseline_pwr_in                                         : in STD_LOGIC_VECTOR(7 downto 0);
72 
                baseline_inhibit_cnt_in                         : in std_logic_vector(7 downto 0);  -- baseline data-collect inhibition after event
73 
                event_inhibit_cnt_in                                    : in std_logic_vector(7 downto 0);  -- event detect inhibition after event
74 
 
75 
                fb_flowctrl_running                                     : out std_logic;
76 
                fb_chain_enable                                         : out std_logic;
77 
                feedback_port0                                                  : out   std_logic_vector(31 downto 0);
78 
                feedback_port1                                                  : out   std_logic_vector(31 downto 0);
79 
                feedback_port2                                                  : out   std_logic_vector(15 downto 0);
80 
                feedback_port3                                                  : out   std_logic_vector(31 downto 0);
81 
 
82 
                adc_ram_fifo_data_wr_data                       : out std_logic_vector(31 downto 0);
83 
                adc_ram_fifo_address                                    : out std_logic_vector(31 downto 0);
84 
                adc_ram_fifo_data_wr_ce                         : out std_logic;
85 
                adc_ram_fifo_addr_wr_ce                         : out std_logic;
86 
                last_buffer_adc_ram_fifo_wr_addr        : out std_logic_vector(31 downto 0)
87 
        );
88 
end Feature_Extraction;
89 
 
90 
architecture behaviour of Feature_Extraction is
91 
 
92 
        constant        WIDTH                                                   :       natural := 16;          --      width of data
93 
        constant        MAX_MWD_PWR                                     :       natural :=      6;                      -- max.
94 
        constant        MAX_CF_PWR                                      :       natural :=      5;                      -- max.
95 
        constant        MAX_BASELINE_PWR                        :       natural :=      9;                      --      max. length of baseline averaging                                       (2^10=1024)
96 
        constant        ZEROX_WINDOW_PWR                        :       natural :=      1;                      -- length of zero-crossing window                               (2^2=4 samples)
97 
        constant        ZEROX_THRESHOLD_PWR             :       natural :=      0;                       -- magnitude of zero-crossing threshold         (2^5=32)
98 
        constant        INTERP_CYCLES                           :       natural :=      11;             -- interpolation cycles for time-fraction calculation
99 
 
100 
        constant FRACTION_SIZE                          : natural       := INTERP_CYCLES;--     - ZEROX_WINDOW_PWR; --all  interp bits are fraction now !! interp between 2 samples
101 
 
102 
        constant BASE_ADDR                                      : std_logic_vector(31 downto 0) := (others => '0');       -- vme-mem base address for ringbuffer
103 
 
104 
 
105 
        COMPONENT MWD_CF_process
106 
                generic(        WIDTH                                                   :       natural := 1;
107 
                                        MAX_MWD_PWR                                     :       natural := 1;
108 
                                        MAX_CF_PWR                                      :       natural :=      1;
109 
                                        MAX_BASELINE_PWR                        :       natural :=      1;
110 
                                        ZEROX_WINDOW_PWR                        :       natural :=      1;
111 
                                        ZEROX_THRESHOLD_PWR             :       natural :=      1;
112 
                                        INTERP_CYCLES                           :       natural :=      1
113 
                                );
114 
                Port (  rst                                                     : in STD_LOGIC;
115 
                                        clk                                                     : in STD_LOGIC;
116 
                                        enable                                          : in STD_LOGIC;
117 
                                        program                                         : in STD_LOGIC;
118 
                                        baseline_enable                 : in STD_LOGIC;
119 
                                        double_CF_in                            : in STD_LOGIC;
120 
                                        bypass_mwd                                      : in STD_LOGIC;
121 
                                        bypass_reshape                          : in STD_LOGIC;
122 
                                        data_in                                         : in STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
123 
                                        invert_data_in                          : in STD_LOGIC;
124 
                                        decay_correction_in             : in STD_LOGIC_VECTOR;
125 
                                        reshape_correction_in   : in STD_LOGIC_VECTOR;
126 
                                        threshold_in                            : in STD_LOGIC_VECTOR;
127 
                                        mwd_pwr_in                                      : in std_logic_vector(7 downto 0);  -- power of 2 for mwd-windowsize
128 
                                        cf_pwr_in                                       : in std_logic_vector(7 downto 0);  -- power of 2 for cf-delay
129 
                                        cf_integral_pwr_in              : in std_logic_vector(7 downto 0);  -- power of 2 for CF integral
130 
                                        baseline_pwr_in                 : in STD_LOGIC_VECTOR(7 downto 0)                         := (others     => '0');
131 
                                        baseline_inhibit_cnt_in : in std_logic_vector(7 downto 0);  -- baseline data-collect inhibition after event
132 
                                        event_inhibit_cnt_in            : in std_logic_vector(7 downto 0);  -- event detect inhibition after event
133 
                                        mwd_switch_out                          : out STD_LOGIC_VECTOR;
134 
                                        baseline_out                            : out STD_LOGIC_VECTOR;
135 
                                        clamped_out                                     : out STD_LOGIC_VECTOR;
136 
                                        del_clamp_out                           : out STD_LOGIC_VECTOR;
137 
                                        CFdev_clamp_out                 : out STD_LOGIC_VECTOR;
138 
                                        cf_trace_out                            : out STD_LOGIC_VECTOR;
139 
                                        integral                                                : out STD_LOGIC_VECTOR;
140 
                                        sample_nr                                       : out STD_LOGIC_VECTOR;
141 
                                        zeroX_out                                       : out STD_LOGIC;
142 
                                        event_detect_out                        : out STD_LOGIC;
143 
                                        bl_gate_out                                     : out STD_LOGIC;
144 
                                        ed_gate_out                                     : out STD_LOGIC;
145 
                                        eventdata_valid                 : out STD_LOGIC;
146 
                                        eventnr_out                                     : out STD_LOGIC_VECTOR;
147 
                                        fraction                                                : out STD_LOGIC_VECTOR;
148 
                                        energy                                          : out STD_LOGIC_VECTOR
149 
                                );
150 
        END COMPONENT;
151 
 
152 
        COMPONENT output_mux
153 
                Port (  rst                                     : in    STD_LOGIC;
154 
                                        clk                                     : in    STD_LOGIC;
155 
                                        input_valid                     : in    STD_LOGIC;
156 
                                        energy_in                       : in    STD_LOGIC_VECTOR;
157 
                                        eventnr_in                      : in    STD_LOGIC_VECTOR;
158 
                                        fraction_in                     : in    STD_LOGIC_VECTOR;
159 
                                        output_valid            : out   STD_LOGIC;
160 
                                        outdata16                       : out   STD_LOGIC_VECTOR(15 downto 0)
161 
                                );
162 
        end COMPONENT;
163 
 
164 
        component output_select
165 
                PORT    (       clk                                     : in  std_logic;
166 
                                        output_select           : in  std_logic_vector;
167 
                                        indata_in                       : in  std_logic_vector; -- Feature Extraction data_in
168 
                                        mwd_in                          : in  std_logic_vector;
169 
                                        baseline_in                     : in  std_logic_vector;
170 
                                        clamped_in                      : in  std_logic_vector;
171 
                                        del_clamp_in            : in  std_logic_vector;
172 
                                        CFdev_clamp_in          : in  std_logic_vector;
173 
                                        cf_trace_in                     : in  std_logic_vector;
174 
                                        integral_in                     : in  std_logic_vector;
175 
                                        zerox_in                                : in    std_logic;
176 
                                        eventdetect_in          : in    std_logic;
177 
                                        gate_in                         : in    std_logic;
178 
                                        energy_in                       : in  std_logic_vector;
179 
                                        mux_data_in                     : in    std_logic_vector;
180 
                                        samplenr_in                     : in    STD_LOGIC_VECTOR;
181 
                                        fraction_in                     : in    STD_LOGIC_VECTOR;
182 
                                        mux_data_valid_in       : in    std_logic;
183 
                                        fe_data_valid           : in    std_logic;
184 
                                        dataword_out            : out   std_logic_vector;
185 
                                        data_out_valid          : out   std_logic
186 
                                );
187 
        end component;
188 
 
189 
 
190 
        component adc_flowcontrol
191 
                port(   rst                                     : in    std_logic;
192 
                                clk                                     : in    std_logic;
193 
                                program_in                      : in    std_logic;--
194 
                                data_available          : in    std_logic;
195 
                                start_adc                       : in    std_logic;
196 
                                ext_trigger                     : in    std_logic;
197 
                                soft_trigger            : in    std_logic;
198 
                                running                         : out   std_logic;
199 
                                chain_enable            : out   std_logic;
200 
                                sync_init_out           : out   std_logic;--
201 
                                sync_rst_out            : out   std_logic;--
202 
                                rst_addr_gen_out        : out   std_logic;
203 
                                write_count                     : out   std_logic_vector(15 downto 0)
204 
                        );
205 
        end component;
206 
 
207 
        component ringbuffer_feed
208 
                port(   rst                             : in    std_logic;
209 
                                clk                             : in    std_logic;
210 
                                enable                  : in    std_logic;
211 
                                data_in                 : in  std_logic_vector(15 downto 0);
212 
                                address_in              : in  std_logic_vector(31 downto 0);
213 
                                data_out_valid  : out   std_logic;
214 
                                addr_out_valid  : out   std_logic;
215 
                                data_out                        : out std_logic_vector(31 downto 0);
216 
                                address_out             : out std_logic_vector(31 downto 0)
217 
                        );
218 
        end component;
219 
 
220 
        component ddr_address_generator
221 
                port(   clk                                     : in    std_logic;
222 
                                rst                                     : in    std_logic;
223 
                                enable                          : in    std_logic;
224 
                                program                         : in    std_logic;
225 
                                restart                         : in    std_logic;
226 
                                base_address_in : in    std_logic_vector;
227 
                                buffersize_in           : in    std_logic_vector;
228 
                                address_out                     : out   std_logic_vector
229 
                        );
230 
        end component;
231 
 
232 
        component control_feedback
233 
        port(   rst                                             : in    std_logic;
234 
                        ADclk                                           : in    std_logic;
235 
                        uPclk                                           : in    std_logic;
236 
                        cmd_output_select               : in    std_logic_vector(3 downto 0);
237 
                        buffersize                              : in    std_logic_vector(31 downto 0);
238 
                        chain_enable                    : in    std_logic;
239 
                        flowctrl_running                : in    std_logic;
240 
                        output_select_valid     : in    std_logic;
241 
                        fb_output_select                : out   std_logic_vector(3 downto 0);
242 
                        fb_buffersize                   : out   std_logic_vector(31 downto 0);
243 
                        fb_chain_enable         : out   std_logic;
244 
                        fb_running                              : out   std_logic;
245 
                        fb_output_valid         : out   std_logic
246 
                );
247 
        end component;
248 
 
249 
        component async_fifo_16x65
250 
                port (din                               : IN std_logic_VECTOR(64 downto 0);
251 
                                rd_clk                  : IN std_logic;
252 
                                rd_en                           : IN std_logic;
253 
                                rst                             : IN std_logic;
254 
                                wr_clk                  : IN std_logic;
255 
                                wr_en                           : IN std_logic;
256 
                                dout                            : OUT std_logic_VECTOR(64 downto 0);
257 
                                empty                           : OUT std_logic;
258 
                                full                            : OUT std_logic;
259 
                                valid                           : OUT std_logic
260 
                        );
261 
        end component;
262 
 
263 
--type output_mode_type is (none,energytime,traces,both);
264 
 
265 
------------------------------------------------------------------------------------------------------
266 
        signal rst_S                                                    : std_logic := '1';
267 
        signal ADclk_S                                                  : std_logic := '0';
268 
        signal uPclk_S                                                  : std_logic := '0';
269 
        signal enable_S                                         : std_logic := '0';
270 
        signal ADCin_S                                                  : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
271 
        signal s16out_ADCin_S                           : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
272 
        signal invert_data_in_S                         : std_logic := '0';
273 
        signal cmd_baseline_enable_S            : std_logic := '0';
274 
        signal cmd_double_CF_S                          : std_logic := '0';
275 
        signal cmd_program_params_S             : std_logic := '0';
276 
        signal cmd_bypass_mwd_S                         : std_logic := '0';
277 
        signal cmd_bypass_reshape_S             : std_logic := '0';
278 
        signal FE_init_S                                                : std_logic := '0';
279 
        signal FE_reset_S                                               : std_logic := '0';
280 
   signal rst_addr_gen_S                                : std_logic := '0';
281 
 
282 
        signal ext_trigger_S                                    : std_logic := '0';
283 
        signal soft_trigger_S                           : std_logic := '0';
284 
        signal cmd_start_adc_S                          : std_logic := '0';
285 
 
286 
        signal mwd_switch_out_S                         : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
287 
        signal baseline_S                                               : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
288 
        signal clamped_S                                                : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
289 
        signal del_clamp_S                                      : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
290 
        signal CFdev_clamp_S                                    : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
291 
        signal cf_trace_S                                               : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
292 
        signal integral_S                                               : STD_LOGIC_VECTOR(WIDTH downto 0) := (others => '0');
293 
        signal samplenr_S                                               : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
294 
        signal eventnr_S                                                : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
295 
        signal fraction_S                                               : STD_LOGIC_VECTOR(FRACTION_SIZE - 1 downto 0) := (others => '0');
296 
        signal energy_S                                         : STD_LOGIC_VECTOR (WIDTH downto 0) := (others => '0');
297 
 
298 
        signal mwd_out_S                                                : std_logic_vector(WIDTH - 1 downto 0);
299 
        signal baseline_out_S                           : std_logic_vector(WIDTH - 1 downto 0);
300 
        signal clamped_out_S                                    : std_logic_vector(WIDTH - 1 downto 0);
301 
        signal del_clamp_out_S                          : std_logic_vector(WIDTH - 1 downto 0);
302 
        signal CFdev_clamp_out_S                        : std_logic_vector(WIDTH - 1 downto 0);
303 
        signal cf_trace_out_S                           : STD_LOGIC_VECTOR(WIDTH - 1 downto 0);
304 
        signal integral_out_S                           : STD_LOGIC_VECTOR(WIDTH - 1 downto 0);
305 
        signal energy_out_S                                     : STD_LOGIC_VECTOR(WIDTH - 1 downto 0);
306 
 
307 
        signal zeroX_out_S                                      : STD_LOGIC := '0';
308 
        signal event_detect_S                           : STD_LOGIC := '0';
309 
        signal bl_gate_out_S                                    : STD_LOGIC := '0';
310 
        signal ed_gate_out_S                                    : STD_LOGIC := '0';
311 
        signal eventdata_valid_S                        : STD_LOGIC := '0';
312 
 
313 
        signal mux_out_valid_S                          : STD_LOGIC := '0';
314 
        signal mux_data_out_S                           : std_logic_vector(15 downto 0)  := (others => '0');
315 
        signal cmd_output_select_S                      : std_logic_vector(3 downto 0)   := (others => '0');
316 
        signal output_select_dout_S             : std_logic_vector(15 downto 0)  := (others => '0');
317 
        signal output_select_valid_S            : std_logic := '0';
318 
 
319 
        signal data_available_S                         : std_logic := '0';
320 
   signal flowctrl_running_S                    : std_logic := '0';
321 
        signal chain_enable_S                           : STD_LOGIC := '0';
322 
        signal data_dcplfifo_write_en_S : STD_LOGIC := '0';
323 
        signal addr_dcplfifo_write_en_S : STD_LOGIC := '0';
324 
 
325 
--      signal dcplfifo_write_en_S                      : STD_LOGIC := '0';             -- never used. data_dcplfifo_write_en_S is used instead as writes are done every (data)cycle
326 
        signal dcplfifo_empty_S                         : STD_LOGIC := '0';
327 
        signal dcplfifo_read_S                          : STD_LOGIC := '0';
328 
        signal dcplfifo_valid_S                         : STD_LOGIC := '0';
329 
 
330 
        signal decay_correction_S                       : std_logic_vector (decay_correction_in'high downto 0) := (others        => '0');
331 
        signal reshape_correction_S             : std_logic_vector (reshape_correction_in'high downto 0) := (others      => '0');
332 
        signal buffersize_S                                     : std_logic_vector(31 downto 0)  := (others => '0');
333 
        signal address_gen_S                                    : std_logic_vector(31 downto 0)  := (others => '0');
334 
        signal int_signal_threshold_S           : STD_LOGIC_VECTOR(15 downto 0)  := (others => '0');
335 
        signal mwd_pwr_S                                                : STD_LOGIC_VECTOR (7 downto 0)  := conv_std_logic_vector(5,     8);                                                     -- original default value
336 
--      signal fb_window_size_S                         : std_logic_vector(7 downto 0);
337 
        signal cf_pwr_S                                         : STD_LOGIC_VECTOR (7 downto 0)  := conv_std_logic_vector(4,     8);                                                     -- original default value
338 
        signal cf_integral_pwr_S                        : STD_LOGIC_VECTOR (7 downto 0)  := conv_std_logic_vector(4,     8);                                                     -- original default value = (mwd_power - 1)
339 
        signal baseline_pwr_S                           : STD_LOGIC_VECTOR (7 downto 0)  := (others      => '0');
340 
        signal baseline_inhibit_cnt_S           : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(32,    8);                                                     -- original default value
341 
        signal event_inhibit_cnt_S                      : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(16,    8);                                                     -- original default value
342 
 
343 
        signal adc_ram_fifo_data_wr_ce_S        : STD_LOGIC := '0';
344 
--      signal adc_ram_fifo_addr_wr_ce_S        : STD_LOGIC := '0'; -- not used. port is driven from async logic function
345 
 
346 
        signal feed2dcpl_fifo_data_S            : std_logic_vector(31 downto 0) := (others => '0');
347 
        signal feed2dcpl_fifo_addr_S            : std_logic_vector(31 downto 0) := (others => '0');
348 
        signal feed2dcpl_fifo_wide_S            : std_logic_vector(64 downto 0) := (others => '0');
349 
 
350 
        signal dcpl_fifo2rb_wide_S                      : std_logic_vector(64 downto 0) := (others => '0');
351 
        signal dcpl_fifo2rb_data_S                      : std_logic_vector(31 downto 0) := (others => '0');
352 
        signal dcpl_fifo2rb_addr_S                      : std_logic_vector(31 downto 0) := (others => '0');
353 
        signal dcpl_fifo2rb_state_S             : std_logic := '0';
354 
 
355 
        signal fb_output_select_S                       : std_logic_vector(3 downto 0)   := (others => '0');
356 
        signal fb_buffersize_s                          : std_logic_vector(31 downto 0)  := (others => '0');
357 
        signal fb_chain_enable_S                        : std_logic := '0';
358 
        signal fb_flowctrl_running_S            : std_logic := '0';
359 
        signal fb_output_select_valid_S : std_logic := '0';
360 
   signal fb_write_count_S                              : std_logic_vector(15 downto 0) := (others => '0');
361 
 
362 
        signal feedback_bus0_S                          : std_logic_vector(31 downto 0) := (others => '0');
363 
        signal feedback_bus1_S                          : std_logic_vector(31 downto 0) := (others => '0');
364 
 
365 
begin
366 
 
367 
        s16out_ADCin_S                                  <= conv_std_logic_vector(conv_integer(unsigned(ADCin_S(15 downto 1))), WIDTH) when invert_data_in_S = '0'
368 
                                                                                        else conv_std_logic_vector(- conv_integer(unsigned(ADCin_S(15 downto 1))), WIDTH);
369 
 
370 
   FE_inst: MWD_CF_process
371 
                generic map(WIDTH                                                       =>      WIDTH,
372 
                                                MAX_MWD_PWR                                     =>      MAX_MWD_PWR,
373 
                                                MAX_CF_PWR                                      =>      MAX_CF_PWR,
374 
                                                MAX_BASELINE_PWR                                =>      MAX_BASELINE_PWR,
375 
                                                ZEROX_WINDOW_PWR                        =>      ZEROX_WINDOW_PWR,
376 
                                                ZEROX_THRESHOLD_PWR             =>      ZEROX_THRESHOLD_PWR,
377 
                                                INTERP_CYCLES                           =>      INTERP_CYCLES
378 
                                                )
379 
                PORT MAP(       rst                                                     => FE_reset_S,  --rst_S,
380 
                                                clk                                                     => ADclk_S,
381 
                                                enable                                          => enable_S,
382 
                                                program                                         => FE_init_S,
383 
                                                baseline_enable                 => cmd_baseline_enable_S,
384 
                                                double_CF_in                            => cmd_double_CF_S,
385 
                                                bypass_mwd                                      => cmd_bypass_mwd_S,
386 
                                                bypass_reshape                          => cmd_bypass_reshape_S,
387 
                                                data_in                                         => ADCin_S,
388 
                                                invert_data_in                          =>      invert_data_in_S,
389 
                                                decay_correction_in             =>      decay_correction_S,
390 
                                                reshape_correction_in   =>      reshape_correction_S,
391 
                                                threshold_in                            =>      int_signal_threshold_S,
392 
                                                mwd_pwr_in                                      => mwd_pwr_S,
393 
                                                cf_pwr_in                                       =>      cf_pwr_s,
394 
                                                cf_integral_pwr_in              =>      cf_integral_pwr_s,
395 
                                                baseline_pwr_in                 =>      baseline_pwr_S,
396 
                                                baseline_inhibit_cnt_in =>      baseline_inhibit_cnt_S,
397 
                                                event_inhibit_cnt_in            =>      event_inhibit_cnt_S,
398 
                                                mwd_switch_out                          =>      mwd_switch_out_S,
399 
                                                baseline_out                            =>      baseline_S,
400 
                                                clamped_out                                     =>      clamped_S,
401 
                                                del_clamp_out                           =>      del_clamp_S,
402 
                                                CFdev_clamp_out                 =>      CFdev_clamp_S,
403 
                                                cf_trace_out                            =>      cf_trace_S,
404 
                                                integral                                                =>      integral_S,
405 
                                                sample_nr                                       => samplenr_S,
406 
                                                zeroX_out                                       =>      zeroX_out_S,
407 
                                                event_detect_out                        =>      event_detect_S,
408 
                                                bl_gate_out                                     =>      bl_gate_out_S,
409 
                                                ed_gate_out                                     =>      ed_gate_out_S,
410 
                                                eventdata_valid                 =>      eventdata_valid_S,
411 
                                                eventnr_out                                     =>      eventnr_S,
412 
                                                fraction                                                =>      fraction_S,
413 
                                                energy                                          =>      energy_S
414 
                                        );
415 
 
416 
                data_mux : output_mux
417 
                        Port map(rst                                            =>      FE_reset_S,     --rst_S,
418 
                                                clk                                             =>      ADclk_S,
419 
                                                input_valid                             => eventdata_valid_S,
420 
                                                energy_in                               =>      energy_S,
421 
                                                eventnr_in                              =>      eventnr_S,
422 
                                                fraction_in                             =>      fraction_S,
423 
                                                output_valid                    => mux_out_valid_S,
424 
                                                outdata16                               => mux_data_out_S
425 
                                        );
426 
 
427 
                data_select: output_select
428 
                        PORT MAP(clk                                    => ADclk_S,
429 
                                                output_select           => cmd_output_select_S,
430 
                                                indata_in                       => s16out_ADCin_S,
431 
                                                mwd_in                          => mwd_out_S,
432 
                                                baseline_in                     => baseline_out_S,
433 
                                                clamped_in                      => clamped_out_S,
434 
                                                del_clamp_in            => del_clamp_out_S,
435 
                                                CFdev_clamp_in          => CFdev_clamp_out_S,
436 
                                                cf_trace_in                     => cf_trace_out_S,
437 
                                                integral_in             => integral_out_S,
438 
                                                zerox_in                        => zeroX_out_S,
439 
                                                eventdetect_in          => event_detect_S,
440 
                                                gate_in                                 => bl_gate_out_S,
441 
                                                energy_in                       => energy_out_S,
442 
                                                mux_data_in             => mux_data_out_S,
443 
                                                samplenr_in                     =>      samplenr_S,
444 
                                                fraction_in                     =>      fraction_S,
445 
                                                mux_data_valid_in => mux_out_valid_S,
446 
                                                fe_data_valid           => enable_S,
447 
                                                dataword_out            => output_select_dout_S,
448 
                                                data_out_valid  => output_select_valid_S
449 
                                        );
450 
 
451 
----------------------------------------------------------------------------------
452 
--      STOMA
453 
----------------------------------------------------------------------------------
454 
last_buffer_adc_ram_fifo_wr_addr(15 downto 0) <= output_select_dout_S;
455 
----------------------------------------------------------------------------------
456 
 
457 
                FE_flow_control : adc_flowcontrol
458 
                        port map(rst                                    =>      rst_S,
459 
                                                clk                                     =>      ADclk_S,
460 
                                                program_in                      =>      cmd_program_params_S,
461 
                                                data_available          =>      data_available_S,
462 
                                                start_adc                       =>      cmd_start_adc_S,
463 
                                                ext_trigger                     =>      ext_trigger_S,
464 
                                                soft_trigger            =>      soft_trigger_S,
465 
                                                running                         => flowctrl_running_S,
466 
                                                chain_enable            =>      chain_enable_S,
467 
                                                sync_init_out           => FE_init_S,
468 
                                                sync_rst_out            =>      FE_reset_S,
469 
                                                rst_addr_gen_out        => rst_addr_gen_S,
470 
                                                write_count                     => fb_write_count_S
471 
                                        );
472 
 
473 
                FE_ringbuf_feed : ringbuffer_feed
474 
                        port map(rst                                    => FE_reset_S,
475 
                                                clk                                     => ADclk_S,
476 
                                                enable                          => chain_enable_S,
477 
                                                data_in                         => output_select_dout_S,
478 
                                                address_in                      => address_gen_S,
479 
                                                data_out_valid          => data_dcplfifo_write_en_S,            -- !!
480 
                                                addr_out_valid          => addr_dcplfifo_write_en_S,            --!!
481 
                                                data_out                                => feed2dcpl_fifo_data_S,
482 
                                                address_out                     => feed2dcpl_fifo_addr_S
483 
                                        );
484 
 
485 
                FE_vme_addr_gen: ddr_address_generator
486 
                        port map(clk                                    => ADclk_S,
487 
                                                rst                                     => FE_reset_S,
488 
                                                enable                          => chain_enable_S,
489 
                                                program                         => FE_init_S,
490 
                                                restart                         => rst_addr_gen_S,
491 
                                                base_address_in => BASE_ADDR,
492 
                                                buffersize_in           => buffersize_S,
493 
                                                address_out                     => address_gen_S
494 
                                        );
495 
 
496 
                FE_control_UI : control_feedback
497 
                        port map(rst                                            => FE_reset_S,
498 
                                                ADclk                                           => ADclk_S,
499 
                                                uPclk                                           => uPclk_S,
500 
                                                cmd_output_select               => cmd_output_select,
501 
                                                buffersize                              => buffersize_S,
502 
                                                chain_enable                    => chain_enable_S,
503 
                                                flowctrl_running                => flowctrl_running_S,
504 
                                                output_select_valid     => output_select_valid_S,
505 
                                                fb_output_select                => fb_output_select_S,
506 
                                                fb_buffersize                   => fb_buffersize_S,
507 
                                                fb_chain_enable         => fb_chain_enable_S,
508 
                                                fb_running                              => fb_flowctrl_running_S,
509 
                                                fb_output_valid         => fb_output_select_valid_S
510 
                                        );
511 
 
512 
 
513 
                adc2uP_fifo     : async_fifo_16x65      -- clock domain decoupling buffer for VME/ringbufferdata
514 
                        port map(rst                            => FE_reset_S,
515 
                                                rd_clk                  => uPclk_S,
516 
                                                rd_en                           => dcplfifo_read_S,
517 
                                                din                             => feed2dcpl_fifo_wide_S,
518 
                                                wr_clk                  => ADclk_S,
519 
                                                wr_en                           => data_dcplfifo_write_en_S,    --
520 
                                                dout                            => dcpl_fifo2rb_wide_S,
521 
                                                empty                           => dcplfifo_empty_S,
522 
                                                full                            => open,
523 
                                                valid                           => dcplfifo_valid_S
524 
                                        );
525 
 
526 
 
527 
--- connect the wires !!------------------------------------------------------------------------------
528 
        dcplfifo_read_S                                 <= not dcplfifo_empty_S;
529 
 
530 
                feed2dcpl_fifo_wide_S(31 downto 0)       <= feed2dcpl_fifo_data_S;
531 
                feed2dcpl_fifo_wide_S(63 downto 32)     <= feed2dcpl_fifo_addr_S;
532 
                feed2dcpl_fifo_wide_S(64)                               <= addr_dcplfifo_write_en_S;
533 
 
534 
                dcpl_fifo2rb_data_S                                             <=      dcpl_fifo2rb_wide_S(31 downto 0);
535 
                dcpl_fifo2rb_addr_S                                             <=      dcpl_fifo2rb_wide_S(63 downto 32);
536 
                dcpl_fifo2rb_state_S                                            <=      dcpl_fifo2rb_wide_S(64);
537 
 
538 
--- now sync the read/write process with wme clock---------------------
539 
        vme_interface_sync : process(uPclk_S)
540 
        begin
541 
                if rising_edge(uPclk_S) then
542 
                        adc_ram_fifo_data_wr_ce_S                               <= dcplfifo_read_S;                     --data_dcplfifo_read_S;
543 
                        if (dcplfifo_valid_S = '1') then
544 
                                adc_ram_fifo_data_wr_ce         <= adc_ram_fifo_data_wr_ce_S;
545 
                                adc_ram_fifo_addr_wr_ce         <= dcpl_fifo2rb_state_S and adc_ram_fifo_data_wr_ce_S;  -- comes from fifo and is allready delayed 1 extra
546 
                        else
547 
                                adc_ram_fifo_data_wr_ce         <= '0';
548 
                                adc_ram_fifo_addr_wr_ce         <= '0';
549 
                        end if;
550 
 
551 
                        adc_ram_fifo_data_wr_data               <= dcpl_fifo2rb_data_S;
552 
                        adc_ram_fifo_address                            <= dcpl_fifo2rb_addr_S;
553 
                end if;
554 
        end process;
555 
 
556 
 
557 
 
558 
        ADclk_S                                                         <=      ADC_CLK;
559 
        uPclk_S                                                         <=      uP_CLK;
560 
 
561 
        data_available_S                                        <= output_select_valid_S;
562 
        decay_correction_S                              <=      decay_correction_in;
563 
        reshape_correction_S                            <=      reshape_correction_in;
564 
        int_signal_threshold_S                  <=      int_signal_threshold_in;
565 
        mwd_pwr_S                                                       <= mwd_pwr_in;
566 
        cf_pwr_s                                                                <= cf_pwr_in;
567 
        cf_integral_pwr_s                                       <= cf_integral_pwr_in;
568 
        baseline_pwr_S                                          <=      baseline_pwr_in;
569 
 
570 
        baseline_inhibit_cnt_S                  <=      baseline_inhibit_cnt_in;
571 
        event_inhibit_cnt_S                             <=      event_inhibit_cnt_in;
572 
 
573 
        fb_flowctrl_running                             <= flowctrl_running_S;
574 
        fb_chain_enable                                 <= fb_chain_enable_S;
575 
 
576 
        mwd_out_S(15 downto 0)                   <= mwd_switch_out_S(16 downto 1);
577 
        integral_out_S  (15 downto 0)    <= integral_S(16 downto 1);
578 
        energy_out_S(15 downto 0)                <= energy_S(16 downto 1);
579 
        del_clamp_out_S(15 downto 0)     <= del_clamp_S(16 downto 1);
580 
        clamped_out_S(15 downto 0)               <= clamped_S(16 downto 1);
581 
        cf_trace_out_S(15 downto 0)      <= cf_trace_S(16 downto 1);
582 
        baseline_out_S(15 downto 0)      <= baseline_S(16 downto 1);
583 
        CFdev_clamp_out_S(15 downto 0)<= CFdev_clamp_S(16 downto 1);
584 
 
585 
        feedback_bus0_S                                 <= fb_buffersize_S;
586 
        feedback_bus1_S(3 downto 0)      <= fb_output_select_S;
587 
        feedback_bus1_S(9 downto 4)     <= (others => '0');
588 
        feedback_bus1_S(10)                             <= fb_chain_enable_S;
589 
        feedback_bus1_S(11)                             <= fb_flowctrl_running_S;
590 
        feedback_bus1_S(12)                             <= fb_output_select_valid_S;
591 
        feedback_bus1_S(15 downto 13)   <= (others => '0');
592 
        feedback_bus1_S(23 downto 16)   <= (others => '0');      --fb_window_size_S;
593 
        feedback_bus1_S(31 downto 24)   <= cf_pwr_S;
594 
 
595 
 
596 
        feedback_port0                                          <= feedback_bus0_S;
597 
        feedback_port1                                          <= feedback_bus1_S;
598 
        feedback_port2                                          <= fb_write_count_S;
599 
        feedback_port3                                          <= dcpl_fifo2rb_addr_S;
600 
 
601 
        last_buffer_adc_ram_fifo_wr_addr(31 downto 16)  <= (others => '0'); -- was not driven... to avoid warning 1305
602 
 
603 
--      data_dcplfifo_read_S            <= not data_dcplfifo_empty_S;
604 
--      addr_dcplfifo_read_S            <= not addr_dcplfifo_empty_S;
605 
 
606 
        ADC2vme_interface_sync : process(ADclk_S)
607 
        begin
608 
                if rising_edge(ADclk_S) then
609 
                -- input sync
610 
                        rst_S                                                                   <=      Reset;
611 
                        ADCin_S                                                         <=      ADCin;
612 
 
613 
                        invert_data_in_S                                        <= invert_data_in;
614 
                        ext_trigger_S                                           <= externaltrigger;
615 
                        soft_trigger_S                                          <= softwaretrigger;
616 
 
617 
                        cmd_output_select_S                             <=      cmd_output_select;
618 
                        cmd_start_adc_S                                 <= cmd_start_adc;
619 
                        cmd_baseline_enable_S                   <= cmd_baseline_enable;
620 
                        cmd_double_CF_S                                 <= cmd_double_CF;
621 
                        enable_S                                                                <= cmd_enableFE;
622 
                        cmd_program_params_S                            <= cmd_program_params;
623 
                        cmd_bypass_mwd_S                                        <=      cmd_bypass_mwd;
624 
                        cmd_bypass_reshape_S                            <=      cmd_bypass_reshape;
625 
 
626 
                        buffersize_S                                            <= buffer_size;                 --      Aanpassen breedte van buffersize voor ddr_address_gen
627 
 
628 
                end if;
629 
        end process;
630 
 
631 
end behaviour;

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