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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : SISO_add_a
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-- Description : Signed In Signed Out Adder Asynchronous
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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entity SISO_add_a is
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Port (dataa : in STD_LOGIC_VECTOR;
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datab : in STD_LOGIC_VECTOR;
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result : out STD_LOGIC_VECTOR
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);
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end SISO_add_a;
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architecture Behavioral of SISO_add_a is
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constant WIDTH : natural := dataa'length;
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constant MAXVAL : integer := 2**(WIDTH - 1) - 1;
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constant MINVAL : integer := - 2**(WIDTH - 1);
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signal a_in_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal b_in_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal sum_S : std_logic_vector(WIDTH downto 0) := (others => '0');
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signal status_S : std_logic_vector(1 downto 0) := (others => '0');
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-- signal overflow_S : std_logic := '0';
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begin
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a_in_S <= dataa(dataa'high) & dataa;
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b_in_S <= datab(datab'high) & datab;
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sum_S <= conv_std_logic_vector((conv_integer(signed(a_in_S)) + conv_integer(signed(b_in_S))), WIDTH + 1);
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status_S <= sum_S(WIDTH) & sum_S(WIDTH - 1);
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-- overflow_S <= sum_S(WIDTH) XOR sum_S(WIDTH - 1);
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result <= conv_std_logic_vector(MAXVAL, WIDTH) when (status_S = b"01") else
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conv_std_logic_vector(MINVAL, WIDTH) when (status_S = b"10") else
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conv_std_logic_vector(conv_integer(signed(sum_S)), WIDTH);
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end Behavioral;
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