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panda_emc |
-----------------------------------------------------------------------------------------------
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : adc_flow_control.vhd
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-- Description : The SIS3301/2 has several options for external triggering and turn on/off
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-- It also has some requirements concerning (vme-)memory use, the most
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-- important of which is that memory can only be written 2x64-bit chunks/words
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-- These 64-bit chunks are written into a 32bit-wide data-fifo accompanied by
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-- 32bit addresses written into a address-fifo. These write-actions have to
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-- be done in groups of 4, in which each cycle contains a data-write-cycle
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-- and the 2nd and 4th contain a address-write cycle. If this rule is not
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-- observed, the interface fpga get screwed-up and the board has to be reset.
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-- The flow-state-machine in this module takes care of this in that is keeps
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-- resets pending until the proper moment and adds dummy-writecycles when
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-- you run out of data unexcpetedly.
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--
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity adc_flowcontrol is
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port( rst : in std_logic;
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clk : in std_logic;
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program_in : in std_logic;
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data_available : in std_logic;
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start_adc : in std_logic;
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ext_trigger : in std_logic;
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soft_trigger : in std_logic;
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running : out std_logic;
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chain_enable : out std_logic;
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sync_init_out : out std_logic;
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sync_rst_out : out std_logic;
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rst_addr_gen_out : out std_logic;
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write_count : out std_logic_vector(15 downto 0)
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);
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end adc_flowcontrol;
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architecture Behavioral of adc_flowcontrol is
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type flow_state_type is (reset_state, program_state, idle_state, start_state, word_a, word_b, word_c, word_d, no_data);
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signal flow_state_S : flow_state_type := idle_state;
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signal rst_S : std_logic := '1';
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signal old_rst_S : std_logic := '1';
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signal rst_pulse_S : std_logic := '1';
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signal rst_pending_S : std_logic := '0';
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signal rst_out_S : std_logic := '0';
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signal clk_S : std_logic := '0';
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signal program_in_S : std_logic := '0';
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signal old_program_in_S : std_logic := '0';
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signal program_pulse_S : std_logic := '1';
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signal program_out_S : std_logic := '0';
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signal data_available_S : std_logic := '0';
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signal start_adc_S : std_logic := '0';
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signal old_start_adc_S : std_logic := '0';
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signal ext_trigger_S : std_logic := '0';
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signal old_ext_trigger_S : std_logic := '0';
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signal soft_trigger_S : std_logic := '0';
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signal old_soft_trigger_S : std_logic := '0';
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signal trigger_pulse_S : std_logic := '0';
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signal start_pulse_S : std_logic := '0';
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signal terminate_S : std_logic := '0';
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signal chain_enable_S : std_logic := '0';
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signal rst_addr_gen_S : std_logic := '0';
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signal running_S : std_logic := '0';
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signal write_count_S : std_logic_vector(15 downto 0) := (others => '0');
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begin
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clk_S <= clk;
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rst_S <= rst;
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program_in_S <= program_in;
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data_available_S <= data_available;
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start_adc_S <= start_adc;
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ext_trigger_S <= ext_trigger;
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soft_trigger_S <= soft_trigger;
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chain_enable <= chain_enable_S;
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running <= running_S;
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write_count <= write_count_S;
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sync_init_out <= program_out_S;
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sync_rst_out <= rst_out_S;
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rst_addr_gen_out <= rst_addr_gen_S;
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fsm_flow_state_control : process(clk_S, rst, rst_S, program_in, program_in_S)
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begin
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if rising_edge(clk_S) then
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case flow_state_S is
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when idle_state =>
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if (rst = '1') or (rst_pulse_S = '1') or (program_pulse_S = '1') then
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flow_state_S <= reset_state;
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elsif (start_pulse_S = '1') then
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flow_state_S <= start_state;
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write_count_S <= (others => '0');
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else
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flow_state_S <= flow_state_S;
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end if;
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when no_data =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') then
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flow_state_S <= reset_state;
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elsif (trigger_pulse_S) = '1' then
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terminate_S <= '0';
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flow_state_S <= idle_state;
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elsif (data_available_S = '1') then
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flow_state_S <= word_a;
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else
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flow_state_S <= flow_state_S;
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end if;
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when reset_state =>
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if (rst = '0') then
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rst_pending_S <= '0';
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flow_state_S <= program_state;
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else
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flow_state_S <= no_data;
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end if;
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when program_state =>
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if ((rst = '1')) then
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flow_state_S <= reset_state;
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else
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flow_state_S <= idle_state;
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end if;
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when start_state =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') then
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flow_state_S <= reset_state;
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elsif (data_available_S = '1') then
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flow_state_S <= word_a;
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else
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flow_state_S <= no_data;
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end if;
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when word_a =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') then
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rst_pending_S <= '1';
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elsif (trigger_pulse_S) = '1' then
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terminate_S <= '1';
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end if;
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flow_state_S <= word_b;
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write_count_S <= write_count_S + 1;
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when word_b =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') then
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rst_pending_S <= '1';
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elsif (trigger_pulse_S) = '1' then
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terminate_S <= '1';
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end if;
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flow_state_S <= word_c;
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write_count_S <= write_count_S + 1;
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when word_c =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') then
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rst_pending_S <= '1';
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elsif (trigger_pulse_S) = '1' then
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terminate_S <= '1';
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end if;
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flow_state_S <= word_d;
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write_count_S <= write_count_S + 1;
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when word_d =>
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if (rst_pulse_S = '1') or (program_pulse_S = '1') or (rst_pending_S = '1') then
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rst_pending_S <= '0';
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flow_state_S <= reset_state;
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elsif (terminate_S = '1') or (trigger_pulse_S = '1') then
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terminate_S <= '0';
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flow_state_S <= idle_state;
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elsif (data_available_S = '0') then
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flow_state_S <= no_data;
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else
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flow_state_S <= word_a; -- running_S and chain_enable are allready '1'
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end if;
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write_count_S <= write_count_S + 1;
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end case;
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end if;
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end process;
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output_signals : process(flow_state_S)
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begin
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case flow_state_S is
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when idle_state =>
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chain_enable_S <= '0';
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running_S <= '0';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when no_data =>
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chain_enable_S <= '0';
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running_S <= '1';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when reset_state =>
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chain_enable_S <= '0';
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running_S <= '0';
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rst_out_S <= '1';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when program_state =>
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chain_enable_S <= '0';
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running_S <= '0';
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rst_out_S <= '0';
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program_out_S <= '1';
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rst_addr_gen_S <= '0';
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when start_state =>
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chain_enable_S <= '0';
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running_S <= '0';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '1';
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when word_a =>
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chain_enable_S <= '1';
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running_S <= '1';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when word_b =>
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chain_enable_S <= '1';
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running_S <= '1';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when word_c =>
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chain_enable_S <= '1';
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running_S <= '1';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when word_d =>
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chain_enable_S <= '1';
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running_S <= '1';
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rst_out_S <= '0';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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when others =>
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chain_enable_S <= '0';
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running_S <= '0';
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rst_out_S <= '1';
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program_out_S <= '0';
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rst_addr_gen_S <= '0';
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end case;
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end process;
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fsm_edge_detect : process(clk_S)
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begin
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if rising_edge(clk_S) then
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old_rst_S <= rst_S;
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old_program_in_S <= program_in_S;
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old_start_adc_S <= start_adc_S;
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old_ext_trigger_S <= ext_trigger_S;
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old_soft_trigger_S <= soft_trigger_S;
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if (old_rst_S = '0' and rst_S = '1') then
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rst_pulse_S <= '1';
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else
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rst_pulse_S <= '0';
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end if;
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if (old_program_in_S = '0' and program_in_S = '1') then
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program_pulse_S <= '1';
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else
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program_pulse_S <= '0';
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end if;
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if (old_start_adc_S = '0' and start_adc_S = '1') then
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start_pulse_S <= '1';
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else
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start_pulse_S <= '0';
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end if;
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if ((old_ext_trigger_S = '0' and ext_trigger_S = '1') or (old_soft_trigger_S = '0' and soft_trigger_S = '1')) then
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trigger_pulse_S <= '1';
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else
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trigger_pulse_S <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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