Subversion Repositories pulse_processing_algorithm

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--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

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-- Company:                     KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author:                      P.J.J. Lemmens

-- Design Name: Feature Extraction

-- Module Name: baseline_follower.vhd

-- Description: Combination of data-delay and programmable-moving_average

--                                              Because you normally don't want to use event-data for baseline calculation, the

--                                              datacollection is inhibited when event occurs (gated). In order to overcome 

--                                              latency of event-detection the baseline-follower has a history-buffer. This

--                                              buffer has a programmable size. 

--                                              The size of the baseline-moving average is programmable as a power of 2.

--                                              

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity baseline_follower is

        generic(        WINDOW_PWR                      :       natural := 1;           -- defines the maximum window in which event disturbance is seen

                                MAX_BASELINE_PWR        :       natural := 1            -- size of the baseline window

                                );

        Port (  rst                                     : in    STD_LOGIC;

                                clk                                     : in    STD_LOGIC;

                                enable                          : in    STD_LOGIC;

                                program                         : in    STD_LOGIC;

                                gate                                    : in    STD_LOGIC;

                                baseline_pwr_in : in    STD_LOGIC_VECTOR(7 downto 0);

                                buffer_size_in          : in    STD_LOGIC_VECTOR(7 downto 0);    -- 

                                data_in                         : in    STD_LOGIC_VECTOR;

                                data_out                                : out   STD_LOGIC_VECTOR;

                                buffer_data_valid       : out STD_LOGIC

                        );

end baseline_follower;

architecture Behavioral of baseline_follower is

        constant        WIDTH                           : natural := data_in'length;

        constant        B_WIDTH                 : natural := WIDTH + MAX_BASELINE_PWR;                  -- extended width for MAX_BASELINE_PWR

--      constant        BASELINE_SIZE   : natural := 2**BASELINE_PWR;                   -- extended width for BASELINE_PWR

        constant        M2_PWR                  : natural := WINDOW_PWR + 1;

        constant        M2                              : natural := 2**M2_PWR;                                         -- M is the MWD window-size; M2= 2*M

        component progdelay_pipeline

                generic(        RAM_SIZE_PWR    : natural;

                                        FLEX_RAM_STYLE  : string

                                );

                port (rst                       : IN    STD_LOGIC ;

                                clk                     : IN    STD_LOGIC ;

                                enable          : IN  STD_LOGIC := '1';

                                program         : in  STD_LOGIC;

                                delay_in                : in    STD_LOGIC_VECTOR;

                                data_in         : IN    STD_LOGIC_VECTOR;

                                data_out                : OUT STD_LOGIC_VECTOR;

                                data_valid      : OUT   STD_LOGIC

                        );

        end component;

        component moving_average_programmable

                generic(MEM_PWR         : natural);

                port (rst                               : in    std_logic;

                                clk                             : in    std_logic;

                                enable                  : in  std_logic;

                                program                 : in  std_logic;

                                avg_pwr_in              : in  std_logic_vector(7 downto 0);

                                data_in                 : in  std_logic_vector;

                                data_out                        : out std_logic_vector

                        );

        end component;

--      component moving_average

--              generic(        WINDOW_PWR      :       natural;

--                                      WINDOW_SIZE     :       natural

--                              );

--              Port (  rst                     : IN    STD_LOGIC ;

--                                      clk                     : IN    STD_LOGIC ;

--                                      enable          : in    STD_LOGIC := '1';

--                                      data_in         : in    STD_LOGIC_VECTOR;

--                                      data_out        : out   STD_LOGIC_VECTOR

--                              );

--      end component;

-----------------------------------------------------------------------

        signal rst_S                            : std_logic := '1';

        signal clk_S                            : std_logic := '0';

        signal enable_S                         : std_logic := '0';

        signal program_S                        : std_logic := '0';

        signal data_in_S                        : std_logic_vector (WIDTH - 1 downto 0) := (others => '0');

        signal M2del_data_S             : std_logic_vector (WIDTH - 1 downto 0) := (others       => '0');

        signal baseline_S                       : STD_LOGIC_VECTOR (WIDTH - 1 downto 0) := (others       => '0');

        signal baseline_gate_S  : STD_LOGIC := '0';

        signal buffer_size_S            : STD_LOGIC_VECTOR (7 downto 0)                   := (others     => '0');

        signal baseline_pwr_S   : STD_LOGIC_VECTOR (7 downto 0)                   := (others     => '0');

        signal deldata_valid_S  : STD_LOGIC := '0';

-----------------------------------------------------------------------

begin

-- M2 pipe is to prevent an event (pulse) from poluting the baseline

        M2_pipe : progdelay_pipeline

                        generic map(RAM_SIZE_PWR        =>      M2_PWR,

                                                        FLEX_RAM_STYLE  => "distributed"

                                                )

                        PORT MAP(rst                                    => rst_S,

                                                clk                                     => clk_S,

                                                enable                          => enable_S,                                            -- not gated !! just keep the record.

                                                program                         => program_S,

                                                delay_in                                => buffer_size_S,                                       -- data delay is equal to the inhibit period

                                                data_in                         => data_in_S,

                                                data_out                        => M2del_data_S,

                                                data_valid                      =>      deldata_valid_S                         -- Tells you when the pipe has been filled an is enabled

                                        );

--      baseline_smooth : moving_average

--              generic map(WINDOW_PWR  =>      BASELINE_PWR,

--                                              WINDOW_SIZE     =>      BASELINE_SIZE

--                                              )

--              port map (      rst             => rst_S,

--                                              clk             =>      clk_S,

--                                              enable  =>      baseline_gate_S,

--                                              data_in         =>      M2del_data_S,

--                                              data_out        => baseline_S

--                                      ); 

        baseline_smooth : moving_average_programmable

                generic map(MEM_PWR     =>      MAX_BASELINE_PWR)

                port map(       rst                     => rst_S,

                                                clk                     =>      clk_S,

                                                enable          =>      baseline_gate_S,

                                                program         => program_S,

                                                avg_pwr_in      => baseline_pwr_S,

                                                data_in         =>      M2del_data_S,

                                                data_out                => baseline_S

                                        );

                -- hook-up the external ports to the internal signals -----------------

                rst_S                                   <=      rst;

                clk_S                                   <=      clk;

                enable_S                        <= enable;

                program_S                       <= program;

                baseline_gate_S <=      deldata_valid_S and gate;

                baseline_pwr_S          <=      baseline_pwr_in;

                buffer_size_S           <= buffer_size_in;

                data_in_S                       <=      data_in;

                data_out                                <=      baseline_S;

                buffer_data_valid       <=      deldata_valid_S;

end Behavioral;