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[/] [pulse_processing_algorithm/] [controller_ddr2_iobs.vhd] - Blame information for rev 2

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--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--  XAPP 253 - Synthesizable DDR SDRAM Controller
--
--*******************************************************************************
--
--  File name :       controller.vhd
--
--  Description :     
--                    Main DDR SDRAM controller block. This includes the following
--                    features:
--                    - The controller state machine that controls the 
--                    initialization process upon power up, as well as the 
--                    read, write, and refresh commands. 
--                    - Accepts and decodes the user commands.
--                    - Generates the address and Bank address signals
--                    - Generates control signals for other modules, including
--                    the control signals for the dqs_en block.
--
-- 
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
 
entity controller_ddr2_iobs is
port(
    clk0             : in std_logic;
    clk180           : in std_logic;
    ddr_rasb_cntrl   : in std_logic;
    ddr_casb_cntrl   : in std_logic;
    ddr_web_cntrl    : in std_logic;
    ddr_cke_cntrl    : in std_logic;
    ddr_csb_cntrl    : in std_logic;
    ddr_ODT_cntrl    : in std_logic;
    ddr_address_cntrl: in std_logic_vector(12 downto 0);
    ddr_ba_cntrl     : in std_logic_vector(1 downto 0);
    rst_dqs_div_int  : in std_logic;
    ddr_rasb         : out std_logic;
    ddr_ODT0         : out std_logic;
    ddr_casb         : out std_logic;
    ddr_web          : out std_logic;
    ddr_ba           : out std_logic_vector(1 downto 0);
    ddr_address      : out std_logic_vector(15 downto 0);
    ddr_cke          : out std_logic;
    ddr_csb          : out std_logic;
    rst_dqs_div      : out std_logic;
   rst_dqs_div_iob   : inout std_logic
--    rst_dqs_div_in   : in std_logic;
--    rst_dqs_div_out  : out std_logic
 
);
end controller_ddr2_iobs;
 
 
architecture arc_controller_ddr2_iobs of controller_ddr2_iobs is
 
attribute xc_props : string;
attribute syn_keep : boolean;
 
 
component IBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component OBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component IBUF
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
component OBUF
port (
       I  : in std_logic;
       O  : out std_logic);
end component;
 
 
component FD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;
 
component OFD
   port(
      Q                              :  out   STD_LOGIC;
      D                              :  in    STD_LOGIC;
      C                              :  in    STD_LOGIC);
end component;
 
--component OBUFT
--port(
--      I : in std_logic;
--      T : in std_logic;
--      O : out std_logic);
--end component;
 
 
---- **************************************************
---- iob attributes for instantiated FD components
---- **************************************************
 
 
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
--signal rst_dqs_div_out     : std_logic;
 
 
--signal GND        : std_logic;
--signal ddr_web_q  : std_logic;
--signal ddr_rasb_q : std_logic;
--signal ddr_casb_q : std_logic;
 
--signal ddr_ba_q : std_logic_vector(1 downto 0);
--signal ddr_address_q : std_logic_vector(15 downto 0);
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
 
 
 
--attribute xc_props of iob_web:  label is "IOB=TRUE";
--attribute xc_props of iob_rasb: label is "IOB=TRUE";
--attribute xc_props of iob_casb: label is "IOB=TRUE";
 
 
--attribute xc_props of iob_addr0: label is "IOB=TRUE";
--attribute xc_props of iob_addr1: label is "IOB=TRUE";
--attribute xc_props of iob_addr2: label is "IOB=TRUE";
--attribute xc_props of iob_addr3: label is "IOB=TRUE";
--attribute xc_props of iob_addr4: label is "IOB=TRUE";
--attribute xc_props of iob_addr5: label is "IOB=TRUE";
--attribute xc_props of iob_addr6: label is "IOB=TRUE";
--attribute xc_props of iob_addr7: label is "IOB=TRUE";
--attribute xc_props of iob_addr8: label is "IOB=TRUE";
--attribute xc_props of iob_addr9: label is "IOB=TRUE";
--attribute xc_props of iob_addr10: label is "IOB=TRUE";
--attribute xc_props of iob_addr11: label is "IOB=TRUE";
--attribute xc_props of iob_addr12: label is "IOB=TRUE";
 
--attribute xc_props of iob_ba0: label is "IOB=TRUE";
--attribute xc_props of iob_ba1: label is "IOB=TRUE";
 
begin
 
--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL
--GND <= '0';
 
 
---- ******************************************* ----
----  Includes the instantiation of FD for cntrl ----
----            signals                          ----
---- ******************************************* ----
 
iob_web : OFD port map (
                         Q    => ddr_web,
                         D    => ddr_web_cntrl,
                         C    => clk180);
 
iob_rasb : OFD port map (
                         Q    => ddr_rasb,
                         D    => ddr_rasb_cntrl,
                         C    => clk180);
 
iob_casb : OFD port map (
                         Q    => ddr_casb,
                         D    => ddr_casb_cntrl,
                         C    => clk180);
 
 
--iob_casb : FD port map (
--                         Q    => ddr_casb_q,
--                         D    => ddr_casb_cntrl,
--                         C    => clk180);                                                  
 
 
---- ************************************* ----
----  Output buffers for control signals   ----
---- ************************************* ----
 
--r0 : OBUF port map (
--                     I => ddr_web_q,
--                     O => ddr_web);
 
--r1 : OBUF port map (
--                     I => ddr_rasb_q,
--                     O => ddr_rasb);
 
--r2 : OBUF port map (
--                     I => ddr_casb_q,
--                     O => ddr_casb);
 
r3 : OBUF port map (
                     I => ddr_cke_cntrl,
                     O => ddr_cke);
 
r4 : OBUF port map (
                     I => ddr_csb_cntrl,
                     O => ddr_csb);
 
r40 : OBUF port map (
                     I => ddr_ODT_cntrl,
                     O => ddr_ODT0);
 
 
 
---- ************************************* ----
----  Output buffers for address signals   ----
---- ************************************* ----
 
 
 
 
--iob_addr0 : FD port map (
--                         Q    => ddr_address_q(0),
--                         D    => ddr_address_cntrl(0),
--                         C    => clk180);
 
iob_addr0 : OFD port map (
                         Q    => ddr_address(0),
                         D    => ddr_address_cntrl(0),
                         C    => clk180);
 
iob_addr1 : OFD port map (
                         Q    => ddr_address(1),
                         D    => ddr_address_cntrl(1),
                         C    => clk180);
 
iob_addr2 : OFD port map (
                         Q    => ddr_address(2),
                         D    => ddr_address_cntrl(2),
                         C    => clk180);
 
iob_addr3 : OFD port map (
                         Q    => ddr_address(3),
                         D    => ddr_address_cntrl(3),
                         C    => clk180);
 
iob_addr4 : OFD port map (
                         Q    => ddr_address(4),
                         D    => ddr_address_cntrl(4),
                         C    => clk180);
 
iob_addr5 : OFD port map (
                         Q    => ddr_address(5),
                         D    => ddr_address_cntrl(5),
                         C    => clk180);
 
iob_addr6 : OFD port map (
                         Q    => ddr_address(6),
                         D    => ddr_address_cntrl(6),
                         C    => clk180);
 
iob_addr7 : OFD port map (
                         Q    => ddr_address(7),
                         D    => ddr_address_cntrl(7),
                         C    => clk180);
 
iob_addr8 : OFD port map (
                         Q    => ddr_address(8),
                         D    => ddr_address_cntrl(8),
                         C    => clk180);
 
iob_addr9 : OFD port map (
                         Q    => ddr_address(9),
                         D    => ddr_address_cntrl(9),
                         C    => clk180);
 
iob_addr10 : OFD port map (
                         Q    => ddr_address(10),
                         D    => ddr_address_cntrl(10),
                         C    => clk180);
 
iob_addr11 : OFD port map (
                         Q    => ddr_address(11),
                         D    => ddr_address_cntrl(11),
                         C    => clk180);
 
iob_addr12 : OFD port map (
                         Q    => ddr_address(12),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
iob_addr13 : OFD port map (
                         Q    => ddr_address(13),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
iob_addr14 : OFD port map (
                         Q    => ddr_address(14),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
 
iob_addr15 : OFD port map (
                         Q    => ddr_address(15),
                         D    => ddr_address_cntrl(12),
                         C    => clk180);
 
 
 
--r5 : OBUF port map (
--                     I => ddr_address_q(0),
--                     O => ddr_address(0));
 
--r6 : OBUF port map (
--                     I => ddr_address_q(1),
--                     O => ddr_address(1));
 
--r7 : OBUF port map (
--                     I => ddr_address_q(2),
--                     O => ddr_address(2));
 
--r8 : OBUF port map (
--                     I => ddr_address_q(3),
--                     O => ddr_address(3));
 
--r9 : OBUF port map (
--                     I => ddr_address_q(4),
--                     O => ddr_address(4));
 
--r10 : OBUF port map (
--                     I => ddr_address_q(5),
--                     O => ddr_address(5));
 
--r11 : OBUF port map (
--                     I => ddr_address_q(6),
--                     O => ddr_address(6));
 
--r12 : OBUF port map (
--                     I => ddr_address_q(7),
--                     O => ddr_address(7));
 
--r13 : OBUF port map (
--                     I => ddr_address_q(8),
--                     O => ddr_address(8));
 
--r14 : OBUF port map (
--                     I => ddr_address_q(9),
--                     O => ddr_address(9));
 
--r15 : OBUF port map (
--                     I => ddr_address_q(10),
--                     O => ddr_address(10));
 
--r16 : OBUF port map (
--                     I => ddr_address_q(11),
--                     O => ddr_address(11));
 
--r17 : OBUF port map (
 --                    I => ddr_address_q(12),
 --                    O => ddr_address(12));
 
 
 
 
iob_ba0 : FD port map (
                         Q    => ddr_ba(0),
                         D    => ddr_ba_cntrl(0),
                         C    => clk180);
 
iob_ba1 : FD port map (
                         Q    => ddr_ba(1),
                         D    => ddr_ba_cntrl(1),
                         C    => clk180);
 
--r18 : OBUF port map (
--                     I => ddr_ba_q(0),
--                     O => ddr_ba(0));
 
--r19 : OBUF port map (
--                     I => ddr_ba_q(1),
--                     O => ddr_ba(1));
 
 
 
---rst_iob_inbuf  :  IBUF port map                        
rst_iob_inbuf  :  IBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_iob,
                              O  => rst_dqs_div);
 
 
---rst_iob_outbuf  :  OBUF port map                            
rst_iob_outbuf  :  OBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_int,
--                              O  => rst_dqs_div_out);
                              O  => rst_dqs_div_iob);
 
 
 
 
 
 
--U3 : OBUFT  port map ( I => rst_dqs_div_out, 
--                       T => '0' ,
--                       O => rst_dqs_div_iob);
 
 
 
 
 
end arc_controller_ddr2_iobs;
 
 
 
 
 
 
 

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Subversion Repositories pulse_processing_algorithm

[/] [pulse_processing_algorithm/] [controller_ddr2_iobs.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	panda_emc	`--******************************************************************************`
2			`--`
3			`-- Xilinx, Inc. 2002 www.xilinx.com`
4			`--`
5			`-- XAPP 253 - Synthesizable DDR SDRAM Controller`
6			`--`
7			`--*******************************************************************************`
8			`--`
9			`-- File name : controller.vhd`
10			`--`
11			`-- Description :`
12			`-- Main DDR SDRAM controller block. This includes the following`
13			`-- features:`
14			`-- - The controller state machine that controls the`
15			`-- initialization process upon power up, as well as the`
16			`-- read, write, and refresh commands.`
17			`-- - Accepts and decodes the user commands.`
18			`-- - Generates the address and Bank address signals`
19			`-- - Generates control signals for other modules, including`
20			`-- the control signals for the dqs_en block.`
21			`--`
22			`--`
23			`--*****************************************************************************`
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26			`use ieee.std_logic_unsigned.all;`
27			`--`
28			`-- pragma translate_off`
29			`library UNISIM;`
30			`use UNISIM.VCOMPONENTS.ALL;`
31			`-- pragma translate_on`
32
33			`entity controller_ddr2_iobs is`
34			`port(`
35			`clk0 : in std_logic;`
36			`clk180 : in std_logic;`
37			`ddr_rasb_cntrl : in std_logic;`
38			`ddr_casb_cntrl : in std_logic;`
39			`ddr_web_cntrl : in std_logic;`
40			`ddr_cke_cntrl : in std_logic;`
41			`ddr_csb_cntrl : in std_logic;`
42			`ddr_ODT_cntrl : in std_logic;`
43			`ddr_address_cntrl: in std_logic_vector(12 downto 0);`
44			`ddr_ba_cntrl : in std_logic_vector(1 downto 0);`
45			`rst_dqs_div_int : in std_logic;`
46			`ddr_rasb : out std_logic;`
47			`ddr_ODT0 : out std_logic;`
48			`ddr_casb : out std_logic;`
49			`ddr_web : out std_logic;`
50			`ddr_ba : out std_logic_vector(1 downto 0);`
51			`ddr_address : out std_logic_vector(15 downto 0);`
52			`ddr_cke : out std_logic;`
53			`ddr_csb : out std_logic;`
54			`rst_dqs_div : out std_logic;`
55			`rst_dqs_div_iob : inout std_logic`
56			`-- rst_dqs_div_in : in std_logic;`
57			`-- rst_dqs_div_out : out std_logic`
58
59			`);`
60			`end controller_ddr2_iobs;`
61
62
63			`architecture arc_controller_ddr2_iobs of controller_ddr2_iobs is`
64
65			`attribute xc_props : string;`
66			`attribute syn_keep : boolean;`
67
68
69			`component IBUF_SSTL2_II`
70			`port (`
71			`I : in std_logic;`
72			`O : out std_logic);`
73			`end component;`
74
75			`component OBUF_SSTL2_II`
76			`port (`
77			`I : in std_logic;`
78			`O : out std_logic);`
79			`end component;`
80
81			`component IBUF`
82			`port (`
83			`I : in std_logic;`
84			`O : out std_logic);`
85			`end component;`
86
87			`component OBUF`
88			`port (`
89			`I : in std_logic;`
90			`O : out std_logic);`
91			`end component;`
92
93
94			`component FD`
95			`port(`
96			`Q : out STD_LOGIC;`
97			`D : in STD_LOGIC;`
98			`C : in STD_LOGIC);`
99			`end component;`
100
101			`component OFD`
102			`port(`
103			`Q : out STD_LOGIC;`
104			`D : in STD_LOGIC;`
105			`C : in STD_LOGIC);`
106			`end component;`
107
108			`--component OBUFT`
109			`--port(`
110			`-- I : in std_logic;`
111			`-- T : in std_logic;`
112			`-- O : out std_logic);`
113			`--end component;`
114
115
116			`---- **************************************************`
117			`---- iob attributes for instantiated FD components`
118			`---- **************************************************`
119
120
121			`--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL`
122			`--signal rst_dqs_div_out : std_logic;`
123
124
125			`--signal GND : std_logic;`
126			`--signal ddr_web_q : std_logic;`
127			`--signal ddr_rasb_q : std_logic;`
128			`--signal ddr_casb_q : std_logic;`
129
130			`--signal ddr_ba_q : std_logic_vector(1 downto 0);`
131			`--signal ddr_address_q : std_logic_vector(15 downto 0);`
132			`--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL`
133
134
135
136			`--attribute xc_props of iob_web: label is "IOB=TRUE";`
137			`--attribute xc_props of iob_rasb: label is "IOB=TRUE";`
138			`--attribute xc_props of iob_casb: label is "IOB=TRUE";`
139
140
141			`--attribute xc_props of iob_addr0: label is "IOB=TRUE";`
142			`--attribute xc_props of iob_addr1: label is "IOB=TRUE";`
143			`--attribute xc_props of iob_addr2: label is "IOB=TRUE";`
144			`--attribute xc_props of iob_addr3: label is "IOB=TRUE";`
145			`--attribute xc_props of iob_addr4: label is "IOB=TRUE";`
146			`--attribute xc_props of iob_addr5: label is "IOB=TRUE";`
147			`--attribute xc_props of iob_addr6: label is "IOB=TRUE";`
148			`--attribute xc_props of iob_addr7: label is "IOB=TRUE";`
149			`--attribute xc_props of iob_addr8: label is "IOB=TRUE";`
150			`--attribute xc_props of iob_addr9: label is "IOB=TRUE";`
151			`--attribute xc_props of iob_addr10: label is "IOB=TRUE";`
152			`--attribute xc_props of iob_addr11: label is "IOB=TRUE";`
153			`--attribute xc_props of iob_addr12: label is "IOB=TRUE";`
154
155			`--attribute xc_props of iob_ba0: label is "IOB=TRUE";`
156			`--attribute xc_props of iob_ba1: label is "IOB=TRUE";`
157
158			`begin`
159
160			`--PLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLPLLPLPLPL`
161			`--GND <= '0';`
162
163
164			`---- ******************************************* ----`
165			`---- Includes the instantiation of FD for cntrl ----`
166			`---- signals ----`
167			`---- ******************************************* ----`
168
169			`iob_web : OFD port map (`
170			`Q => ddr_web,`
171			`D => ddr_web_cntrl,`
172			`C => clk180);`
173
174			`iob_rasb : OFD port map (`
175			`Q => ddr_rasb,`
176			`D => ddr_rasb_cntrl,`
177			`C => clk180);`
178
179			`iob_casb : OFD port map (`
180			`Q => ddr_casb,`
181			`D => ddr_casb_cntrl,`
182			`C => clk180);`
183
184
185			`--iob_casb : FD port map (`
186			`-- Q => ddr_casb_q,`
187			`-- D => ddr_casb_cntrl,`
188			`-- C => clk180);`
189
190
191			`---- ************************************* ----`
192			`---- Output buffers for control signals ----`
193			`---- ************************************* ----`
194
195			`--r0 : OBUF port map (`
196			`-- I => ddr_web_q,`
197			`-- O => ddr_web);`
198
199			`--r1 : OBUF port map (`
200			`-- I => ddr_rasb_q,`
201			`-- O => ddr_rasb);`
202
203			`--r2 : OBUF port map (`
204			`-- I => ddr_casb_q,`
205			`-- O => ddr_casb);`
206
207			`r3 : OBUF port map (`
208			`I => ddr_cke_cntrl,`
209			`O => ddr_cke);`
210
211			`r4 : OBUF port map (`
212			`I => ddr_csb_cntrl,`
213			`O => ddr_csb);`
214
215			`r40 : OBUF port map (`
216			`I => ddr_ODT_cntrl,`
217			`O => ddr_ODT0);`
218
219
220
221			`---- ************************************* ----`
222			`---- Output buffers for address signals ----`
223			`---- ************************************* ----`
224
225
226
227
228			`--iob_addr0 : FD port map (`
229			`-- Q => ddr_address_q(0),`
230			`-- D => ddr_address_cntrl(0),`
231			`-- C => clk180);`
232
233			`iob_addr0 : OFD port map (`
234			`Q => ddr_address(0),`
235			`D => ddr_address_cntrl(0),`
236			`C => clk180);`
237
238			`iob_addr1 : OFD port map (`
239			`Q => ddr_address(1),`
240			`D => ddr_address_cntrl(1),`
241			`C => clk180);`
242
243			`iob_addr2 : OFD port map (`
244			`Q => ddr_address(2),`
245			`D => ddr_address_cntrl(2),`
246			`C => clk180);`
247
248			`iob_addr3 : OFD port map (`
249			`Q => ddr_address(3),`
250			`D => ddr_address_cntrl(3),`
251			`C => clk180);`
252
253			`iob_addr4 : OFD port map (`
254			`Q => ddr_address(4),`
255			`D => ddr_address_cntrl(4),`
256			`C => clk180);`
257
258			`iob_addr5 : OFD port map (`
259			`Q => ddr_address(5),`
260			`D => ddr_address_cntrl(5),`
261			`C => clk180);`
262
263			`iob_addr6 : OFD port map (`
264			`Q => ddr_address(6),`
265			`D => ddr_address_cntrl(6),`
266			`C => clk180);`
267
268			`iob_addr7 : OFD port map (`
269			`Q => ddr_address(7),`
270			`D => ddr_address_cntrl(7),`
271			`C => clk180);`
272
273			`iob_addr8 : OFD port map (`
274			`Q => ddr_address(8),`
275			`D => ddr_address_cntrl(8),`
276			`C => clk180);`
277
278			`iob_addr9 : OFD port map (`
279			`Q => ddr_address(9),`
280			`D => ddr_address_cntrl(9),`
281			`C => clk180);`
282
283			`iob_addr10 : OFD port map (`
284			`Q => ddr_address(10),`
285			`D => ddr_address_cntrl(10),`
286			`C => clk180);`
287
288			`iob_addr11 : OFD port map (`
289			`Q => ddr_address(11),`
290			`D => ddr_address_cntrl(11),`
291			`C => clk180);`
292
293			`iob_addr12 : OFD port map (`
294			`Q => ddr_address(12),`
295			`D => ddr_address_cntrl(12),`
296			`C => clk180);`
297
298			`iob_addr13 : OFD port map (`
299			`Q => ddr_address(13),`
300			`D => ddr_address_cntrl(12),`
301			`C => clk180);`
302
303			`iob_addr14 : OFD port map (`
304			`Q => ddr_address(14),`
305			`D => ddr_address_cntrl(12),`
306			`C => clk180);`
307
308
309			`iob_addr15 : OFD port map (`
310			`Q => ddr_address(15),`
311			`D => ddr_address_cntrl(12),`
312			`C => clk180);`
313
314
315
316			`--r5 : OBUF port map (`
317			`-- I => ddr_address_q(0),`
318			`-- O => ddr_address(0));`
319
320			`--r6 : OBUF port map (`
321			`-- I => ddr_address_q(1),`
322			`-- O => ddr_address(1));`
323
324			`--r7 : OBUF port map (`
325			`-- I => ddr_address_q(2),`
326			`-- O => ddr_address(2));`
327
328			`--r8 : OBUF port map (`
329			`-- I => ddr_address_q(3),`
330			`-- O => ddr_address(3));`
331
332			`--r9 : OBUF port map (`
333			`-- I => ddr_address_q(4),`
334			`-- O => ddr_address(4));`
335
336			`--r10 : OBUF port map (`
337			`-- I => ddr_address_q(5),`
338			`-- O => ddr_address(5));`
339
340			`--r11 : OBUF port map (`
341			`-- I => ddr_address_q(6),`
342			`-- O => ddr_address(6));`
343
344			`--r12 : OBUF port map (`
345			`-- I => ddr_address_q(7),`
346			`-- O => ddr_address(7));`
347
348			`--r13 : OBUF port map (`
349			`-- I => ddr_address_q(8),`
350			`-- O => ddr_address(8));`
351
352			`--r14 : OBUF port map (`
353			`-- I => ddr_address_q(9),`
354			`-- O => ddr_address(9));`
355
356			`--r15 : OBUF port map (`
357			`-- I => ddr_address_q(10),`
358			`-- O => ddr_address(10));`
359
360			`--r16 : OBUF port map (`
361			`-- I => ddr_address_q(11),`
362			`-- O => ddr_address(11));`
363
364			`--r17 : OBUF port map (`
365			`-- I => ddr_address_q(12),`
366			`-- O => ddr_address(12));`
367
368
369
370
371			`iob_ba0 : FD port map (`
372			`Q => ddr_ba(0),`
373			`D => ddr_ba_cntrl(0),`
374			`C => clk180);`
375
376			`iob_ba1 : FD port map (`
377			`Q => ddr_ba(1),`
378			`D => ddr_ba_cntrl(1),`
379			`C => clk180);`
380
381			`--r18 : OBUF port map (`
382			`-- I => ddr_ba_q(0),`
383			`-- O => ddr_ba(0));`
384
385			`--r19 : OBUF port map (`
386			`-- I => ddr_ba_q(1),`
387			`-- O => ddr_ba(1));`
388
389
390
391			`---rst_iob_inbuf : IBUF port map`
392			`rst_iob_inbuf : IBUF_SSTL2_II port map`
393			`( I => rst_dqs_div_iob,`
394			`O => rst_dqs_div);`
395
396
397			`---rst_iob_outbuf : OBUF port map`
398			`rst_iob_outbuf : OBUF_SSTL2_II port map`
399			`( I => rst_dqs_div_int,`
400			`-- O => rst_dqs_div_out);`
401			`O => rst_dqs_div_iob);`
402
403
404
405
406
407
408			`--U3 : OBUFT port map ( I => rst_dqs_div_out,`
409			`-- T => '0' ,`
410			`-- O => rst_dqs_div_iob);`
411
412
413
414
415
416			`end arc_controller_ddr2_iobs;`
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