1 |
2 |
panda_emc |
--*********************************************************************
|
2 |
|
|
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins
|
3 |
|
|
|
4 |
|
|
-- In the current DATA PATH logic DATA CAPTURE part was modified.
|
5 |
|
|
-- The below changes were made to reduce the resources in
|
6 |
|
|
-- the data capture
|
7 |
|
|
|
8 |
|
|
-- in the current architecture data ( dq ) from ddr memory
|
9 |
|
|
-- directly stored into the FIFO's.
|
10 |
|
|
|
11 |
|
|
-- Architectural changes :
|
12 |
|
|
|
13 |
|
|
-- Used only TWO FIFOs ( instead of FOUR FIFOs )
|
14 |
|
|
-- Used Single col ( col0 ) dqs_delayed_col signals
|
15 |
|
|
-- Used Gray Counters for write and read pointers of the FIFOs
|
16 |
|
|
|
17 |
|
|
-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
|
18 |
|
|
-- dq_clk stage was removed
|
19 |
|
|
-- dqs_clk_div logic was removed
|
20 |
|
|
-- ddr1_transfer_done logic was removed
|
21 |
|
|
-- data valid signals registering in clk90 domain was removed
|
22 |
|
|
|
23 |
|
|
-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
|
24 |
|
|
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic
|
25 |
|
|
-- write enable for the FIFOs derived from rst_dqs_div signal
|
26 |
|
|
|
27 |
|
|
|
28 |
|
|
|
29 |
|
|
--*********************************************************************
|
30 |
|
|
|
31 |
|
|
|
32 |
|
|
library ieee;
|
33 |
|
|
use ieee.std_logic_1164.all;
|
34 |
|
|
use ieee.std_logic_unsigned.all;
|
35 |
|
|
--library synplify;
|
36 |
|
|
--use synplify.attributes.all;
|
37 |
|
|
--
|
38 |
|
|
-- pragma translate_off
|
39 |
|
|
library UNISIM;
|
40 |
|
|
use UNISIM.VCOMPONENTS.ALL;
|
41 |
|
|
-- pragma translate_on
|
42 |
|
|
--
|
43 |
|
|
|
44 |
|
|
entity data_read is
|
45 |
|
|
port(
|
46 |
|
|
|
47 |
|
|
clk90 : in std_logic;
|
48 |
|
|
reset90_r : in std_logic;
|
49 |
|
|
--old ddr_dq_in : in std_logic_vector(15 downto 0);
|
50 |
|
|
ddr_dq_in_rising : in std_logic_vector(15 downto 0);
|
51 |
|
|
ddr_dq_in_falling : in std_logic_vector(15 downto 0);
|
52 |
|
|
read_valid_data_1 : in std_logic;
|
53 |
|
|
|
54 |
|
|
fifo_00_wr_en : in std_logic;
|
55 |
|
|
fifo_10_wr_en : in std_logic;
|
56 |
|
|
|
57 |
|
|
fifo_01_wr_en : in std_logic;
|
58 |
|
|
fifo_11_wr_en : in std_logic;
|
59 |
|
|
|
60 |
|
|
fifo_00_wr_addr : in std_logic_vector(3 downto 0);
|
61 |
|
|
fifo_01_wr_addr : in std_logic_vector(3 downto 0);
|
62 |
|
|
fifo_10_wr_addr : in std_logic_vector(3 downto 0);
|
63 |
|
|
fifo_11_wr_addr : in std_logic_vector(3 downto 0);
|
64 |
|
|
|
65 |
|
|
-- dqs0_delayed_col1 : in std_logic;
|
66 |
|
|
-- dqs1_delayed_col1 : in std_logic;
|
67 |
|
|
|
68 |
|
|
dqs0_delayed_col0 : in std_logic;
|
69 |
|
|
dqs1_delayed_col0 : in std_logic;
|
70 |
|
|
|
71 |
|
|
|
72 |
|
|
user_output_data : out std_logic_vector(31 downto 0);
|
73 |
|
|
fifo0_rd_addr_val: out std_logic_vector(3 downto 0);
|
74 |
|
|
fifo1_rd_addr_val: out std_logic_vector(3 downto 0)
|
75 |
|
|
|
76 |
|
|
);
|
77 |
|
|
end data_read;
|
78 |
|
|
|
79 |
|
|
architecture arc_data_read of data_read is
|
80 |
|
|
|
81 |
|
|
attribute syn_keep : boolean; -- Using Syn_Keep Derictive
|
82 |
|
|
attribute syn_noprune : boolean; -- Using syn_noprune Derictive
|
83 |
|
|
|
84 |
|
|
attribute syn_preserve : boolean; -- Using syn_noprune Derictive
|
85 |
|
|
-- rd_gray_cntr is a gray counter with a SYNC reset ( reset_90r) for fifo rd_addr
|
86 |
|
|
component rd_gray_cntr port (
|
87 |
|
|
clk : in std_logic;
|
88 |
|
|
reset : in std_logic;
|
89 |
|
|
cnt_en : in std_logic;
|
90 |
|
|
rgc_gcnt : out std_logic_vector(3 downto 0)
|
91 |
|
|
|
92 |
|
|
);
|
93 |
|
|
end component;
|
94 |
|
|
|
95 |
|
|
component FD port(
|
96 |
|
|
Q : out STD_LOGIC;
|
97 |
|
|
C : in STD_LOGIC;
|
98 |
|
|
D : in STD_LOGIC
|
99 |
|
|
);
|
100 |
|
|
end component;
|
101 |
|
|
|
102 |
|
|
-- 16x1 Dual Port RAM Component Instansiated
|
103 |
|
|
|
104 |
|
|
component RAM16X1D
|
105 |
|
|
port (D : in std_logic;
|
106 |
|
|
WE : in std_logic;
|
107 |
|
|
WCLK : in std_logic;
|
108 |
|
|
A0 : in std_logic;
|
109 |
|
|
A1 : in std_logic;
|
110 |
|
|
A2 : in std_logic;
|
111 |
|
|
A3 : in std_logic;
|
112 |
|
|
DPRA0 : in std_logic;
|
113 |
|
|
DPRA1 : in std_logic;
|
114 |
|
|
DPRA2 : in std_logic;
|
115 |
|
|
DPRA3 : in std_logic;
|
116 |
|
|
SPO : out std_logic;
|
117 |
|
|
DPO : out std_logic);
|
118 |
|
|
|
119 |
|
|
end component;
|
120 |
|
|
|
121 |
|
|
|
122 |
|
|
signal read_valid_data_1_r : std_logic;
|
123 |
|
|
signal read_valid_data_1_r1 : std_logic;
|
124 |
|
|
--PL
|
125 |
|
|
--signal read_valid_data_1_r2 : std_logic;
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
|
129 |
|
|
signal fifo00_rd_addr : std_logic_vector(3 downto 0);
|
130 |
|
|
signal fifo01_rd_addr : std_logic_vector(3 downto 0);
|
131 |
|
|
|
132 |
|
|
|
133 |
|
|
signal fifo00_rd_addr_r : std_logic_vector(3 downto 0);
|
134 |
|
|
signal fifo01_rd_addr_r : std_logic_vector(3 downto 0);
|
135 |
|
|
signal fifo10_rd_addr_r : std_logic_vector(3 downto 0);
|
136 |
|
|
signal fifo11_rd_addr_r : std_logic_vector(3 downto 0);
|
137 |
|
|
--PL
|
138 |
|
|
--signal fifop_rd_addr_r : std_logic_vector(3 downto 0);
|
139 |
|
|
|
140 |
|
|
|
141 |
|
|
attribute syn_noprune of fifo00_rd_addr_r : signal is true;
|
142 |
|
|
attribute syn_noprune of fifo01_rd_addr_r : signal is true;
|
143 |
|
|
attribute syn_noprune of fifo10_rd_addr_r : signal is true;
|
144 |
|
|
attribute syn_noprune of fifo11_rd_addr_r : signal is true;
|
145 |
|
|
--PL
|
146 |
|
|
--attribute syn_noprune of fifop_rd_addr_r : signal is true;
|
147 |
|
|
|
148 |
|
|
attribute syn_preserve of fifo00_rd_addr_r : signal is true; -- verbietet register verdoppelung
|
149 |
|
|
attribute syn_preserve of fifo01_rd_addr_r : signal is true;
|
150 |
|
|
attribute syn_preserve of fifo10_rd_addr_r : signal is true;
|
151 |
|
|
attribute syn_preserve of fifo11_rd_addr_r : signal is true;
|
152 |
|
|
--PL
|
153 |
|
|
--attribute syn_preserve of fifop_rd_addr_r : signal is true;
|
154 |
|
|
|
155 |
|
|
|
156 |
|
|
|
157 |
|
|
signal fifo_00_data_out : std_logic_vector(7 downto 0);
|
158 |
|
|
signal fifo_01_data_out : std_logic_vector(7 downto 0);
|
159 |
|
|
signal fifo_10_data_out : std_logic_vector(7 downto 0);
|
160 |
|
|
signal fifo_11_data_out : std_logic_vector(7 downto 0);
|
161 |
|
|
|
162 |
|
|
|
163 |
|
|
-- reg added for timing
|
164 |
|
|
signal fifo_00_data_out_r : std_logic_vector(7 downto 0);
|
165 |
|
|
signal fifo_01_data_out_r : std_logic_vector(7 downto 0);
|
166 |
|
|
signal fifo_10_data_out_r : std_logic_vector(7 downto 0);
|
167 |
|
|
signal fifo_11_data_out_r : std_logic_vector(7 downto 0);
|
168 |
|
|
|
169 |
|
|
signal first_sdr_data : std_logic_vector(31 downto 0);
|
170 |
|
|
|
171 |
|
|
signal dqs0_delayed_col0_n : std_logic;
|
172 |
|
|
signal dqs1_delayed_col0_n : std_logic;
|
173 |
|
|
|
174 |
|
|
|
175 |
|
|
--th attribute syn_keep of dqs0_delayed_col0 : signal is true;
|
176 |
|
|
--th attribute syn_keep of dqs0_delayed_col0_n : signal is true;
|
177 |
|
|
|
178 |
|
|
-- Directive for synthesis
|
179 |
|
|
--attribute syn_noprune of dqs0_delayed_col0_n : signal is true;
|
180 |
|
|
--attribute syn_noprune of dqs1_delayed_col0_n : signal is true;
|
181 |
|
|
|
182 |
|
|
|
183 |
|
|
--signal dqs0_delayed_col1_n : std_logic;
|
184 |
|
|
--signal dqs1_delayed_col1_n : std_logic;
|
185 |
|
|
|
186 |
|
|
-- Directive for synthesis
|
187 |
|
|
--attribute syn_noprune of dqs0_delayed_col1_n : signal is true;
|
188 |
|
|
--attribute syn_noprune of dqs1_delayed_col1_n : signal is true;
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
|
192 |
|
|
begin
|
193 |
|
|
|
194 |
|
|
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
|
195 |
|
|
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
|
196 |
|
|
|
197 |
|
|
|
198 |
|
|
--dqs0_delayed_col1_n <= not dqs0_delayed_col1;
|
199 |
|
|
--dqs1_delayed_col1_n <= not dqs1_delayed_col1;
|
200 |
|
|
|
201 |
|
|
|
202 |
|
|
user_output_data <= first_sdr_data;
|
203 |
|
|
|
204 |
|
|
|
205 |
|
|
fifo0_rd_addr_val <= fifo01_rd_addr;
|
206 |
|
|
fifo1_rd_addr_val <= fifo00_rd_addr;
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
process(clk90)
|
210 |
|
|
begin
|
211 |
|
|
if clk90'event and clk90 = '1' then
|
212 |
|
|
if reset90_r = '1' then
|
213 |
|
|
fifo_00_data_out_r <= "00000000";
|
214 |
|
|
fifo_01_data_out_r <= "00000000";
|
215 |
|
|
fifo_10_data_out_r <= "00000000";
|
216 |
|
|
fifo_11_data_out_r <= "00000000";
|
217 |
|
|
else
|
218 |
|
|
fifo_00_data_out_r <= fifo_00_data_out;
|
219 |
|
|
fifo_01_data_out_r <= fifo_01_data_out;
|
220 |
|
|
fifo_10_data_out_r <= fifo_10_data_out;
|
221 |
|
|
fifo_11_data_out_r <= fifo_11_data_out;
|
222 |
|
|
end if;
|
223 |
|
|
end if;
|
224 |
|
|
end process;
|
225 |
|
|
|
226 |
|
|
|
227 |
|
|
process(clk90)
|
228 |
|
|
begin
|
229 |
|
|
if clk90'event and clk90 = '1' then
|
230 |
|
|
if reset90_r = '1' then
|
231 |
|
|
fifo00_rd_addr_r <= "0000";
|
232 |
|
|
fifo01_rd_addr_r <= "0000";
|
233 |
|
|
fifo10_rd_addr_r <= "0000";
|
234 |
|
|
fifo11_rd_addr_r <= "0000";
|
235 |
|
|
--PL
|
236 |
|
|
-- fifop_rd_addr_r <= "0000";
|
237 |
|
|
else
|
238 |
|
|
fifo00_rd_addr_r <= fifo00_rd_addr;
|
239 |
|
|
fifo01_rd_addr_r <= fifo00_rd_addr;
|
240 |
|
|
fifo10_rd_addr_r <= fifo00_rd_addr;
|
241 |
|
|
fifo11_rd_addr_r <= fifo00_rd_addr;
|
242 |
|
|
--PL
|
243 |
|
|
-- fifop_rd_addr_r <= fifo01_rd_addr;
|
244 |
|
|
end if;
|
245 |
|
|
end if;
|
246 |
|
|
end process;
|
247 |
|
|
|
248 |
|
|
|
249 |
|
|
process(clk90)
|
250 |
|
|
begin
|
251 |
|
|
if clk90'event and clk90 = '1' then
|
252 |
|
|
if reset90_r = '1' then
|
253 |
|
|
first_sdr_data <= (others => '0');
|
254 |
|
|
read_valid_data_1_r <= '0';
|
255 |
|
|
read_valid_data_1_r1 <= '0';
|
256 |
|
|
--PL
|
257 |
|
|
--read_valid_data_1_r2 <= '0';
|
258 |
|
|
else
|
259 |
|
|
read_valid_data_1_r <= read_valid_data_1;
|
260 |
|
|
read_valid_data_1_r1 <= read_valid_data_1_r;
|
261 |
|
|
-- PL
|
262 |
|
|
-- read_valid_data_1_r2 <= read_valid_data_1_r1;
|
263 |
|
|
if (read_valid_data_1_r1 = '1') then
|
264 |
|
|
first_sdr_data <=
|
265 |
|
|
fifo_10_data_out_r & fifo_00_data_out_r &
|
266 |
|
|
fifo_11_data_out_r & fifo_01_data_out_r ;
|
267 |
|
|
else
|
268 |
|
|
first_sdr_data <= first_sdr_data;
|
269 |
|
|
end if;
|
270 |
|
|
end if;
|
271 |
|
|
end if;
|
272 |
|
|
end process;
|
273 |
|
|
|
274 |
|
|
--------------------------------------------------------------------
|
275 |
|
|
|
276 |
|
|
-- fifo_x0_rd_addr and fifo_x1_rd_addr counters ( gray counters )
|
277 |
|
|
|
278 |
|
|
fifo0_rd_addr_inst : rd_gray_cntr port map (
|
279 |
|
|
clk => clk90,
|
280 |
|
|
reset => reset90_r,
|
281 |
|
|
cnt_en => read_valid_data_1,
|
282 |
|
|
rgc_gcnt => fifo00_rd_addr
|
283 |
|
|
|
284 |
|
|
);
|
285 |
|
|
fifo1_rd_addr_inst : rd_gray_cntr port map (
|
286 |
|
|
clk => clk90,
|
287 |
|
|
reset => reset90_r,
|
288 |
|
|
cnt_en => read_valid_data_1,
|
289 |
|
|
rgc_gcnt => fifo01_rd_addr
|
290 |
|
|
|
291 |
|
|
);
|
292 |
|
|
|
293 |
|
|
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
--*************************************************************************************************************************
|
297 |
|
|
-- Dual Port RAM 16x1 instantiations (fifo0 -- Positive edge, fifo1 -- Trailing edge)
|
298 |
|
|
--*************************************************************************************************************************
|
299 |
|
|
|
300 |
|
|
--- Byte0 instantiation
|
301 |
|
|
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
fifo0_bit0 : RAM16X1D
|
305 |
|
|
port map (DPO => fifo_00_data_out(0),
|
306 |
|
|
A0 => fifo_00_wr_addr(0),
|
307 |
|
|
A1 => fifo_00_wr_addr(1),
|
308 |
|
|
A2 => fifo_00_wr_addr(2),
|
309 |
|
|
A3 => fifo_00_wr_addr(3),
|
310 |
|
|
D => ddr_dq_in_rising(0),
|
311 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
312 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
313 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
314 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
315 |
|
|
WCLK => dqs0_delayed_col0,
|
316 |
|
|
WE => fifo_00_wr_en );
|
317 |
|
|
|
318 |
|
|
fifo1_bit0 : RAM16X1D
|
319 |
|
|
port map (DPO => fifo_01_data_out(0),
|
320 |
|
|
A0 => fifo_01_wr_addr(0),
|
321 |
|
|
A1 => fifo_01_wr_addr(1),
|
322 |
|
|
A2 => fifo_01_wr_addr(2),
|
323 |
|
|
A3 => fifo_01_wr_addr(3),
|
324 |
|
|
D => ddr_dq_in_falling(0),
|
325 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
326 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
327 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
328 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
329 |
|
|
WCLK => dqs0_delayed_col0_n,
|
330 |
|
|
WE => fifo_01_wr_en );
|
331 |
|
|
|
332 |
|
|
fifo0_bit1 : RAM16X1D
|
333 |
|
|
port map (DPO => fifo_00_data_out(1),
|
334 |
|
|
A0 => fifo_00_wr_addr(0),
|
335 |
|
|
A1 => fifo_00_wr_addr(1),
|
336 |
|
|
A2 => fifo_00_wr_addr(2),
|
337 |
|
|
A3 => fifo_00_wr_addr(3),
|
338 |
|
|
D => ddr_dq_in_rising(1),
|
339 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
340 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
341 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
342 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
343 |
|
|
WCLK => dqs0_delayed_col0,
|
344 |
|
|
WE => fifo_00_wr_en );
|
345 |
|
|
|
346 |
|
|
fifo1_bit1 : RAM16X1D
|
347 |
|
|
port map (DPO => fifo_01_data_out(1),
|
348 |
|
|
A0 => fifo_01_wr_addr(0),
|
349 |
|
|
A1 => fifo_01_wr_addr(1),
|
350 |
|
|
A2 => fifo_01_wr_addr(2),
|
351 |
|
|
A3 => fifo_01_wr_addr(3),
|
352 |
|
|
D => ddr_dq_in_falling(1),
|
353 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
354 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
355 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
356 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
357 |
|
|
WCLK => dqs0_delayed_col0_n,
|
358 |
|
|
WE => fifo_01_wr_en );
|
359 |
|
|
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
fifo0_bit2 : RAM16X1D
|
363 |
|
|
port map (DPO => fifo_00_data_out(2),
|
364 |
|
|
A0 => fifo_00_wr_addr(0),
|
365 |
|
|
A1 => fifo_00_wr_addr(1),
|
366 |
|
|
A2 => fifo_00_wr_addr(2),
|
367 |
|
|
A3 => fifo_00_wr_addr(3),
|
368 |
|
|
D => ddr_dq_in_rising(2),
|
369 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
370 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
371 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
372 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
373 |
|
|
WCLK => dqs0_delayed_col0,
|
374 |
|
|
WE => fifo_00_wr_en );
|
375 |
|
|
|
376 |
|
|
fifo1_bit2 : RAM16X1D
|
377 |
|
|
port map (DPO => fifo_01_data_out(2),
|
378 |
|
|
A0 => fifo_01_wr_addr(0),
|
379 |
|
|
A1 => fifo_01_wr_addr(1),
|
380 |
|
|
A2 => fifo_01_wr_addr(2),
|
381 |
|
|
A3 => fifo_01_wr_addr(3),
|
382 |
|
|
D => ddr_dq_in_falling(2),
|
383 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
384 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
385 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
386 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
387 |
|
|
WCLK => dqs0_delayed_col0_n,
|
388 |
|
|
WE => fifo_01_wr_en );
|
389 |
|
|
|
390 |
|
|
fifo0_bit3 : RAM16X1D
|
391 |
|
|
port map (DPO => fifo_00_data_out(3),
|
392 |
|
|
A0 => fifo_00_wr_addr(0),
|
393 |
|
|
A1 => fifo_00_wr_addr(1),
|
394 |
|
|
A2 => fifo_00_wr_addr(2),
|
395 |
|
|
A3 => fifo_00_wr_addr(3),
|
396 |
|
|
D => ddr_dq_in_rising(3),
|
397 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
398 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
399 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
400 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
401 |
|
|
WCLK => dqs0_delayed_col0,
|
402 |
|
|
WE => fifo_00_wr_en );
|
403 |
|
|
|
404 |
|
|
fifo1_bit3 : RAM16X1D
|
405 |
|
|
port map (DPO => fifo_01_data_out(3),
|
406 |
|
|
A0 => fifo_01_wr_addr(0),
|
407 |
|
|
A1 => fifo_01_wr_addr(1),
|
408 |
|
|
A2 => fifo_01_wr_addr(2),
|
409 |
|
|
A3 => fifo_01_wr_addr(3),
|
410 |
|
|
D => ddr_dq_in_falling(3),
|
411 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
412 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
413 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
414 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
415 |
|
|
WCLK => dqs0_delayed_col0_n,
|
416 |
|
|
WE => fifo_01_wr_en );
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
|
420 |
|
|
fifo0_bit4 : RAM16X1D
|
421 |
|
|
port map (DPO => fifo_00_data_out(4),
|
422 |
|
|
A0 => fifo_00_wr_addr(0),
|
423 |
|
|
A1 => fifo_00_wr_addr(1),
|
424 |
|
|
A2 => fifo_00_wr_addr(2),
|
425 |
|
|
A3 => fifo_00_wr_addr(3),
|
426 |
|
|
D => ddr_dq_in_rising(4),
|
427 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
428 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
429 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
430 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
431 |
|
|
WCLK => dqs0_delayed_col0,
|
432 |
|
|
WE => fifo_00_wr_en );
|
433 |
|
|
|
434 |
|
|
fifo1_bit4 : RAM16X1D
|
435 |
|
|
port map (DPO => fifo_01_data_out(4),
|
436 |
|
|
A0 => fifo_01_wr_addr(0),
|
437 |
|
|
A1 => fifo_01_wr_addr(1),
|
438 |
|
|
A2 => fifo_01_wr_addr(2),
|
439 |
|
|
A3 => fifo_01_wr_addr(3),
|
440 |
|
|
D => ddr_dq_in_falling(4),
|
441 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
442 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
443 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
444 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
445 |
|
|
WCLK => dqs0_delayed_col0_n,
|
446 |
|
|
WE => fifo_01_wr_en );
|
447 |
|
|
|
448 |
|
|
fifo0_bit5 : RAM16X1D
|
449 |
|
|
port map (DPO => fifo_00_data_out(5),
|
450 |
|
|
A0 => fifo_00_wr_addr(0),
|
451 |
|
|
A1 => fifo_00_wr_addr(1),
|
452 |
|
|
A2 => fifo_00_wr_addr(2),
|
453 |
|
|
A3 => fifo_00_wr_addr(3),
|
454 |
|
|
D => ddr_dq_in_rising(5),
|
455 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
456 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
457 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
458 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
459 |
|
|
WCLK => dqs0_delayed_col0,
|
460 |
|
|
WE => fifo_00_wr_en );
|
461 |
|
|
|
462 |
|
|
fifo1_bit5 : RAM16X1D
|
463 |
|
|
port map (DPO => fifo_01_data_out(5),
|
464 |
|
|
A0 => fifo_01_wr_addr(0),
|
465 |
|
|
A1 => fifo_01_wr_addr(1),
|
466 |
|
|
A2 => fifo_01_wr_addr(2),
|
467 |
|
|
A3 => fifo_01_wr_addr(3),
|
468 |
|
|
D => ddr_dq_in_falling(5),
|
469 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
470 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
471 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
472 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
473 |
|
|
WCLK => dqs0_delayed_col0_n,
|
474 |
|
|
WE => fifo_01_wr_en );
|
475 |
|
|
|
476 |
|
|
|
477 |
|
|
fifo0_bit6 : RAM16X1D
|
478 |
|
|
port map (DPO => fifo_00_data_out(6),
|
479 |
|
|
A0 => fifo_00_wr_addr(0),
|
480 |
|
|
A1 => fifo_00_wr_addr(1),
|
481 |
|
|
A2 => fifo_00_wr_addr(2),
|
482 |
|
|
A3 => fifo_00_wr_addr(3),
|
483 |
|
|
D => ddr_dq_in_rising(6),
|
484 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
485 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
486 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
487 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
488 |
|
|
WCLK => dqs0_delayed_col0,
|
489 |
|
|
WE => fifo_00_wr_en );
|
490 |
|
|
|
491 |
|
|
fifo1_bit6 : RAM16X1D
|
492 |
|
|
port map (DPO => fifo_01_data_out(6),
|
493 |
|
|
A0 => fifo_01_wr_addr(0),
|
494 |
|
|
A1 => fifo_01_wr_addr(1),
|
495 |
|
|
A2 => fifo_01_wr_addr(2),
|
496 |
|
|
A3 => fifo_01_wr_addr(3),
|
497 |
|
|
D => ddr_dq_in_falling(6),
|
498 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
499 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
500 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
501 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
502 |
|
|
WCLK => dqs0_delayed_col0_n,
|
503 |
|
|
WE => fifo_01_wr_en );
|
504 |
|
|
|
505 |
|
|
fifo0_bit7 : RAM16X1D
|
506 |
|
|
port map (DPO => fifo_00_data_out(7),
|
507 |
|
|
A0 => fifo_00_wr_addr(0),
|
508 |
|
|
A1 => fifo_00_wr_addr(1),
|
509 |
|
|
A2 => fifo_00_wr_addr(2),
|
510 |
|
|
A3 => fifo_00_wr_addr(3),
|
511 |
|
|
D => ddr_dq_in_rising(7),
|
512 |
|
|
DPRA0 => fifo00_rd_addr_r(0),
|
513 |
|
|
DPRA1 => fifo00_rd_addr_r(1),
|
514 |
|
|
DPRA2 => fifo00_rd_addr_r(2),
|
515 |
|
|
DPRA3 => fifo00_rd_addr_r(3),
|
516 |
|
|
WCLK => dqs0_delayed_col0,
|
517 |
|
|
WE => fifo_00_wr_en );
|
518 |
|
|
|
519 |
|
|
fifo1_bit7 : RAM16X1D
|
520 |
|
|
port map (DPO => fifo_01_data_out(7),
|
521 |
|
|
A0 => fifo_01_wr_addr(0),
|
522 |
|
|
A1 => fifo_01_wr_addr(1),
|
523 |
|
|
A2 => fifo_01_wr_addr(2),
|
524 |
|
|
A3 => fifo_01_wr_addr(3),
|
525 |
|
|
D => ddr_dq_in_falling(7),
|
526 |
|
|
DPRA0 => fifo01_rd_addr_r(0),
|
527 |
|
|
DPRA1 => fifo01_rd_addr_r(1),
|
528 |
|
|
DPRA2 => fifo01_rd_addr_r(2),
|
529 |
|
|
DPRA3 => fifo01_rd_addr_r(3),
|
530 |
|
|
WCLK => dqs0_delayed_col0_n,
|
531 |
|
|
WE => fifo_01_wr_en );
|
532 |
|
|
|
533 |
|
|
|
534 |
|
|
-- Byte1 Fifo instantiation
|
535 |
|
|
|
536 |
|
|
fifo0_bit8 : RAM16X1D
|
537 |
|
|
port map (DPO => fifo_10_data_out(0),
|
538 |
|
|
A0 => fifo_10_wr_addr(0),
|
539 |
|
|
A1 => fifo_10_wr_addr(1),
|
540 |
|
|
A2 => fifo_10_wr_addr(2),
|
541 |
|
|
A3 => fifo_10_wr_addr(3),
|
542 |
|
|
D => ddr_dq_in_rising(8),
|
543 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
544 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
545 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
546 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
547 |
|
|
WCLK => dqs1_delayed_col0,
|
548 |
|
|
WE => fifo_10_wr_en );
|
549 |
|
|
|
550 |
|
|
fifo1_bit8 : RAM16X1D
|
551 |
|
|
port map (DPO => fifo_11_data_out(0),
|
552 |
|
|
A0 => fifo_11_wr_addr(0),
|
553 |
|
|
A1 => fifo_11_wr_addr(1),
|
554 |
|
|
A2 => fifo_11_wr_addr(2),
|
555 |
|
|
A3 => fifo_11_wr_addr(3),
|
556 |
|
|
D => ddr_dq_in_falling(8),
|
557 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
558 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
559 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
560 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
561 |
|
|
WCLK => dqs1_delayed_col0_n,
|
562 |
|
|
WE => fifo_11_wr_en );
|
563 |
|
|
|
564 |
|
|
fifo0_bit9 : RAM16X1D
|
565 |
|
|
port map (DPO => fifo_10_data_out(1),
|
566 |
|
|
A0 => fifo_10_wr_addr(0),
|
567 |
|
|
A1 => fifo_10_wr_addr(1),
|
568 |
|
|
A2 => fifo_10_wr_addr(2),
|
569 |
|
|
A3 => fifo_10_wr_addr(3),
|
570 |
|
|
D => ddr_dq_in_rising(9),
|
571 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
572 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
573 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
574 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
575 |
|
|
WCLK => dqs1_delayed_col0,
|
576 |
|
|
WE => fifo_10_wr_en );
|
577 |
|
|
|
578 |
|
|
fifo1_bit9 : RAM16X1D
|
579 |
|
|
port map (DPO => fifo_11_data_out(1),
|
580 |
|
|
A0 => fifo_11_wr_addr(0),
|
581 |
|
|
A1 => fifo_11_wr_addr(1),
|
582 |
|
|
A2 => fifo_11_wr_addr(2),
|
583 |
|
|
A3 => fifo_11_wr_addr(3),
|
584 |
|
|
D => ddr_dq_in_falling(9),
|
585 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
586 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
587 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
588 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
589 |
|
|
WCLK => dqs1_delayed_col0_n,
|
590 |
|
|
WE => fifo_11_wr_en );
|
591 |
|
|
|
592 |
|
|
|
593 |
|
|
fifo0_bit10 : RAM16X1D
|
594 |
|
|
port map (DPO => fifo_10_data_out(2),
|
595 |
|
|
A0 => fifo_10_wr_addr(0),
|
596 |
|
|
A1 => fifo_10_wr_addr(1),
|
597 |
|
|
A2 => fifo_10_wr_addr(2),
|
598 |
|
|
A3 => fifo_10_wr_addr(3),
|
599 |
|
|
D => ddr_dq_in_rising(10),
|
600 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
601 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
602 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
603 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
604 |
|
|
WCLK => dqs1_delayed_col0,
|
605 |
|
|
WE => fifo_10_wr_en );
|
606 |
|
|
|
607 |
|
|
fifo1_bit10 : RAM16X1D
|
608 |
|
|
port map (DPO => fifo_11_data_out(2),
|
609 |
|
|
A0 => fifo_11_wr_addr(0),
|
610 |
|
|
A1 => fifo_11_wr_addr(1),
|
611 |
|
|
A2 => fifo_11_wr_addr(2),
|
612 |
|
|
A3 => fifo_11_wr_addr(3),
|
613 |
|
|
D => ddr_dq_in_falling(10),
|
614 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
615 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
616 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
617 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
618 |
|
|
WCLK => dqs1_delayed_col0_n,
|
619 |
|
|
WE => fifo_11_wr_en );
|
620 |
|
|
|
621 |
|
|
fifo0_bit11 : RAM16X1D
|
622 |
|
|
port map (DPO => fifo_10_data_out(3),
|
623 |
|
|
A0 => fifo_10_wr_addr(0),
|
624 |
|
|
A1 => fifo_10_wr_addr(1),
|
625 |
|
|
A2 => fifo_10_wr_addr(2),
|
626 |
|
|
A3 => fifo_10_wr_addr(3),
|
627 |
|
|
D => ddr_dq_in_rising(11),
|
628 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
629 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
630 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
631 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
632 |
|
|
WCLK => dqs1_delayed_col0,
|
633 |
|
|
WE => fifo_10_wr_en );
|
634 |
|
|
|
635 |
|
|
fifo1_bit11 : RAM16X1D
|
636 |
|
|
port map (DPO => fifo_11_data_out(3),
|
637 |
|
|
A0 => fifo_11_wr_addr(0),
|
638 |
|
|
A1 => fifo_11_wr_addr(1),
|
639 |
|
|
A2 => fifo_11_wr_addr(2),
|
640 |
|
|
A3 => fifo_11_wr_addr(3),
|
641 |
|
|
D => ddr_dq_in_falling(11),
|
642 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
643 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
644 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
645 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
646 |
|
|
WCLK => dqs1_delayed_col0_n,
|
647 |
|
|
WE => fifo_11_wr_en );
|
648 |
|
|
|
649 |
|
|
|
650 |
|
|
|
651 |
|
|
fifo0_bit12 : RAM16X1D
|
652 |
|
|
port map (DPO => fifo_10_data_out(4),
|
653 |
|
|
A0 => fifo_10_wr_addr(0),
|
654 |
|
|
A1 => fifo_10_wr_addr(1),
|
655 |
|
|
A2 => fifo_10_wr_addr(2),
|
656 |
|
|
A3 => fifo_10_wr_addr(3),
|
657 |
|
|
D => ddr_dq_in_rising(12),
|
658 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
659 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
660 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
661 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
662 |
|
|
WCLK => dqs1_delayed_col0,
|
663 |
|
|
WE => fifo_10_wr_en );
|
664 |
|
|
|
665 |
|
|
fifo1_bit12 : RAM16X1D
|
666 |
|
|
port map (DPO => fifo_11_data_out(4),
|
667 |
|
|
A0 => fifo_11_wr_addr(0),
|
668 |
|
|
A1 => fifo_11_wr_addr(1),
|
669 |
|
|
A2 => fifo_11_wr_addr(2),
|
670 |
|
|
A3 => fifo_11_wr_addr(3),
|
671 |
|
|
D => ddr_dq_in_falling(12),
|
672 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
673 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
674 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
675 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
676 |
|
|
WCLK => dqs1_delayed_col0_n,
|
677 |
|
|
WE => fifo_11_wr_en );
|
678 |
|
|
|
679 |
|
|
fifo0_bit13 : RAM16X1D
|
680 |
|
|
port map (DPO => fifo_10_data_out(5),
|
681 |
|
|
A0 => fifo_10_wr_addr(0),
|
682 |
|
|
A1 => fifo_10_wr_addr(1),
|
683 |
|
|
A2 => fifo_10_wr_addr(2),
|
684 |
|
|
A3 => fifo_10_wr_addr(3),
|
685 |
|
|
D => ddr_dq_in_rising(13),
|
686 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
687 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
688 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
689 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
690 |
|
|
WCLK => dqs1_delayed_col0,
|
691 |
|
|
WE => fifo_10_wr_en );
|
692 |
|
|
|
693 |
|
|
fifo1_bit13 : RAM16X1D
|
694 |
|
|
port map (DPO => fifo_11_data_out(5),
|
695 |
|
|
A0 => fifo_11_wr_addr(0),
|
696 |
|
|
A1 => fifo_11_wr_addr(1),
|
697 |
|
|
A2 => fifo_11_wr_addr(2),
|
698 |
|
|
A3 => fifo_11_wr_addr(3),
|
699 |
|
|
D => ddr_dq_in_falling(13),
|
700 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
701 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
702 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
703 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
704 |
|
|
WCLK => dqs1_delayed_col0_n,
|
705 |
|
|
WE => fifo_11_wr_en );
|
706 |
|
|
|
707 |
|
|
|
708 |
|
|
fifo0_bit14 : RAM16X1D
|
709 |
|
|
port map (DPO => fifo_10_data_out(6),
|
710 |
|
|
A0 => fifo_10_wr_addr(0),
|
711 |
|
|
A1 => fifo_10_wr_addr(1),
|
712 |
|
|
A2 => fifo_10_wr_addr(2),
|
713 |
|
|
A3 => fifo_10_wr_addr(3),
|
714 |
|
|
D => ddr_dq_in_rising(14),
|
715 |
|
|
DPRA0 => fifo10_rd_addr_r(0),
|
716 |
|
|
DPRA1 => fifo10_rd_addr_r(1),
|
717 |
|
|
DPRA2 => fifo10_rd_addr_r(2),
|
718 |
|
|
DPRA3 => fifo10_rd_addr_r(3),
|
719 |
|
|
WCLK => dqs1_delayed_col0,
|
720 |
|
|
WE => fifo_10_wr_en );
|
721 |
|
|
|
722 |
|
|
fifo1_bit14 : RAM16X1D
|
723 |
|
|
port map (DPO => fifo_11_data_out(6),
|
724 |
|
|
A0 => fifo_11_wr_addr(0),
|
725 |
|
|
A1 => fifo_11_wr_addr(1),
|
726 |
|
|
A2 => fifo_11_wr_addr(2),
|
727 |
|
|
A3 => fifo_11_wr_addr(3),
|
728 |
|
|
D => ddr_dq_in_falling(14),
|
729 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
730 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
731 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
732 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
733 |
|
|
WCLK => dqs1_delayed_col0_n,
|
734 |
|
|
WE => fifo_11_wr_en );
|
735 |
|
|
|
736 |
|
|
fifo0_bit15 : RAM16X1D
|
737 |
|
|
port map (DPO => fifo_10_data_out(7),
|
738 |
|
|
A0 => fifo_10_wr_addr(0),
|
739 |
|
|
A1 => fifo_10_wr_addr(1),
|
740 |
|
|
A2 => fifo_10_wr_addr(2),
|
741 |
|
|
A3 => fifo_10_wr_addr(3),
|
742 |
|
|
D => ddr_dq_in_rising(15),
|
743 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
744 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
745 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
746 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
747 |
|
|
WCLK => dqs1_delayed_col0,
|
748 |
|
|
WE => fifo_10_wr_en );
|
749 |
|
|
|
750 |
|
|
fifo1_bit15 : RAM16X1D
|
751 |
|
|
port map (DPO => fifo_11_data_out(7),
|
752 |
|
|
A0 => fifo_11_wr_addr(0),
|
753 |
|
|
A1 => fifo_11_wr_addr(1),
|
754 |
|
|
A2 => fifo_11_wr_addr(2),
|
755 |
|
|
A3 => fifo_11_wr_addr(3),
|
756 |
|
|
D => ddr_dq_in_falling(15),
|
757 |
|
|
DPRA0 => fifo11_rd_addr_r(0),
|
758 |
|
|
DPRA1 => fifo11_rd_addr_r(1),
|
759 |
|
|
DPRA2 => fifo11_rd_addr_r(2),
|
760 |
|
|
DPRA3 => fifo11_rd_addr_r(3),
|
761 |
|
|
WCLK => dqs1_delayed_col0_n,
|
762 |
|
|
WE => fifo_11_wr_en );
|
763 |
|
|
|
764 |
|
|
|
765 |
|
|
|
766 |
|
|
|
767 |
|
|
end arc_data_read;
|