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[/] [pulse_processing_algorithm/] [datapath_ddr2_iobs.vhd] - Blame information for rev 2

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--*********************************************************************
-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins
 
-- In the current DATA PATH logic DATA CAPTURE part was modified.
-- The below changes were made to reduce the resources in 
-- the data capture
 
-- in the current architecture data ( dq ) from ddr memory 
-- directly stored into the FIFO's.
 
-- Architectural changes :
 
-- Used only TWO FIFOs ( instead of FOUR FIFOs ) 
-- Used Single col ( col0 ) dqs_delayed_col signals
-- Used Gray Counters for write and read pointers of the FIFOs 
 
-- fbit stage is removed from ddr1_dqbit module ( in the data capture )
-- dq_clk stage was removed 
-- dqs_clk_div logic was removed
-- ddr1_transfer_done logic was removed 
-- data valid signals registering in clk90 domain was removed
 
-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain
-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic  
-- write enable for the FIFOs derived from rst_dqs_div signal
 
 
-- Code revised by      : Narayana Murty.
-- Date                               : Nov 18, 2003. 
 
--*********************************************************************
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify; 
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
 
 
 
 
 
entity datapath_ddr2_iobs is
port(
    clk               : in std_logic;
    clk90             : in std_logic;
    reset90_r        : in std_logic;
    dqs_reset         : in std_logic;
    dqs_enable        : in std_logic;
    ddr_dqs           : inout std_logic_vector(1 downto 0);
    ddr_dq            : inout std_logic_vector(15 downto 0);
    write_data_falling: in std_logic_vector(15 downto 0);
    write_data_rising : in std_logic_vector(15 downto 0);
    write_en_val      : in std_logic;
    write_en_val1     : in std_logic;
    data_mask_f       : in std_logic_vector(1 downto 0);
    data_mask_r       : in std_logic_vector(1 downto 0);
    dqs_int_delay_in0 : out std_logic;
    dqs_int_delay_in1 : out std_logic;
    ddr_dq_in_rising  : out std_logic_vector(15 downto 0);
    ddr_dq_in_falling : out std_logic_vector(15 downto 0);
--old    ddr_dq_val         : out std_logic_vector(15 downto 0);
    ddr_dm            : out std_logic_vector(1 downto 0)
);
end datapath_ddr2_iobs;
 
 
architecture arc_datapathiobs of datapath_ddr2_iobs is
 
 
attribute syn_keep : boolean;  -- Using Syn_Keep Derictive
attribute syn_noprune : boolean;  -- Using syn_noprune Derictive
attribute syn_preserve : boolean;  -- Using syn_noprune Derictive
 
component s3_dqs_iob
port(
     clk            : in std_logic;
     clk180         : in std_logic;
     ddr_dqs_reset  : in std_logic;
     ddr_dqs_enable : in std_logic;
     ddr_dqs        : inout std_logic;
     dqs            : out std_logic
     );
end component;
 
 
        COMPONENT s3_ddr_iob
        PORT(
                write_data_falling : IN std_logic;
                write_data_rising : IN std_logic;
                read_dq_ce : IN std_logic;
                clk_rx : IN std_logic;
                clk90 : IN std_logic;
                clk270 : IN std_logic;
                write_en_val : IN std_logic;
                reset : IN std_logic;
                ddr_dq_inout : INOUT std_logic;
                read_data_in_rising : OUT std_logic;
                read_data_in_falling : OUT std_logic
                );
        END COMPONENT;
 
 
 
 
component ddr2_dm
port (
      ddr_dm       : out std_logic_vector(1 downto 0);
      mask_falling : in std_logic_vector(1 downto 0);
      mask_rising  : in std_logic_vector(1 downto 0);
      clk90        : in std_logic;
      clk270       : in std_logic
      );
end component;
 
 
component BUF
port (I : in std_logic;
      O : out std_logic);
end component;
 
 
component LUT4
   generic(
      INIT                           :  bit_vector(15 downto 0) := x"0000" );
   port(
      O                              :  out   STD_ULOGIC;
      I0                             :  in    STD_ULOGIC;
      I1                             :  in    STD_ULOGIC;
      I2                             :  in    STD_ULOGIC;
      I3                             :  in    STD_ULOGIC
      );
end component;
 
 
signal clk270       : std_logic;
signal clk180       : std_logic;
--signal ddr_dq_in    : std_logic_vector( 15 downto 0);
--attribute syn_keep of clk180 : signal is true; 
--attribute syn_keep of clk270 : signal is true; 
signal write_en_val_r : std_logic;
--PL
--signal write_en_val1_r : std_logic;
signal dqs_enable1 : std_logic;
signal dqs_reset1 : std_logic;
 
signal read_dq_dqs0_ce : std_logic;
signal read_dq_dqs1_ce : std_logic;
 
signal dqs0_in : std_logic;
signal dqs1_in : std_logic;
 
attribute syn_keep of dqs0_in      : signal is true;
attribute syn_keep of dqs_int_delay_in0      : signal is true;
attribute syn_keep of dqs_int_delay_in1      : signal is true;
 
signal dqs0_in_delay1 : std_logic;
signal dqs0_in_delay2 : std_logic;
signal dqs0_in_delay3 : std_logic;
signal dqs1_in_delay1 : std_logic;
signal dqs1_in_delay2 : std_logic;
signal dqs1_in_delay3 : std_logic;
 
begin
 
clk270  <=  not clk90;
clk180  <=  not clk;
 
dqs_enable1 <= dqs_enable;
 
dqs_reset1 <= dqs_reset;
 
 
 
--old ddr_dq_val <= ddr_dq_in;
 
ddr2_dm0 : ddr2_dm port map (
                             ddr_dm       => ddr_dm(1 downto 0),
                             mask_falling => data_mask_f(1 downto 0),
                             mask_rising  => data_mask_r(1 downto 0),
                             clk90        => clk90,
                             clk270       => clk270
                            );
 
process(clk90)
begin
 if clk90'event and clk90 = '0' then
  if reset90_r = '1' then
 
    write_en_val_r    <= '0';
--PL
--    write_en_val1_r   <= '0';
 
  else
 
     write_en_val_r  <= write_en_val;
--PL
--     write_en_val1_r  <= write_en_val1; 
 
  end if;
 end if;
end process;
 
--***********************************************************************
--    Read Data Capture Module Instantiations
--***********************************************************************
-- DQS IOB instantiations
--***********************************************************************
 
 
-- dqs_int_delay_in0  <=   dqs0_in ;
-- dqs_int_delay_in1  <=         dqs1_in ;
 
--dqs0_buf_delay : BUF port map (I  => dqs0_in, O  => dqs_int_delay_in0);
 
dqs0_lut_delay1 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs0_in,
             I2 => '0',
             I3 => '1',
             O  => dqs0_in_delay1
            );
 
dqs0_lut_delay2 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs0_in_delay1,
             I2 => '0',
             I3 => '1',
--             O  => dqs_int_delay_in0
             O  => dqs0_in_delay2
            );
 
dqs0_lut_delay3 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs0_in_delay2,
             I2 => '0',
             I3 => '1',
             O  => dqs0_in_delay3
            );
 
dqs0_lut_delay4 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs0_in_delay3,
             I2 => '0',
             I3 => '1',
             O  => dqs_int_delay_in0
            );
 
 
 
 
 
 
 
 
 
 
dqs1_lut_delay1 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs1_in,
             I2 => '0',
             I3 => '1',
             O  => dqs1_in_delay1
            );
 
dqs1_lut_delay2 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs1_in_delay1,
             I2 => '0',
             I3 => '1',
             O  => dqs1_in_delay2
            );
 
dqs1_lut_delay3 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs1_in_delay2,
             I2 => '0',
             I3 => '1',
             O  => dqs1_in_delay3
            );
 
dqs1_lut_delay4 :  LUT4  generic map (INIT => x"e2e2")
port map   ( I0 => '1',
             I1 => dqs1_in_delay3,
             I2 => '0',
             I3 => '1',
             O  => dqs_int_delay_in1
            );
 
 
 
 
 
 
 
 s3_dqs_iob0 : s3_dqs_iob port map (
                              clk            => clk,
                              clk180         => clk180,
                              ddr_dqs_reset  => dqs_reset1,
                              ddr_dqs_enable => dqs_enable1,
                              ddr_dqs        => ddr_dqs(0),
                              dqs            => dqs0_in
                                        );
 
 s3_dqs_iob1 : s3_dqs_iob port map (
                              clk            => clk,
                              clk180         => clk180,
                              ddr_dqs_reset  => dqs_reset1,
                              ddr_dqs_enable => dqs_enable1,
                              ddr_dqs        => ddr_dqs(1),
                              dqs            => dqs1_in
                             );
 
 
 
--******************************************************************************************************************************
-- DDR Data bit instantiations (-bits)
--******************************************************************************************************************************            
 
 
 
 
 
 
read_dq_dqs0_ce   <=  '1' ;
read_dq_dqs1_ce   <=  '1' ;
 
s3_ddr_iob0 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(0),
                                                        write_data_falling => write_data_falling(0),
                                                        write_data_rising  => write_data_rising(0),
--old                                                           read_data_in       => ddr_dq_in(0),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(0),
                           read_data_in_falling => ddr_dq_in_falling(0),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
 
s3_ddr_iob1 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(1),
                                                        write_data_falling => write_data_falling(1),
                                                        write_data_rising  => write_data_rising(1),
--old                                                           read_data_in       => ddr_dq_in(1),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(1),
                           read_data_in_falling => ddr_dq_in_falling(1),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob2 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(2),
                                                        write_data_falling => write_data_falling(2),
                                                        write_data_rising  => write_data_rising(2),
--old                                                           read_data_in       => ddr_dq_in(2),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(2),
                           read_data_in_falling => ddr_dq_in_falling(2),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob3 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(3),
                                                        write_data_falling => write_data_falling(3),
                                                        write_data_rising  => write_data_rising(3),
--old                                                           read_data_in       => ddr_dq_in(3),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(3),
                           read_data_in_falling => ddr_dq_in_falling(3),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob4 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(4),
                                                        write_data_falling => write_data_falling(4),
                                                        write_data_rising  => write_data_rising(4),
--old                                                           read_data_in       => ddr_dq_in(4),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(4),
                           read_data_in_falling => ddr_dq_in_falling(4),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob5 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(5),
                                                        write_data_falling => write_data_falling(5),
                                                        write_data_rising  => write_data_rising(5),
--old                                                           read_data_in       => ddr_dq_in(5),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(5),
                           read_data_in_falling => ddr_dq_in_falling(5),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob6 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(6),
                                                        write_data_falling => write_data_falling(6),
                                                        write_data_rising  => write_data_rising(6),
--old                                                           read_data_in       => ddr_dq_in(6),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(6),
                           read_data_in_falling => ddr_dq_in_falling(6),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob7 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(7),
                                                        write_data_falling => write_data_falling(7),
                                                        write_data_rising  => write_data_rising(7),
--old                                                           read_data_in       => ddr_dq_in(7),
                           read_dq_ce => read_dq_dqs0_ce,
                           clk_rx => dqs0_in,
                           read_data_in_rising => ddr_dq_in_rising(7),
                           read_data_in_falling => ddr_dq_in_falling(7),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob8  : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(8),
                                                        write_data_falling => write_data_falling(8),
                                                        write_data_rising  => write_data_rising(8),
--old                                                           read_data_in       => ddr_dq_in(8),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(8),
                           read_data_in_falling => ddr_dq_in_falling(8),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob9 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(9),
                                                        write_data_falling => write_data_falling(9),
                                                        write_data_rising  => write_data_rising(9),
--old                                                           read_data_in       => ddr_dq_in(9),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(9),
                           read_data_in_falling => ddr_dq_in_falling(9),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
 
s3_ddr_iob10  : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(10),
                                                        write_data_falling => write_data_falling(10),
                                                        write_data_rising  => write_data_rising(10),
--old                                                           read_data_in       => ddr_dq_in(10),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(10),
                           read_data_in_falling => ddr_dq_in_falling(10),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
 
s3_ddr_iob11 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(11),
                                                        write_data_falling => write_data_falling(11),
                                                        write_data_rising  => write_data_rising(11),
--old                                                           read_data_in       => ddr_dq_in(11),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(11),
                           read_data_in_falling => ddr_dq_in_falling(11),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob12  : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(12),
                                                        write_data_falling => write_data_falling(12),
                                                        write_data_rising  => write_data_rising(12),
--old                                                           read_data_in       => ddr_dq_in(12),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(12),
                           read_data_in_falling => ddr_dq_in_falling(12),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob13  : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(13),
                                                        write_data_falling => write_data_falling(13),
                                                        write_data_rising  => write_data_rising(13),
--old                                                           read_data_in       => ddr_dq_in(13),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(13),
                           read_data_in_falling => ddr_dq_in_falling(13),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob14 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(14),
                                                        write_data_falling => write_data_falling(14),
                                                        write_data_rising  => write_data_rising(14),
--old                                                           read_data_in       => ddr_dq_in(14),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(14),
                           read_data_in_falling => ddr_dq_in_falling(14),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
s3_ddr_iob15 : s3_ddr_iob  port map(
                                                        ddr_dq_inout       => ddr_dq(15),
                                                        write_data_falling => write_data_falling(15),
                                                        write_data_rising  => write_data_rising(15),
--old                                                           read_data_in       => ddr_dq_in(15),
                           read_dq_ce => read_dq_dqs1_ce,
                           clk_rx => dqs1_in,
                           read_data_in_rising => ddr_dq_in_rising(15),
                           read_data_in_falling => ddr_dq_in_falling(15),
                                                        clk90              => clk90,
                                                        clk270             => clk270,
                                                        write_en_val       => write_en_val_r,
                                                        reset              => reset90_r
                                                        );
 
 
 
 
end arc_datapathiobs;

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Subversion Repositories pulse_processing_algorithm

[/] [pulse_processing_algorithm/] [datapath_ddr2_iobs.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	panda_emc	`--*********************************************************************`
2			`-- DDR 72 Bit Controller DATA PATH for LEFT RIGHT Pins`
3
4			`-- In the current DATA PATH logic DATA CAPTURE part was modified.`
5			`-- The below changes were made to reduce the resources in`
6			`-- the data capture`
7
8			`-- in the current architecture data ( dq ) from ddr memory`
9			`-- directly stored into the FIFO's.`
10
11			`-- Architectural changes :`
12
13			`-- Used only TWO FIFOs ( instead of FOUR FIFOs )`
14			`-- Used Single col ( col0 ) dqs_delayed_col signals`
15			`-- Used Gray Counters for write and read pointers of the FIFOs`
16
17			`-- fbit stage is removed from ddr1_dqbit module ( in the data capture )`
18			`-- dq_clk stage was removed`
19			`-- dqs_clk_div logic was removed`
20			`-- ddr1_transfer_done logic was removed`
21			`-- data valid signals registering in clk90 domain was removed`
22
23			`-- fifo_0 and fifo_1 wr_addr was double registered in clk90 domain`
24			`-- only fifo_0 and fifo_1 empty signals were used for read_data_valid_1 logic`
25			`-- write enable for the FIFOs derived from rst_dqs_div signal`
26
27
28			`-- Code revised by : Narayana Murty.`
29			`-- Date : Nov 18, 2003.`
30
31			`--*********************************************************************`
32
33
34			`library ieee;`
35			`use ieee.std_logic_1164.all;`
36			`use ieee.std_logic_unsigned.all;`
37			`--library synplify;`
38			`--use synplify.attributes.all;`
39			`--`
40			`-- pragma translate_off`
41			`library UNISIM;`
42			`use UNISIM.VCOMPONENTS.ALL;`
43			`-- pragma translate_on`
44			`--`
45
46
47
48
49
50			`entity datapath_ddr2_iobs is`
51			`port(`
52			`clk : in std_logic;`
53			`clk90 : in std_logic;`
54			`reset90_r : in std_logic;`
55			`dqs_reset : in std_logic;`
56			`dqs_enable : in std_logic;`
57			`ddr_dqs : inout std_logic_vector(1 downto 0);`
58			`ddr_dq : inout std_logic_vector(15 downto 0);`
59			`write_data_falling: in std_logic_vector(15 downto 0);`
60			`write_data_rising : in std_logic_vector(15 downto 0);`
61			`write_en_val : in std_logic;`
62			`write_en_val1 : in std_logic;`
63			`data_mask_f : in std_logic_vector(1 downto 0);`
64			`data_mask_r : in std_logic_vector(1 downto 0);`
65			`dqs_int_delay_in0 : out std_logic;`
66			`dqs_int_delay_in1 : out std_logic;`
67			`ddr_dq_in_rising : out std_logic_vector(15 downto 0);`
68			`ddr_dq_in_falling : out std_logic_vector(15 downto 0);`
69			`--old ddr_dq_val : out std_logic_vector(15 downto 0);`
70			`ddr_dm : out std_logic_vector(1 downto 0)`
71			`);`
72			`end datapath_ddr2_iobs;`
73
74
75			`architecture arc_datapathiobs of datapath_ddr2_iobs is`
76
77
78			`attribute syn_keep : boolean; -- Using Syn_Keep Derictive`
79			`attribute syn_noprune : boolean; -- Using syn_noprune Derictive`
80			`attribute syn_preserve : boolean; -- Using syn_noprune Derictive`
81
82			`component s3_dqs_iob`
83			`port(`
84			`clk : in std_logic;`
85			`clk180 : in std_logic;`
86			`ddr_dqs_reset : in std_logic;`
87			`ddr_dqs_enable : in std_logic;`
88			`ddr_dqs : inout std_logic;`
89			`dqs : out std_logic`
90			`);`
91			`end component;`
92
93
94			`COMPONENT s3_ddr_iob`
95			`PORT(`
96			`write_data_falling : IN std_logic;`
97			`write_data_rising : IN std_logic;`
98			`read_dq_ce : IN std_logic;`
99			`clk_rx : IN std_logic;`
100			`clk90 : IN std_logic;`
101			`clk270 : IN std_logic;`
102			`write_en_val : IN std_logic;`
103			`reset : IN std_logic;`
104			`ddr_dq_inout : INOUT std_logic;`
105			`read_data_in_rising : OUT std_logic;`
106			`read_data_in_falling : OUT std_logic`
107			`);`
108			`END COMPONENT;`
109
110
111
112
113			`component ddr2_dm`
114			`port (`
115			`ddr_dm : out std_logic_vector(1 downto 0);`
116			`mask_falling : in std_logic_vector(1 downto 0);`
117			`mask_rising : in std_logic_vector(1 downto 0);`
118			`clk90 : in std_logic;`
119			`clk270 : in std_logic`
120			`);`
121			`end component;`
122
123
124			`component BUF`
125			`port (I : in std_logic;`
126			`O : out std_logic);`
127			`end component;`
128
129
130			`component LUT4`
131			`generic(`
132			`INIT : bit_vector(15 downto 0) := x"0000" );`
133			`port(`
134			`O : out STD_ULOGIC;`
135			`I0 : in STD_ULOGIC;`
136			`I1 : in STD_ULOGIC;`
137			`I2 : in STD_ULOGIC;`
138			`I3 : in STD_ULOGIC`
139			`);`
140			`end component;`
141
142
143			`signal clk270 : std_logic;`
144			`signal clk180 : std_logic;`
145			`--signal ddr_dq_in : std_logic_vector( 15 downto 0);`
146			`--attribute syn_keep of clk180 : signal is true;`
147			`--attribute syn_keep of clk270 : signal is true;`
148			`signal write_en_val_r : std_logic;`
149			`--PL`
150			`--signal write_en_val1_r : std_logic;`
151			`signal dqs_enable1 : std_logic;`
152			`signal dqs_reset1 : std_logic;`
153
154			`signal read_dq_dqs0_ce : std_logic;`
155			`signal read_dq_dqs1_ce : std_logic;`
156
157			`signal dqs0_in : std_logic;`
158			`signal dqs1_in : std_logic;`
159
160			`attribute syn_keep of dqs0_in : signal is true;`
161			`attribute syn_keep of dqs_int_delay_in0 : signal is true;`
162			`attribute syn_keep of dqs_int_delay_in1 : signal is true;`
163
164			`signal dqs0_in_delay1 : std_logic;`
165			`signal dqs0_in_delay2 : std_logic;`
166			`signal dqs0_in_delay3 : std_logic;`
167			`signal dqs1_in_delay1 : std_logic;`
168			`signal dqs1_in_delay2 : std_logic;`
169			`signal dqs1_in_delay3 : std_logic;`
170
171			`begin`
172
173			`clk270 <= not clk90;`
174			`clk180 <= not clk;`
175
176			`dqs_enable1 <= dqs_enable;`
177
178			`dqs_reset1 <= dqs_reset;`
179
180
181
182			`--old ddr_dq_val <= ddr_dq_in;`
183
184			`ddr2_dm0 : ddr2_dm port map (`
185			`ddr_dm => ddr_dm(1 downto 0),`
186			`mask_falling => data_mask_f(1 downto 0),`
187			`mask_rising => data_mask_r(1 downto 0),`
188			`clk90 => clk90,`
189			`clk270 => clk270`
190			`);`
191
192			`process(clk90)`
193			`begin`
194			`if clk90'event and clk90 = '0' then`
195			`if reset90_r = '1' then`
196
197			`write_en_val_r <= '0';`
198			`--PL`
199			`-- write_en_val1_r <= '0';`
200
201			`else`
202
203			`write_en_val_r <= write_en_val;`
204			`--PL`
205			`-- write_en_val1_r <= write_en_val1;`
206
207			`end if;`
208			`end if;`
209			`end process;`
210
211			`--***********************************************************************`
212			`-- Read Data Capture Module Instantiations`
213			`--***********************************************************************`
214			`-- DQS IOB instantiations`
215			`--***********************************************************************`
216
217
218			`-- dqs_int_delay_in0 <= dqs0_in ;`
219			`-- dqs_int_delay_in1 <= dqs1_in ;`
220
221			`--dqs0_buf_delay : BUF port map (I => dqs0_in, O => dqs_int_delay_in0);`
222
223			`dqs0_lut_delay1 : LUT4 generic map (INIT => x"e2e2")`
224			`port map ( I0 => '1',`
225			`I1 => dqs0_in,`
226			`I2 => '0',`
227			`I3 => '1',`
228			`O => dqs0_in_delay1`
229			`);`
230
231			`dqs0_lut_delay2 : LUT4 generic map (INIT => x"e2e2")`
232			`port map ( I0 => '1',`
233			`I1 => dqs0_in_delay1,`
234			`I2 => '0',`
235			`I3 => '1',`
236			`-- O => dqs_int_delay_in0`
237			`O => dqs0_in_delay2`
238			`);`
239
240			`dqs0_lut_delay3 : LUT4 generic map (INIT => x"e2e2")`
241			`port map ( I0 => '1',`
242			`I1 => dqs0_in_delay2,`
243			`I2 => '0',`
244			`I3 => '1',`
245			`O => dqs0_in_delay3`
246			`);`
247
248			`dqs0_lut_delay4 : LUT4 generic map (INIT => x"e2e2")`
249			`port map ( I0 => '1',`
250			`I1 => dqs0_in_delay3,`
251			`I2 => '0',`
252			`I3 => '1',`
253			`O => dqs_int_delay_in0`
254			`);`
255
256
257
258
259
260
261
262
263
264
265			`dqs1_lut_delay1 : LUT4 generic map (INIT => x"e2e2")`
266			`port map ( I0 => '1',`
267			`I1 => dqs1_in,`
268			`I2 => '0',`
269			`I3 => '1',`
270			`O => dqs1_in_delay1`
271			`);`
272
273			`dqs1_lut_delay2 : LUT4 generic map (INIT => x"e2e2")`
274			`port map ( I0 => '1',`
275			`I1 => dqs1_in_delay1,`
276			`I2 => '0',`
277			`I3 => '1',`
278			`O => dqs1_in_delay2`
279			`);`
280
281			`dqs1_lut_delay3 : LUT4 generic map (INIT => x"e2e2")`
282			`port map ( I0 => '1',`
283			`I1 => dqs1_in_delay2,`
284			`I2 => '0',`
285			`I3 => '1',`
286			`O => dqs1_in_delay3`
287			`);`
288
289			`dqs1_lut_delay4 : LUT4 generic map (INIT => x"e2e2")`
290			`port map ( I0 => '1',`
291			`I1 => dqs1_in_delay3,`
292			`I2 => '0',`
293			`I3 => '1',`
294			`O => dqs_int_delay_in1`
295			`);`
296
297
298
299
300
301
302
303			`s3_dqs_iob0 : s3_dqs_iob port map (`
304			`clk => clk,`
305			`clk180 => clk180,`
306			`ddr_dqs_reset => dqs_reset1,`
307			`ddr_dqs_enable => dqs_enable1,`
308			`ddr_dqs => ddr_dqs(0),`
309			`dqs => dqs0_in`
310			`);`
311
312			`s3_dqs_iob1 : s3_dqs_iob port map (`
313			`clk => clk,`
314			`clk180 => clk180,`
315			`ddr_dqs_reset => dqs_reset1,`
316			`ddr_dqs_enable => dqs_enable1,`
317			`ddr_dqs => ddr_dqs(1),`
318			`dqs => dqs1_in`
319			`);`
320
321
322
323			`--******************************************************************************************************************************`
324			`-- DDR Data bit instantiations (-bits)`
325			`--******************************************************************************************************************************`
326
327
328
329
330
331
332			`read_dq_dqs0_ce <= '1' ;`
333			`read_dq_dqs1_ce <= '1' ;`
334
335			`s3_ddr_iob0 : s3_ddr_iob port map(`
336			`ddr_dq_inout => ddr_dq(0),`
337			`write_data_falling => write_data_falling(0),`
338			`write_data_rising => write_data_rising(0),`
339			`--old read_data_in => ddr_dq_in(0),`
340			`read_dq_ce => read_dq_dqs0_ce,`
341			`clk_rx => dqs0_in,`
342			`read_data_in_rising => ddr_dq_in_rising(0),`
343			`read_data_in_falling => ddr_dq_in_falling(0),`
344			`clk90 => clk90,`
345			`clk270 => clk270,`
346			`write_en_val => write_en_val_r,`
347			`reset => reset90_r`
348			`);`
349
350
351			`s3_ddr_iob1 : s3_ddr_iob port map(`
352			`ddr_dq_inout => ddr_dq(1),`
353			`write_data_falling => write_data_falling(1),`
354			`write_data_rising => write_data_rising(1),`
355			`--old read_data_in => ddr_dq_in(1),`
356			`read_dq_ce => read_dq_dqs0_ce,`
357			`clk_rx => dqs0_in,`
358			`read_data_in_rising => ddr_dq_in_rising(1),`
359			`read_data_in_falling => ddr_dq_in_falling(1),`
360			`clk90 => clk90,`
361			`clk270 => clk270,`
362			`write_en_val => write_en_val_r,`
363			`reset => reset90_r`
364			`);`
365
366			`s3_ddr_iob2 : s3_ddr_iob port map(`
367			`ddr_dq_inout => ddr_dq(2),`
368			`write_data_falling => write_data_falling(2),`
369			`write_data_rising => write_data_rising(2),`
370			`--old read_data_in => ddr_dq_in(2),`
371			`read_dq_ce => read_dq_dqs0_ce,`
372			`clk_rx => dqs0_in,`
373			`read_data_in_rising => ddr_dq_in_rising(2),`
374			`read_data_in_falling => ddr_dq_in_falling(2),`
375			`clk90 => clk90,`
376			`clk270 => clk270,`
377			`write_en_val => write_en_val_r,`
378			`reset => reset90_r`
379			`);`
380
381			`s3_ddr_iob3 : s3_ddr_iob port map(`
382			`ddr_dq_inout => ddr_dq(3),`
383			`write_data_falling => write_data_falling(3),`
384			`write_data_rising => write_data_rising(3),`
385			`--old read_data_in => ddr_dq_in(3),`
386			`read_dq_ce => read_dq_dqs0_ce,`
387			`clk_rx => dqs0_in,`
388			`read_data_in_rising => ddr_dq_in_rising(3),`
389			`read_data_in_falling => ddr_dq_in_falling(3),`
390			`clk90 => clk90,`
391			`clk270 => clk270,`
392			`write_en_val => write_en_val_r,`
393			`reset => reset90_r`
394			`);`
395
396			`s3_ddr_iob4 : s3_ddr_iob port map(`
397			`ddr_dq_inout => ddr_dq(4),`
398			`write_data_falling => write_data_falling(4),`
399			`write_data_rising => write_data_rising(4),`
400			`--old read_data_in => ddr_dq_in(4),`
401			`read_dq_ce => read_dq_dqs0_ce,`
402			`clk_rx => dqs0_in,`
403			`read_data_in_rising => ddr_dq_in_rising(4),`
404			`read_data_in_falling => ddr_dq_in_falling(4),`
405			`clk90 => clk90,`
406			`clk270 => clk270,`
407			`write_en_val => write_en_val_r,`
408			`reset => reset90_r`
409			`);`
410
411			`s3_ddr_iob5 : s3_ddr_iob port map(`
412			`ddr_dq_inout => ddr_dq(5),`
413			`write_data_falling => write_data_falling(5),`
414			`write_data_rising => write_data_rising(5),`
415			`--old read_data_in => ddr_dq_in(5),`
416			`read_dq_ce => read_dq_dqs0_ce,`
417			`clk_rx => dqs0_in,`
418			`read_data_in_rising => ddr_dq_in_rising(5),`
419			`read_data_in_falling => ddr_dq_in_falling(5),`
420			`clk90 => clk90,`
421			`clk270 => clk270,`
422			`write_en_val => write_en_val_r,`
423			`reset => reset90_r`
424			`);`
425
426			`s3_ddr_iob6 : s3_ddr_iob port map(`
427			`ddr_dq_inout => ddr_dq(6),`
428			`write_data_falling => write_data_falling(6),`
429			`write_data_rising => write_data_rising(6),`
430			`--old read_data_in => ddr_dq_in(6),`
431			`read_dq_ce => read_dq_dqs0_ce,`
432			`clk_rx => dqs0_in,`
433			`read_data_in_rising => ddr_dq_in_rising(6),`
434			`read_data_in_falling => ddr_dq_in_falling(6),`
435			`clk90 => clk90,`
436			`clk270 => clk270,`
437			`write_en_val => write_en_val_r,`
438			`reset => reset90_r`
439			`);`
440
441			`s3_ddr_iob7 : s3_ddr_iob port map(`
442			`ddr_dq_inout => ddr_dq(7),`
443			`write_data_falling => write_data_falling(7),`
444			`write_data_rising => write_data_rising(7),`
445			`--old read_data_in => ddr_dq_in(7),`
446			`read_dq_ce => read_dq_dqs0_ce,`
447			`clk_rx => dqs0_in,`
448			`read_data_in_rising => ddr_dq_in_rising(7),`
449			`read_data_in_falling => ddr_dq_in_falling(7),`
450			`clk90 => clk90,`
451			`clk270 => clk270,`
452			`write_en_val => write_en_val_r,`
453			`reset => reset90_r`
454			`);`
455
456			`s3_ddr_iob8 : s3_ddr_iob port map(`
457			`ddr_dq_inout => ddr_dq(8),`
458			`write_data_falling => write_data_falling(8),`
459			`write_data_rising => write_data_rising(8),`
460			`--old read_data_in => ddr_dq_in(8),`
461			`read_dq_ce => read_dq_dqs1_ce,`
462			`clk_rx => dqs1_in,`
463			`read_data_in_rising => ddr_dq_in_rising(8),`
464			`read_data_in_falling => ddr_dq_in_falling(8),`
465			`clk90 => clk90,`
466			`clk270 => clk270,`
467			`write_en_val => write_en_val_r,`
468			`reset => reset90_r`
469			`);`
470
471			`s3_ddr_iob9 : s3_ddr_iob port map(`
472			`ddr_dq_inout => ddr_dq(9),`
473			`write_data_falling => write_data_falling(9),`
474			`write_data_rising => write_data_rising(9),`
475			`--old read_data_in => ddr_dq_in(9),`
476			`read_dq_ce => read_dq_dqs1_ce,`
477			`clk_rx => dqs1_in,`
478			`read_data_in_rising => ddr_dq_in_rising(9),`
479			`read_data_in_falling => ddr_dq_in_falling(9),`
480			`clk90 => clk90,`
481			`clk270 => clk270,`
482			`write_en_val => write_en_val_r,`
483			`reset => reset90_r`
484			`);`
485
486
487			`s3_ddr_iob10 : s3_ddr_iob port map(`
488			`ddr_dq_inout => ddr_dq(10),`
489			`write_data_falling => write_data_falling(10),`
490			`write_data_rising => write_data_rising(10),`
491			`--old read_data_in => ddr_dq_in(10),`
492			`read_dq_ce => read_dq_dqs1_ce,`
493			`clk_rx => dqs1_in,`
494			`read_data_in_rising => ddr_dq_in_rising(10),`
495			`read_data_in_falling => ddr_dq_in_falling(10),`
496			`clk90 => clk90,`
497			`clk270 => clk270,`
498			`write_en_val => write_en_val_r,`
499			`reset => reset90_r`
500			`);`
501
502
503			`s3_ddr_iob11 : s3_ddr_iob port map(`
504			`ddr_dq_inout => ddr_dq(11),`
505			`write_data_falling => write_data_falling(11),`
506			`write_data_rising => write_data_rising(11),`
507			`--old read_data_in => ddr_dq_in(11),`
508			`read_dq_ce => read_dq_dqs1_ce,`
509			`clk_rx => dqs1_in,`
510			`read_data_in_rising => ddr_dq_in_rising(11),`
511			`read_data_in_falling => ddr_dq_in_falling(11),`
512			`clk90 => clk90,`
513			`clk270 => clk270,`
514			`write_en_val => write_en_val_r,`
515			`reset => reset90_r`
516			`);`
517
518			`s3_ddr_iob12 : s3_ddr_iob port map(`
519			`ddr_dq_inout => ddr_dq(12),`
520			`write_data_falling => write_data_falling(12),`
521			`write_data_rising => write_data_rising(12),`
522			`--old read_data_in => ddr_dq_in(12),`
523			`read_dq_ce => read_dq_dqs1_ce,`
524			`clk_rx => dqs1_in,`
525			`read_data_in_rising => ddr_dq_in_rising(12),`
526			`read_data_in_falling => ddr_dq_in_falling(12),`
527			`clk90 => clk90,`
528			`clk270 => clk270,`
529			`write_en_val => write_en_val_r,`
530			`reset => reset90_r`
531			`);`
532
533			`s3_ddr_iob13 : s3_ddr_iob port map(`
534			`ddr_dq_inout => ddr_dq(13),`
535			`write_data_falling => write_data_falling(13),`
536			`write_data_rising => write_data_rising(13),`
537			`--old read_data_in => ddr_dq_in(13),`
538			`read_dq_ce => read_dq_dqs1_ce,`
539			`clk_rx => dqs1_in,`
540			`read_data_in_rising => ddr_dq_in_rising(13),`
541			`read_data_in_falling => ddr_dq_in_falling(13),`
542			`clk90 => clk90,`
543			`clk270 => clk270,`
544			`write_en_val => write_en_val_r,`
545			`reset => reset90_r`
546			`);`
547
548			`s3_ddr_iob14 : s3_ddr_iob port map(`
549			`ddr_dq_inout => ddr_dq(14),`
550			`write_data_falling => write_data_falling(14),`
551			`write_data_rising => write_data_rising(14),`
552			`--old read_data_in => ddr_dq_in(14),`
553			`read_dq_ce => read_dq_dqs1_ce,`
554			`clk_rx => dqs1_in,`
555			`read_data_in_rising => ddr_dq_in_rising(14),`
556			`read_data_in_falling => ddr_dq_in_falling(14),`
557			`clk90 => clk90,`
558			`clk270 => clk270,`
559			`write_en_val => write_en_val_r,`
560			`reset => reset90_r`
561			`);`
562
563			`s3_ddr_iob15 : s3_ddr_iob port map(`
564			`ddr_dq_inout => ddr_dq(15),`
565			`write_data_falling => write_data_falling(15),`
566			`write_data_rising => write_data_rising(15),`
567			`--old read_data_in => ddr_dq_in(15),`
568			`read_dq_ce => read_dq_dqs1_ce,`
569			`clk_rx => dqs1_in,`
570			`read_data_in_rising => ddr_dq_in_rising(15),`
571			`read_data_in_falling => ddr_dq_in_falling(15),`
572			`clk90 => clk90,`
573			`clk270 => clk270,`
574			`write_en_val => write_en_val_r,`
575			`reset => reset90_r`
576			`);`
577
578
579
580
581			`end arc_datapathiobs;`