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--******************************************************************************

--

--  Xilinx, Inc. 2002                 www.xilinx.com

--

--

--*******************************************************************************

--

--  File name :       ddr2_data_path.vhd

--

--  Description :     This module comprises the write and read data paths for the

--                    DDR1 memory interface. The write data along with write enable 

--                    signals are forwarded to the DDR IOB FFs. The read data is 

--                    captured in CLB FFs and finally input to FIFOs.

-- 

--                    

--  Date - revision : 10/16/2003

--

--

--

--*****************************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

--library synplify; 

--use synplify.attributes.all;

--

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

entity ddr2_data_path is

port(

     user_input_data    : in std_logic_vector(31 downto 0);

     clk                : in std_logic;

     clk180             : IN std_logic;

     clk90              : in std_logic;

     reset              : in std_logic;

     reset90            : in std_logic;

     reset180           : in std_logic;

     reset270           : in std_logic;

     write_enable       : in std_logic;

     rst_dqs_div_in     : in std_logic;

     delay_sel          : in std_logic_vector(4 downto 0);

     dqs_int_delay_in0  : in std_logic;

     dqs_int_delay_in1  : in std_logic;

--     dq_in              : in std_logic_vector(15 downto 0);       

     dq_in_rising              : in std_logic_vector(15 downto 0);

     dq_in_falling              : in std_logic_vector(15 downto 0);

     u_data_val         : out std_logic;

     user_output_data   : out std_logic_vector(31 downto 0);

     write_en_val       : out std_logic;

     write_en_val1      : out std_logic;

     reset90_r_val      : out std_logic;

     data_mask_f        : out std_logic_vector(1 downto 0);

     data_mask_r        : out std_logic_vector(1 downto 0);

     write_data_falling : out std_logic_vector(15 downto 0);

     write_data_rising  : out std_logic_vector(15 downto 0);

     test_fifo_wr_addr: out std_logic_vector(15 downto 0)

     );

end ddr2_data_path;

architecture arc_ddr2_data_path of ddr2_data_path is

component data_read

port(

     clk90              : in std_logic;

     reset90_r          : in std_logic;

--old     ddr_dq_in          : in std_logic_vector(15 downto 0);   

     ddr_dq_in_rising   : in std_logic_vector(15 downto 0);

     ddr_dq_in_falling  : in std_logic_vector(15 downto 0);

     read_valid_data_1  : in std_logic;

     fifo_00_wr_en       : in std_logic;

     fifo_10_wr_en       : in std_logic;

     fifo_01_wr_en       : in std_logic;

     fifo_11_wr_en       : in std_logic;

     fifo_00_wr_addr    : in std_logic_vector(3 downto 0);

     fifo_01_wr_addr    : in std_logic_vector(3 downto 0);

     fifo_10_wr_addr    : in std_logic_vector(3 downto 0);

     fifo_11_wr_addr    : in std_logic_vector(3 downto 0);

--      dqs0_delayed_col1  : in std_logic;

--      dqs1_delayed_col1  : in std_logic;

        dqs0_delayed_col0  : in std_logic;

        dqs1_delayed_col0  : in std_logic;

        user_output_data   : out std_logic_vector(31 downto 0);

        fifo0_rd_addr_val: out std_logic_vector(3 downto 0);

     fifo1_rd_addr_val: out std_logic_vector(3 downto 0)

     );

end component;

component data_read_controller

port(

     clk90              : in std_logic;

     clk180              : in std_logic;

     reset_r            : in std_logic;

     reset90_r          : in std_logic;

     rst_dqs_div_in     : in std_logic;

     delay_sel          : in std_logic_vector(4 downto 0);

     dqs_int_delay_in0  : in std_logic;

     dqs_int_delay_in1  : in std_logic;

     fifo0_rd_addr      : in std_logic_vector(3 downto 0);

     fifo1_rd_addr      : in std_logic_vector(3 downto 0);

     u_data_val         : out std_logic;

     read_valid_data_1_val  : out std_logic;

     fifo_00_wr_en_val  : out std_logic;

     fifo_10_wr_en_val                  : out std_logic;

     fifo_01_wr_en_val                  : out std_logic;

     fifo_11_wr_en_val                  : out std_logic;

     fifo_00_wr_addr_val    : out std_logic_vector(3 downto 0);

     fifo_01_wr_addr_val    : out std_logic_vector(3 downto 0);

     fifo_10_wr_addr_val    : out std_logic_vector(3 downto 0);

     fifo_11_wr_addr_val    : out std_logic_vector(3 downto 0);

        dqs0_delayed_col0_val  : out std_logic;

        dqs1_delayed_col0_val  : out std_logic

--      dqs0_delayed_col1_val  : out std_logic;

--      dqs1_delayed_col1_val  : out std_logic

      );

end component;

component data_write

port(

     user_input_data    : in std_logic_vector(31 downto 0);

     clk90              : in std_logic;

     reset90_r          : in std_logic;

     reset270_r         : in std_logic;

     write_enable       : in std_logic;

     write_en_val       : out std_logic;

     write_en_val1      : out std_logic;

     write_data_falling : out std_logic_vector(15 downto 0);

     write_data_rising  : out std_logic_vector(15 downto 0);

     data_mask_f        : out std_logic_vector(1 downto 0);

     data_mask_r        : out std_logic_vector(1 downto 0)

     );

end component;

component data_path_rst

port(

     clk                : in std_logic;

     clk180             : in std_logic;

     clk90              : in std_logic;

     reset              : in std_logic;

     reset90            : in std_logic;

     reset180           : in std_logic;

     reset270           : in std_logic;

     reset_r            : out std_logic;

     reset90_r          : out std_logic;

     reset90_r1         : out std_logic;

     reset180_r         : out std_logic;

     reset270_r         : out std_logic

    );

end component;

signal reset_r          : std_logic;

signal reset90_r        : std_logic;

signal reset90_r1       : std_logic;

signal reset180_r       : std_logic;

signal reset270_r       : std_logic;

 signal fifo0_rd_addr    : std_logic_vector(3 downto 0);

 signal fifo1_rd_addr    : std_logic_vector(3 downto 0);

 signal read_valid_data_1  : std_logic;

 signal fifo_00_wr_addr    : std_logic_vector(3 downto 0);

 signal fifo_01_wr_addr    : std_logic_vector(3 downto 0);

 signal fifo_10_wr_addr    : std_logic_vector(3 downto 0);

 signal fifo_11_wr_addr    : std_logic_vector(3 downto 0);

 signal fifo_00_wr_en                   :  std_logic;

 signal fifo_10_wr_en                   :  std_logic;

 signal fifo_01_wr_en                   :  std_logic;

 signal fifo_11_wr_en                   :  std_logic;

-- signal dqs0_delayed_col1  :  std_logic;

-- signal dqs1_delayed_col1  :  std_logic;

 signal dqs0_delayed_col0  :  std_logic;

 signal dqs1_delayed_col0  :  std_logic;

   Function to_std_logic(X: in Boolean) return Std_Logic is

   variable ret : std_logic;

   begin

   if x then ret := '1';  else ret := '0'; end if;

   return ret;

   end to_std_logic;

attribute syn_keep : boolean;  -- Using Syn_Keep Derictive

--signal tclk180_fifo_01_wr_en: std_logic;

--signal tclk180_fifo_01_wr_en_delay1: std_logic;

--signal tclk180_fifo_01_wr_en_delay2: std_logic;

--signal tclk180_fifo_01_wr_en_delay3: std_logic;

--signal tclk180_fifo_01_wr_en_delay4: std_logic;

--signal tclk180_fifo_01_wr_en_delay5: std_logic;

--signal tclk180_fifo_01_wr_en_delay6: std_logic;

--signal tclk180_fifo_01_wr_en_delay7: std_logic;

--signal tclk180_fifo_01_wr_en_delay8: std_logic;

--signal tclk180_fifo_01_wr_en_delay9: std_logic;

--signal tclk180_fifo_01_wr_en_end_pulse: std_logic;

--signal tclk180_fifo_01_00_neq_flag: std_logic;

--signal tclk180_fifo_11_wr_en: std_logic;

--signal tclk180_fifo_11_wr_en_delay1: std_logic;

--signal tclk180_fifo_11_wr_en_delay2: std_logic;

--signal tclk180_fifo_11_wr_en_delay3: std_logic;

--signal tclk180_fifo_11_wr_en_delay4: std_logic;

--signal tclk180_fifo_11_wr_en_delay5: std_logic;

--signal tclk180_fifo_11_wr_en_delay6: std_logic;

--signal tclk180_fifo_11_wr_en_delay7: std_logic;

--signal tclk180_fifo_11_wr_en_delay8: std_logic;

--signal tclk180_fifo_11_wr_en_delay9: std_logic;

--signal tclk180_fifo_11_wr_en_end_pulse: std_logic;

--PL: om een warning te lozen

--signal tclk180_fifo_11_10_neq_flag: std_logic;

--attribute syn_keep of tclk180_fifo_01_wr_en_end_pulse : signal is true;

--attribute syn_keep of tclk180_fifo_01_00_neq_flag : signal is true;

--PL: om een warning te lozen

--attribute syn_keep of tclk180_fifo_11_wr_en_end_pulse : signal is true;

--PL: om een warning te lozen

--attribute syn_keep of tclk180_fifo_11_10_neq_flag : signal is true;

 begin

-- test

--PL alles commentaar want dit zijn 2 schuifregisters naar nergens

test_fifo_logic: process(clk180)

        begin

--                      if rising_edge (clk180) then 

--                      tclk180_fifo_01_wr_en            <= fifo_01_wr_en ;

--                      tclk180_fifo_01_wr_en_delay1     <= tclk180_fifo_01_wr_en ;

--                      tclk180_fifo_01_wr_en_delay2     <= tclk180_fifo_01_wr_en_delay1 ;

--                      tclk180_fifo_01_wr_en_delay3     <= tclk180_fifo_01_wr_en_delay2 ;

--                      tclk180_fifo_01_wr_en_delay4     <= tclk180_fifo_01_wr_en_delay3 ;

--                      tclk180_fifo_01_wr_en_delay5     <= tclk180_fifo_01_wr_en_delay4 ;

--                      tclk180_fifo_01_wr_en_delay6     <= tclk180_fifo_01_wr_en_delay5 ;

--                      tclk180_fifo_01_wr_en_delay7     <= tclk180_fifo_01_wr_en_delay6 ;

--                      tclk180_fifo_01_wr_en_delay8     <= tclk180_fifo_01_wr_en_delay7 ;

--                      tclk180_fifo_01_wr_en_delay9     <= tclk180_fifo_01_wr_en_delay8 ;

--                      tclk180_fifo_01_wr_en_end_pulse  <= tclk180_fifo_01_wr_en_delay9 and not tclk180_fifo_01_wr_en_delay8;

--              end if;

--PL: om een warning te lozen

--      if rising_edge (clk180) then 

--              tclk180_fifo_01_00_neq_flag      <=  tclk180_fifo_01_wr_en_end_pulse and to_std_logic( fifo_01_wr_addr /= fifo_00_wr_addr)  ; 

--      end if;

--      if rising_edge (clk180) then 

--              tclk180_fifo_11_wr_en            <= fifo_11_wr_en ;

--              tclk180_fifo_11_wr_en_delay1     <= tclk180_fifo_11_wr_en ;

--              tclk180_fifo_11_wr_en_delay2     <= tclk180_fifo_11_wr_en_delay1 ;

--              tclk180_fifo_11_wr_en_delay3     <= tclk180_fifo_11_wr_en_delay2 ;

--              tclk180_fifo_11_wr_en_delay4     <= tclk180_fifo_11_wr_en_delay3 ;

--              tclk180_fifo_11_wr_en_delay5     <= tclk180_fifo_11_wr_en_delay4 ;

--              tclk180_fifo_11_wr_en_delay6     <= tclk180_fifo_11_wr_en_delay5 ;

--              tclk180_fifo_11_wr_en_delay7     <= tclk180_fifo_11_wr_en_delay6 ;

--              tclk180_fifo_11_wr_en_delay8     <= tclk180_fifo_11_wr_en_delay7 ;

--              tclk180_fifo_11_wr_en_delay9     <= tclk180_fifo_11_wr_en_delay8 ;

--              tclk180_fifo_11_wr_en_end_pulse  <= tclk180_fifo_11_wr_en_delay9 and not tclk180_fifo_11_wr_en_delay8;

--      end if;

--PL: om een warning te lozen

--      if rising_edge (clk180) then 

--              tclk180_fifo_11_10_neq_flag      <=  tclk180_fifo_11_wr_en_end_pulse and to_std_logic( fifo_11_wr_addr /= fifo_10_wr_addr)  ; 

--      end if;

        if rising_edge (clk180) then

                test_fifo_wr_addr(15 downto 12)   <=  fifo_11_wr_addr(3 downto 0)   ;

                test_fifo_wr_addr(11 downto 8)    <=  fifo_10_wr_addr(3 downto 0)   ;

                test_fifo_wr_addr(7 downto 4)     <=  fifo_01_wr_addr(3 downto 0)   ;

                test_fifo_wr_addr(3 downto 0)     <=  fifo_00_wr_addr(3 downto 0)   ;

        end if;

end process;

reset90_r_val   <= reset90_r;

data_read0 : data_read

port map (

         clk90               =>    clk90,

         reset90_r           =>    reset90_r1,

         ddr_dq_in_rising    =>    dq_in_rising,

         ddr_dq_in_falling   =>    dq_in_falling,

         read_valid_data_1   =>    read_valid_data_1,

            fifo_00_wr_en                    => fifo_00_wr_en,

            fifo_10_wr_en                    => fifo_10_wr_en,

            fifo_01_wr_en                    => fifo_01_wr_en,

            fifo_11_wr_en                    => fifo_11_wr_en,

         fifo_00_wr_addr     =>    fifo_00_wr_addr,

         fifo_01_wr_addr     =>    fifo_01_wr_addr,

         fifo_10_wr_addr     =>    fifo_10_wr_addr,

         fifo_11_wr_addr     =>    fifo_11_wr_addr,

         dqs0_delayed_col0   =>    dqs0_delayed_col0,

         dqs1_delayed_col0   =>    dqs1_delayed_col0,

         user_output_data    =>    user_output_data,

         fifo0_rd_addr_val   =>    fifo0_rd_addr,

         fifo1_rd_addr_val   =>    fifo1_rd_addr

         );

data_read_controller0 : data_read_controller

port map (

            clk90              =>   clk90,

            clk180             =>   clk180,

            reset_r            =>   reset_r,

            reset90_r          =>   reset90_r1,

            rst_dqs_div_in     =>   rst_dqs_div_in,

            delay_sel          =>   delay_sel,

            dqs_int_delay_in0  =>   dqs_int_delay_in0,

            dqs_int_delay_in1  =>   dqs_int_delay_in1,

            fifo0_rd_addr    =>   fifo0_rd_addr,

            fifo1_rd_addr    =>   fifo1_rd_addr,

            u_data_val                                                      => u_data_val,

            read_valid_data_1_val  =>   read_valid_data_1,

            fifo_00_wr_en_val                               => fifo_00_wr_en,

            fifo_10_wr_en_val                               => fifo_10_wr_en,

            fifo_01_wr_en_val                               => fifo_01_wr_en,

            fifo_11_wr_en_val                               => fifo_11_wr_en,

            fifo_00_wr_addr_val     =>    fifo_00_wr_addr,

            fifo_01_wr_addr_val     =>    fifo_01_wr_addr,

            fifo_10_wr_addr_val     =>    fifo_10_wr_addr,

            fifo_11_wr_addr_val     =>    fifo_11_wr_addr,

                dqs0_delayed_col0_val     => dqs0_delayed_col0,

                dqs1_delayed_col0_val     => dqs1_delayed_col0

         );

data_write0 : data_write

port map (

          user_input_data    =>   user_input_data,

          clk90              =>   clk90,

          reset90_r          =>   reset90_r1,

          reset270_r         =>   reset270_r,

          write_enable       =>   write_enable,

          write_en_val       =>   write_en_val,

          write_en_val1      =>   write_en_val1,

          write_data_falling =>   write_data_falling,

          write_data_rising  =>   write_data_rising,

          data_mask_f        =>   data_mask_f,

          data_mask_r        =>   data_mask_r

         );

data_path_rst0 : data_path_rst

port map (

          clk                =>   clk,

          clk180             =>   clk180,

          clk90              =>   clk90,

          reset              =>   reset,

          reset90            =>   reset90,

          reset180           =>   reset180,

          reset270           =>   reset270,

          reset_r            =>   reset_r,

          reset90_r          =>   reset90_r,

          reset90_r1         =>   reset90_r1,

          reset180_r         =>   reset180_r,

          reset270_r         =>   reset270_r

         );

end arc_ddr2_data_path;