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--******************************************************************************

--

--  Xilinx, Inc. 2002                 www.xilinx.com

--

--

--*******************************************************************************

--

--  File name :       ddr2_dm.vhd

--

--  Description :     This module instantiates DDR IOB output flip-flops, and an 

--                    output buffer for the data mask bits.   

--                   

--  Date - revision : 07/31/2003

--

--

-- 

--*****************************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

-- pragma translate_off

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

-- pragma translate_on

--

entity ddr2_dm is

port (

      ddr_dm       : out std_logic_vector(1 downto 0);   --Data mask output

      mask_falling : in std_logic_vector(1 downto 0);    --Mask output on falling edge

      mask_rising  : in std_logic_vector(1 downto 0);    --Mask output on rising edge

      clk90        : in std_logic;    --Clock 90

      clk270       : in std_logic

      );

end ddr2_dm;

architecture arc_ddr2_dm of ddr2_dm is

component FDDRRSE

port( Q  : out std_logic;

      C0 : in std_logic;

      C1 : in std_logic;

      CE : in std_logic;

      D0 : in std_logic;

      D1 : in std_logic;

      R  : in std_logic;

      S  : in std_logic);

end component;

component OBUF

port (

       I : in std_logic;

       O : out std_logic);

end component;

--***********************************************************************\

--     Internal signal declaration

--***********************************************************************/

signal mask_o    : std_logic_vector(1 downto 0);  -- Mask output intermediate signal

signal gnd       : std_logic;

signal vcc       : std_logic;

begin

gnd      <= '0';

vcc      <= '1';

-- Data Mask Output during a write command

DDR_DM0_OUT : FDDRRSE port map (

                               Q  => mask_o(0),

                               C0 => clk270,

                               C1 => clk90,

                               CE => vcc,

                               D0 => mask_rising(0),

                               D1 => mask_falling(0),

                               R  => gnd,

                               S  => gnd

                              );

DDR_DM1_OUT : FDDRRSE port map (

                               Q  => mask_o(1),

                               C0 => clk270,

                               C1 => clk90,

                               CE => vcc,

                               D0 => mask_rising(1),

                               D1 => mask_falling(1),

                               R  => gnd,

                               S  => gnd

                              );

DM0_OBUF : OBUF port map (

                         I => mask_o(0),

                         O => ddr_dm(0)

                        );

DM1_OBUF : OBUF port map (

                         I => mask_o(1),

                         O => ddr_dm(1)

                        );

end arc_ddr2_dm;