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[/] [pulse_processing_algorithm/] [ddr2_iobs.vhd] - Blame information for rev 2

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--******************************************************************************
--
--  Xilinx, Inc. 2002                 www.xilinx.com
--
--  XAPP 253 - Synthesizable DDR SDRAM Controller
--
--*******************************************************************************
--
--  File name :       controller.vhd
--
-- 
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity ddr2_iobs is
port(
     clk0              : in std_logic;
     clk180            : in std_logic;
     clk90             : in std_logic;
     ddr_rasb_cntrl    : in std_logic;
     ddr_ODT_cntrl     : in std_logic;
     ddr_casb_cntrl    : in std_logic;
     ddr_web_cntrl     : in std_logic;
     ddr_cke_cntrl     : in std_logic;
     ddr_csb_cntrl     : in std_logic;
     ddr_address_cntrl : in std_logic_vector(12 downto 0);
     ddr_ba_cntrl      : in std_logic_vector(1 downto 0);
     rst_dqs_div_int   : in std_logic;
     dqs_reset         : in std_logic;
     dqs_enable        : in std_logic;
     ddr_dqs           : inout std_logic_vector(1 downto 0);
     ddr_dq            : inout std_logic_vector(15 downto 0);
     write_data_falling: in std_logic_vector(15 downto 0);
     write_data_rising : in std_logic_vector(15 downto 0);
     write_en_val      : in std_logic;
     write_en_val1      : in std_logic;
     reset90_r        : in std_logic;
     data_mask_f       : in std_logic_vector(1 downto 0);
     data_mask_r       : in std_logic_vector(1 downto 0);
     ddr_ODT0          : out std_logic;
     ddr_rasb          : out std_logic;
     ddr_casb          : out std_logic;
     ddr_web           : out std_logic;
     ddr_ba            : out std_logic_vector(1 downto 0);
     ddr_address       : out std_logic_vector(15 downto 0);
     ddr_cke           : out std_logic;
     ddr_csb           : out std_logic;
     rst_dqs_div       : out std_logic;
     rst_dqs_div_iob   : inout std_logic;
 --    rst_dqs_div_in    : in std_logic;--changed by shyam on 13 march
 --    rst_dqs_div_out   : out std_logic;--changed by shyam on 13 march
     dqs_int_delay_in0 : out std_logic;
     dqs_int_delay_in1 : out std_logic;
     dq_in_rising             : out std_logic_vector(15 downto 0);
     dq_in_falling             : out std_logic_vector(15 downto 0);
--old     dq_in             : out std_logic_vector(15 downto 0);
     ddr_dm            : out std_logic_vector(1 downto 0)
);
end ddr2_iobs;
 
 
architecture arc_ddr2_iobs of ddr2_iobs is
 
 
 
component controller_ddr2_iobs
port(
     clk0             : in std_logic;
     clk180           : in std_logic;
     ddr_rasb_cntrl   : in std_logic;
     ddr_casb_cntrl   : in std_logic;
     ddr_web_cntrl    : in std_logic;
     ddr_cke_cntrl    : in std_logic;
     ddr_ODT_cntrl    : in std_logic;
     ddr_csb_cntrl    : in std_logic;
     ddr_address_cntrl: in std_logic_vector(12 downto 0);
     ddr_ba_cntrl     : in std_logic_vector(1 downto 0);
     rst_dqs_div_int  : in std_logic;
     ddr_ODT0         : out std_logic;
     ddr_rasb         : out std_logic;
     ddr_casb         : out std_logic;
     ddr_web          : out std_logic;
     ddr_ba           : out std_logic_vector(1 downto 0);
     ddr_address      : out std_logic_vector(15 downto 0);
     ddr_cke          : out std_logic;
     ddr_csb          : out std_logic;
     rst_dqs_div      : out std_logic;
--     rst_dqs_div_in   : in std_logic;
--     rst_dqs_div_out  : out std_logic
     rst_dqs_div_iob  : inout std_logic
    );
end component;
 
        COMPONENT datapath_ddr2_iobs
        PORT(
                clk : IN std_logic;
                clk90 : IN std_logic;
                reset90_r : IN std_logic;
                dqs_reset : IN std_logic;
                dqs_enable : IN std_logic;
                write_data_falling : IN std_logic_vector(15 downto 0);
                write_data_rising : IN std_logic_vector(15 downto 0);
                write_en_val : IN std_logic;
                write_en_val1 : IN std_logic;
                data_mask_f : IN std_logic_vector(1 downto 0);
                data_mask_r : IN std_logic_vector(1 downto 0);
                ddr_dqs : INOUT std_logic_vector(1 downto 0);
                ddr_dq : INOUT std_logic_vector(15 downto 0);
                dqs_int_delay_in0 : OUT std_logic;
                dqs_int_delay_in1 : OUT std_logic;
                ddr_dq_in_rising : OUT std_logic_vector(15 downto 0);
                ddr_dq_in_falling : OUT std_logic_vector(15 downto 0);
                ddr_dm : OUT std_logic_vector(1 downto 0)
                );
        END COMPONENT;
 
 
 
 
 
 
 
 
 
begin
 
 
 
 
controller_ddr2_iobs0 : controller_ddr2_iobs port map (
                                             clk0              =>  clk0,
                                             clk180            =>  clk180,
                                             ddr_rasb_cntrl    =>  ddr_rasb_cntrl,
                                             ddr_casb_cntrl    =>  ddr_casb_cntrl,
                                             ddr_web_cntrl     =>  ddr_web_cntrl,
                                             ddr_cke_cntrl     =>  ddr_cke_cntrl,
                                             ddr_csb_cntrl     =>  ddr_csb_cntrl,
                                             ddr_ODT_cntrl     =>  ddr_ODT_cntrl,
                                             ddr_address_cntrl =>  ddr_address_cntrl(12 downto 0),
                                             ddr_ba_cntrl      =>  ddr_ba_cntrl(1 downto 0),
                                             rst_dqs_div_int   =>  rst_dqs_div_int,
--PL: Hela hola... poortje vergeten !!! 
                                                                                                                        ddr_ODT0                                =>      ddr_ODT0,       -- DIT ZAT ER DUS NIET IN, WAS DEFAULT '0'
                                             ddr_rasb          =>  ddr_rasb,
                                             ddr_casb          =>  ddr_casb,
                                             ddr_web           =>  ddr_web,
                                             ddr_ba            =>  ddr_ba(1 downto 0),
                                             ddr_address       =>  ddr_address(15 downto 0),
                                             ddr_cke           =>  ddr_cke,
                                             ddr_csb           =>  ddr_csb,
                                             rst_dqs_div       =>  rst_dqs_div,
--                                             rst_dqs_div_in    =>  rst_dqs_div_in,
--                                             rst_dqs_div_out   =>  rst_dqs_div_out                                                );
                                             rst_dqs_div_iob   =>  rst_dqs_div_iob                                                  );
 
datapath_ddr2_iobs0 : datapath_ddr2_iobs port map (
                                         clk                =>   clk0,
                                         clk90              =>   clk90,
                                         reset90_r          =>   reset90_r,
                                         dqs_reset          =>   dqs_reset,
                                         dqs_enable         =>   dqs_enable,
                                         ddr_dqs            =>   ddr_dqs(1 downto 0),
                                         ddr_dq             =>   ddr_dq(15 downto 0),
                                         write_data_falling =>   write_data_falling(15 downto 0),
                                         write_data_rising  =>   write_data_rising(15 downto 0),
                                         write_en_val       =>   write_en_val,
                                         write_en_val1      =>   write_en_val1,
                                         data_mask_f        =>   data_mask_f(1 downto 0),
                                         data_mask_r        =>   data_mask_r(1 downto 0),
                                         dqs_int_delay_in0  =>   dqs_int_delay_in0,
                                         dqs_int_delay_in1  =>   dqs_int_delay_in1,
                                         ddr_dq_in_rising   =>   dq_in_rising(15 downto 0),
                                         ddr_dq_in_falling  =>   dq_in_falling(15 downto 0),
--old                                         ddr_dq_val         =>   dq_in(15 downto 0),
                                         ddr_dm             =>   ddr_dm(1 downto 0)
                                        );
 
 
 
 
end arc_ddr2_iobs;
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	2	panda_emc	`--******************************************************************************`
2			`--`
3			`-- Xilinx, Inc. 2002 www.xilinx.com`
4			`--`
5			`-- XAPP 253 - Synthesizable DDR SDRAM Controller`
6			`--`
7			`--*******************************************************************************`
8			`--`
9			`-- File name : controller.vhd`
10			`--`
11			`--`
12			`--*****************************************************************************`
13			`library ieee;`
14			`use ieee.std_logic_1164.all;`
15			`use ieee.std_logic_unsigned.all;`
16			`--`
17			`-- pragma translate_off`
18			`library UNISIM;`
19			`use UNISIM.VCOMPONENTS.ALL;`
20			`-- pragma translate_on`
21			`--`
22			`entity ddr2_iobs is`
23			`port(`
24			`clk0 : in std_logic;`
25			`clk180 : in std_logic;`
26			`clk90 : in std_logic;`
27			`ddr_rasb_cntrl : in std_logic;`
28			`ddr_ODT_cntrl : in std_logic;`
29			`ddr_casb_cntrl : in std_logic;`
30			`ddr_web_cntrl : in std_logic;`
31			`ddr_cke_cntrl : in std_logic;`
32			`ddr_csb_cntrl : in std_logic;`
33			`ddr_address_cntrl : in std_logic_vector(12 downto 0);`
34			`ddr_ba_cntrl : in std_logic_vector(1 downto 0);`
35			`rst_dqs_div_int : in std_logic;`
36			`dqs_reset : in std_logic;`
37			`dqs_enable : in std_logic;`
38			`ddr_dqs : inout std_logic_vector(1 downto 0);`
39			`ddr_dq : inout std_logic_vector(15 downto 0);`
40			`write_data_falling: in std_logic_vector(15 downto 0);`
41			`write_data_rising : in std_logic_vector(15 downto 0);`
42			`write_en_val : in std_logic;`
43			`write_en_val1 : in std_logic;`
44			`reset90_r : in std_logic;`
45			`data_mask_f : in std_logic_vector(1 downto 0);`
46			`data_mask_r : in std_logic_vector(1 downto 0);`
47			`ddr_ODT0 : out std_logic;`
48			`ddr_rasb : out std_logic;`
49			`ddr_casb : out std_logic;`
50			`ddr_web : out std_logic;`
51			`ddr_ba : out std_logic_vector(1 downto 0);`
52			`ddr_address : out std_logic_vector(15 downto 0);`
53			`ddr_cke : out std_logic;`
54			`ddr_csb : out std_logic;`
55			`rst_dqs_div : out std_logic;`
56			`rst_dqs_div_iob : inout std_logic;`
57			`-- rst_dqs_div_in : in std_logic;--changed by shyam on 13 march`
58			`-- rst_dqs_div_out : out std_logic;--changed by shyam on 13 march`
59			`dqs_int_delay_in0 : out std_logic;`
60			`dqs_int_delay_in1 : out std_logic;`
61			`dq_in_rising : out std_logic_vector(15 downto 0);`
62			`dq_in_falling : out std_logic_vector(15 downto 0);`
63			`--old dq_in : out std_logic_vector(15 downto 0);`
64			`ddr_dm : out std_logic_vector(1 downto 0)`
65			`);`
66			`end ddr2_iobs;`
67
68
69			`architecture arc_ddr2_iobs of ddr2_iobs is`
70
71
72
73			`component controller_ddr2_iobs`
74			`port(`
75			`clk0 : in std_logic;`
76			`clk180 : in std_logic;`
77			`ddr_rasb_cntrl : in std_logic;`
78			`ddr_casb_cntrl : in std_logic;`
79			`ddr_web_cntrl : in std_logic;`
80			`ddr_cke_cntrl : in std_logic;`
81			`ddr_ODT_cntrl : in std_logic;`
82			`ddr_csb_cntrl : in std_logic;`
83			`ddr_address_cntrl: in std_logic_vector(12 downto 0);`
84			`ddr_ba_cntrl : in std_logic_vector(1 downto 0);`
85			`rst_dqs_div_int : in std_logic;`
86			`ddr_ODT0 : out std_logic;`
87			`ddr_rasb : out std_logic;`
88			`ddr_casb : out std_logic;`
89			`ddr_web : out std_logic;`
90			`ddr_ba : out std_logic_vector(1 downto 0);`
91			`ddr_address : out std_logic_vector(15 downto 0);`
92			`ddr_cke : out std_logic;`
93			`ddr_csb : out std_logic;`
94			`rst_dqs_div : out std_logic;`
95			`-- rst_dqs_div_in : in std_logic;`
96			`-- rst_dqs_div_out : out std_logic`
97			`rst_dqs_div_iob : inout std_logic`
98			`);`
99			`end component;`
100
101			`COMPONENT datapath_ddr2_iobs`
102			`PORT(`
103			`clk : IN std_logic;`
104			`clk90 : IN std_logic;`
105			`reset90_r : IN std_logic;`
106			`dqs_reset : IN std_logic;`
107			`dqs_enable : IN std_logic;`
108			`write_data_falling : IN std_logic_vector(15 downto 0);`
109			`write_data_rising : IN std_logic_vector(15 downto 0);`
110			`write_en_val : IN std_logic;`
111			`write_en_val1 : IN std_logic;`
112			`data_mask_f : IN std_logic_vector(1 downto 0);`
113			`data_mask_r : IN std_logic_vector(1 downto 0);`
114			`ddr_dqs : INOUT std_logic_vector(1 downto 0);`
115			`ddr_dq : INOUT std_logic_vector(15 downto 0);`
116			`dqs_int_delay_in0 : OUT std_logic;`
117			`dqs_int_delay_in1 : OUT std_logic;`
118			`ddr_dq_in_rising : OUT std_logic_vector(15 downto 0);`
119			`ddr_dq_in_falling : OUT std_logic_vector(15 downto 0);`
120			`ddr_dm : OUT std_logic_vector(1 downto 0)`
121			`);`
122			`END COMPONENT;`
123
124
125
126
127
128
129
130
131
132			`begin`
133
134
135
136
137			`controller_ddr2_iobs0 : controller_ddr2_iobs port map (`
138			`clk0 => clk0,`
139			`clk180 => clk180,`
140			`ddr_rasb_cntrl => ddr_rasb_cntrl,`
141			`ddr_casb_cntrl => ddr_casb_cntrl,`
142			`ddr_web_cntrl => ddr_web_cntrl,`
143			`ddr_cke_cntrl => ddr_cke_cntrl,`
144			`ddr_csb_cntrl => ddr_csb_cntrl,`
145			`ddr_ODT_cntrl => ddr_ODT_cntrl,`
146			`ddr_address_cntrl => ddr_address_cntrl(12 downto 0),`
147			`ddr_ba_cntrl => ddr_ba_cntrl(1 downto 0),`
148			`rst_dqs_div_int => rst_dqs_div_int,`
149			`--PL: Hela hola... poortje vergeten !!!`
150			`ddr_ODT0 => ddr_ODT0, -- DIT ZAT ER DUS NIET IN, WAS DEFAULT '0'`
151			`ddr_rasb => ddr_rasb,`
152			`ddr_casb => ddr_casb,`
153			`ddr_web => ddr_web,`
154			`ddr_ba => ddr_ba(1 downto 0),`
155			`ddr_address => ddr_address(15 downto 0),`
156			`ddr_cke => ddr_cke,`
157			`ddr_csb => ddr_csb,`
158			`rst_dqs_div => rst_dqs_div,`
159			`-- rst_dqs_div_in => rst_dqs_div_in,`
160			`-- rst_dqs_div_out => rst_dqs_div_out );`
161			`rst_dqs_div_iob => rst_dqs_div_iob );`
162
163			`datapath_ddr2_iobs0 : datapath_ddr2_iobs port map (`
164			`clk => clk0,`
165			`clk90 => clk90,`
166			`reset90_r => reset90_r,`
167			`dqs_reset => dqs_reset,`
168			`dqs_enable => dqs_enable,`
169			`ddr_dqs => ddr_dqs(1 downto 0),`
170			`ddr_dq => ddr_dq(15 downto 0),`
171			`write_data_falling => write_data_falling(15 downto 0),`
172			`write_data_rising => write_data_rising(15 downto 0),`
173			`write_en_val => write_en_val,`
174			`write_en_val1 => write_en_val1,`
175			`data_mask_f => data_mask_f(1 downto 0),`
176			`data_mask_r => data_mask_r(1 downto 0),`
177			`dqs_int_delay_in0 => dqs_int_delay_in0,`
178			`dqs_int_delay_in1 => dqs_int_delay_in1,`
179			`ddr_dq_in_rising => dq_in_rising(15 downto 0),`
180			`ddr_dq_in_falling => dq_in_falling(15 downto 0),`
181			`--old ddr_dq_val => dq_in(15 downto 0),`
182			`ddr_dm => ddr_dm(1 downto 0)`
183			`);`
184
185
186
187
188			`end arc_ddr2_iobs;`
189
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Subversion Repositories pulse_processing_algorithm

[/] [pulse_processing_algorithm/] [ddr2_iobs.vhd] - Blame information for rev 2