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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : dff_re.vhd
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-- Description : D-FlipFlop with Reset & Enable; variable width
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity dff_re is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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data_valid : out STD_LOGIC;
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d : in STD_LOGIC_VECTOR;
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q : out STD_LOGIC_VECTOR
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);
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end dff_re;
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architecture Behavioral of dff_re is
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constant WIDTH : natural := d'length;
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic;
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signal enable_S : std_logic;
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signal data_valid_S : std_logic := '0';
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signal d_S : STD_LOGIC_VECTOR(d'high downto 0);
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signal q_S : STD_LOGIC_VECTOR(q'high downto 0) := (others => '0');
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begin
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rst_S <= rst;
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clk_S <= clk;
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enable_S <= enable;
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data_valid <= data_valid_S;
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d_S <= d;
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q <= q_S;
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process(clk_S, rst_S, enable_S)
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begin
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if rising_edge(clk_S) then
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if rst_S='1' then
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q_S(WIDTH - 1 downto 0) <= (others => '0');
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data_valid_S <= '0';
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elsif (enable_S = '1') then
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q_S <= d_S;
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data_valid_S <= '1';
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else
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data_valid_S <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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