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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : gate_generator.vhd
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-- Description : Generate 2 independent gating signals upon event-detection
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-- bl-gate == '1' enables collection of baseline data/samples
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-- ed-gate == '1' enables event detection
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-- Both are disabled at an event and remain inactive for seperate counts
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.numeric_std.ALL;
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entity gate_generator is
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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program : in STD_LOGIC;
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baseline_enable : in STD_LOGIC;
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event_in : in STD_LOGIC;
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baseline_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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event_inhibit_cnt_in : in STD_LOGIC_VECTOR;
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bl_gate_out : out STD_LOGIC; -- baseline gate-signal
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ed_gate_out : out STD_LOGIC -- baseline gating inhibited because of event
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);
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end gate_generator;
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architecture Behavioral of gate_generator is
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type Gate_state_type is (gate_idle, gate_inhibit, gate_enable);
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal program_S : std_logic := '0';
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signal baseline_enable_S : std_logic := '0';
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signal event_in_S : std_logic := '0';
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-- signal baseline_inhibit_set_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value
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-- signal event_inhibit_set_S : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(20, 8); -- original default value
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signal bl_gate_S : std_logic := '0';
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signal ed_gate_S : std_logic := '0';
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-- baseline_inhibit_counter; inhibits baseline sampling at reset or event
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-- signal bl_inhibit_cnt_S : std_logic_vector(M4_PWR+ 1 downto 0) := conv_std_logic_vector(BL_GATE_COUNT,M4_PWR + 2);
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signal bl_inhibit_cnt_S : std_logic_vector(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value;
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signal bl_inhibit_val_S : std_logic_vector(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value;
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-- signal bl_gate_cnt_S : std_logic_vector(M4_PWR+ 1 downto 0) := (others => '0'); --conv_std_logic_vector(BL_GATE_COUNT,M4_PWR + 2);
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-- event_detect_inhibit_counter; inhibits baseline sampling during event
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-- signal ed_inhib_cnt_S : std_logic_vector(BASE_WINDOW_PWR+ 1 downto 0) := (others => '0'); -- conv_std_logic_vector(ED_INHIBIT_COUNT,BASE_WINDOW_PWR + 2);
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signal ed_inhibit_cnt_S : std_logic_vector(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value;
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signal ed_inhibit_val_S : std_logic_vector(7 downto 0) := conv_std_logic_vector(32, 8); -- original default value;
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begin
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rst_S <= rst;
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clk_S <= clk;
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enable_S <= enable;
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program_S <= program;
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baseline_enable_S <= baseline_enable; -- allready clocked in Feature_extraction.vhd
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event_in_S <= event_in;
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bl_gate_out <= bl_gate_S;
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ed_gate_out <= ed_gate_S;
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gate_count : process(clk_S, enable_S, event_in_S, baseline_enable_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') or (program_S = '1') then
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bl_inhibit_val_S <= baseline_inhibit_cnt_in;
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ed_inhibit_val_S <= event_inhibit_cnt_in;
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elsif enable_S = '1' then
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if (baseline_enable_S = '1') then
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-- on eventdetect, initialize event_inhibition for a fixed period
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if (event_in_S = '1') then
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ed_inhibit_cnt_S <= ed_inhibit_val_S;
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-- event_inhibition for a fixed period
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elsif (ed_inhibit_cnt_S > 0) then
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ed_inhibit_cnt_S <= ed_inhibit_cnt_S - 1;
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end if;
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-- on eventdetect, initialize baseline_inhibition for a fixed period
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if (event_in_S = '1') then
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bl_inhibit_cnt_S <= bl_inhibit_val_S;
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-- event_inhibition for a fixed period
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elsif (bl_inhibit_cnt_S > 0) then
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bl_inhibit_cnt_S <= bl_inhibit_cnt_S - 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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gate : process(clk_S, enable_S, event_in_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (enable_S = '1') and (bl_inhibit_cnt_S = 0) and (event_in_S = '0') and (baseline_enable_S = '1') then
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bl_gate_S <= '1';
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else
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bl_gate_S <= '0';
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end if;
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if (enable_S = '1') and (ed_inhibit_cnt_S = 0) and (event_in_S = '0') and (baseline_enable_S = '1') then
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ed_gate_S <= '1';
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else
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ed_gate_S <= '0';
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end if;
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end if;
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end process;
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end Behavioral;
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