Subversion Repositories pulse_processing_algorithm

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--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

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-- Company              :       KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author               :       P.J.J. Lemmens

-- Design Name  :       Feature Extraction

-- Module Name  :       peak_detect.vhd

-- Description  :       peak-detector keeps track of <DEPTH> samples. When a trigger occurs

--                                              the max value of these samples is determined and sent to max_out

--                                              accompanied by a max_valid signal. This process runs on the sample clock

--                                              and the <DEPTH> determines it's latency

--                                              

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

entity history_max is

        generic(        MEM_PWR                 :       natural :=      1;              -- memory size = 2^MEM_PWR

                                DEPTH                           :       natural := 1            --      implemented buffer depth; should be < 2^MEM_PWR

                                );

        Port (  rst                     : in  STD_LOGIC;

                                clk                     : in  STD_LOGIC;

                                enable          : in  STD_LOGIC := '1';

                                trigger         : in    STD_LOGIC;

                                data_in         : in  STD_LOGIC_VECTOR;

                                max_valid       : out   STD_LOGIC;

                                max_out         : out   STD_LOGIC_VECTOR

                        );

end history_max;

architecture Behavioral of history_max is

        constant        WIDTH                                           : natural := data_in'length;

        component pipeline

                generic(        RAM_SIZE_PWR    : natural;

                                        DELAY                           :       natural);

                port (  rst                             : IN STD_LOGIC ;

                                        clk                             : IN STD_LOGIC ;

                                        enable                  : IN  STD_LOGIC := '1';

                                        data_in                 : IN STD_LOGIC_VECTOR;

                                        data_valid              : out   std_logic;

                                        data_out                        : OUT STD_LOGIC_VECTOR

                                );

        end component;

        signal rst_S                            : std_logic := '1';

        signal clk_S                            : std_logic;

        signal enable_S                 : std_logic := '1';

        signal trigger_S                        : std_logic := '1';

        signal data_in_S                        : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal del_data_S                       : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal max_valid_S              : std_logic := '0';

        signal max_out_S                        : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal pipecount_S              : std_logic_vector(MEM_PWR downto 0) := (others => '0');

begin

                history_pipe : pipeline

                        generic map(RAM_SIZE_PWR        =>      MEM_PWR,

                                                        DELAY                           => DEPTH - 1) -- hier doen want ik voeg in deze file ook nog een stap toe !!

                        PORT MAP (      rst             => rst_S,

                                                        clk             => clk_S,

                                                        enable  =>      enable_S,                       -- this pipe is allways running !!

                                                        data_in => data_in_S,

                                                        data_out => del_data_S

                                                );

                clk_S                   <= clk;                                                                                                 -- connect clk PORT to internal clk-signal

                rst_S                   <= rst;

                enable_S        <= enable;

                trigger_S       <= trigger;

                data_in_S       <= data_in;

                max_valid       <=      max_valid_S;

                max_out         <=      max_out_S;

                get_max : process (clk_S, rst_S, data_in_S, trigger_S)

                begin

                        if (clk_S'event and clk_S = '1') then

                                if (rst_S = '1') then

                                        max_valid_S     <= '0';

                                        pipecount_S <= (others => '0');

                                else

                                        if (enable_S = '1') then

                                                if (trigger_S = '1') then

                                                        pipecount_S     <= conv_std_logic_vector(DEPTH - 1, MEM_PWR + 1);

                                                        max_out_S       <= del_data_S;

                                                else

                                                        if (pipecount_S > 0) then

                                                                pipecount_S <= pipecount_S - 1;

                                                                if (del_data_S > max_out_S) then

                                                                        max_out_S       <= del_data_S;  -- this is one extra delay

                                                                end if;

                                                        end if;

                                                end if;

                                                if (pipecount_S = 1) then

                                                        max_valid_S     <= '1';

                                                else

                                                        max_valid_S     <= '0';

                                                end if;

                                        end if;

                                end if;

                        end if;

                end process;

end Behavioral;