1 |
2 |
panda_emc |
-----------------------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
|
4 |
|
|
-- p.j.j.lemmens@rug.nl
|
5 |
|
|
-- http://www-panda.gsi.de
|
6 |
|
|
--
|
7 |
|
|
-- As a reference, please use:
|
8 |
|
|
-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
|
9 |
|
|
-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
|
10 |
|
|
-- Nuclear Inst. and Methods in Physics Research, A ....
|
11 |
|
|
--
|
12 |
|
|
--
|
13 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
14 |
|
|
-- it under the terms of the GNU Lesser General Public License as published by
|
15 |
|
|
-- the Free Software Foundation; either version 3 of the License, or
|
16 |
|
|
-- (at your option) any later version.
|
17 |
|
|
--
|
18 |
|
|
-- This program is distributed in the hope that it will be useful,
|
19 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
20 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
21 |
|
|
-- GNU Lesser General Public License for more details.
|
22 |
|
|
--
|
23 |
|
|
-- You should have received a copy of the GNU General Public License
|
24 |
|
|
-- along with this program; if not, write to the Free Software
|
25 |
|
|
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
|
26 |
|
|
--
|
27 |
|
|
-----------------------------------------------------------------------------------------------
|
28 |
|
|
-----------------------------------------------------------------------------------------------
|
29 |
|
|
-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
|
30 |
|
|
-- Author : P.J.J. Lemmens
|
31 |
|
|
-- Design Name : Feature Extraction
|
32 |
|
|
-- Module Name : pipeline.vhd
|
33 |
|
|
-- Description : fixed-length delayline / datapipe with a (generic-fixed) maximum size
|
34 |
|
|
--
|
35 |
|
|
-----------------------------------------------------------------------------------------------
|
36 |
|
|
library IEEE;
|
37 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
38 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
39 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
40 |
|
|
|
41 |
|
|
entity pipeline is
|
42 |
|
|
generic (RAM_SIZE_PWR : natural := 1;
|
43 |
|
|
DELAY : natural := 1
|
44 |
|
|
);
|
45 |
|
|
Port (clk : in STD_LOGIC;
|
46 |
|
|
rst : in STD_LOGIC;
|
47 |
|
|
enable : in STD_LOGIC;
|
48 |
|
|
data_in : in STD_LOGIC_VECTOR;
|
49 |
|
|
data_valid : out std_logic;
|
50 |
|
|
data_out : out STD_LOGIC_VECTOR
|
51 |
|
|
);
|
52 |
|
|
end pipeline;
|
53 |
|
|
|
54 |
|
|
architecture Behavioral of pipeline is
|
55 |
|
|
|
56 |
|
|
constant WIDTH : natural := data_in'length;
|
57 |
|
|
constant MAX_RAM_ADDRESS : natural := 2**RAM_SIZE_PWR - 1;
|
58 |
|
|
constant RAM_DEPTH : natural := DELAY - 2;
|
59 |
|
|
-- constant ZERO : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
|
60 |
|
|
|
61 |
|
|
component block_ram
|
62 |
|
|
generic (RAM_SIZE_PWR : natural := 1);
|
63 |
|
|
Port (clk : in STD_LOGIC := '0';
|
64 |
|
|
enable : in STD_LOGIC := '0';
|
65 |
|
|
write_ptr : in STD_LOGIC_VECTOR;
|
66 |
|
|
read_ptr : in STD_LOGIC_VECTOR;
|
67 |
|
|
data_in : in STD_LOGIC_VECTOR;
|
68 |
|
|
data_out : out STD_LOGIC_VECTOR
|
69 |
|
|
);
|
70 |
|
|
end component;
|
71 |
|
|
|
72 |
|
|
|
73 |
|
|
signal clk_S : STD_LOGIC := '0';
|
74 |
|
|
signal rst_S : STD_LOGIC := '1';
|
75 |
|
|
signal enable_S : STD_LOGIC := '0';
|
76 |
|
|
signal data_valid_S : STD_LOGIC := '0';
|
77 |
|
|
signal data_in_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
|
78 |
|
|
signal del_data_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
|
79 |
|
|
signal data_out_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
|
80 |
|
|
|
81 |
|
|
signal write_ptr_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR);
|
82 |
|
|
signal read_ptr_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := (others => '0');
|
83 |
|
|
|
84 |
|
|
signal rst_count_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR downto 0) := conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR + 1);
|
85 |
|
|
|
86 |
|
|
begin
|
87 |
|
|
-- BLOCKRAM read/write gives DEPTH+1 delay !!!
|
88 |
|
|
-- DEPTH MUST be greater than 4 !!!
|
89 |
|
|
pipe_ram : block_ram
|
90 |
|
|
generic map(RAM_SIZE_PWR => RAM_SIZE_PWR)
|
91 |
|
|
Port map(clk => clk_S,
|
92 |
|
|
enable => enable_S,
|
93 |
|
|
write_ptr => write_ptr_S,
|
94 |
|
|
read_ptr => read_ptr_S,
|
95 |
|
|
data_in => data_in_S,
|
96 |
|
|
data_out => del_data_S
|
97 |
|
|
);
|
98 |
|
|
|
99 |
|
|
|
100 |
|
|
clk_S <= clk;
|
101 |
|
|
rst_S <= rst;
|
102 |
|
|
enable_S <= enable;
|
103 |
|
|
data_in_S <= data_in;
|
104 |
|
|
data_valid <= data_valid_S;
|
105 |
|
|
data_out <= data_out_S;
|
106 |
|
|
|
107 |
|
|
rst_fake : process (clk_S, rst_S)
|
108 |
|
|
begin
|
109 |
|
|
if (clk_S'event and clk_S = '1') then
|
110 |
|
|
if rst_S = '1' then
|
111 |
|
|
rst_count_S <= conv_std_logic_vector(RAM_DEPTH + 1, RAM_SIZE_PWR + 1);
|
112 |
|
|
else
|
113 |
|
|
if (enable_S = '1' and rst_count_S > 0) then
|
114 |
|
|
rst_count_S <= rst_count_S - 1;
|
115 |
|
|
end if;
|
116 |
|
|
end if;
|
117 |
|
|
end if;
|
118 |
|
|
end process;
|
119 |
|
|
|
120 |
|
|
ram_reg : process (clk_S, rst_S, rst_count_S, del_data_S)
|
121 |
|
|
begin
|
122 |
|
|
if (clk_S'event and clk_S = '1') then
|
123 |
|
|
if (rst_S = '1') then
|
124 |
|
|
data_out_S <= (others => '0');
|
125 |
|
|
data_valid_S <= '0';
|
126 |
|
|
else
|
127 |
|
|
if (enable_S = '1') then
|
128 |
|
|
if (rst_count_S > 0) then
|
129 |
|
|
data_out_S <= (others => '0');
|
130 |
|
|
data_valid_S <= '0';
|
131 |
|
|
else
|
132 |
|
|
data_out_S <= del_data_S;
|
133 |
|
|
data_valid_S <= '1';
|
134 |
|
|
end if;
|
135 |
|
|
end if;
|
136 |
|
|
end if;
|
137 |
|
|
end if;
|
138 |
|
|
end process;
|
139 |
|
|
|
140 |
|
|
|
141 |
|
|
write_ptr : process(clk_S, rst_S, enable_S)
|
142 |
|
|
begin
|
143 |
|
|
if (clk_S'event and clk_S = '1') then
|
144 |
|
|
if rst_S = '1' then
|
145 |
|
|
write_ptr_S <= conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR);
|
146 |
|
|
else
|
147 |
|
|
if (enable_S ='1') then
|
148 |
|
|
if (write_ptr_S < MAX_RAM_ADDRESS) then
|
149 |
|
|
write_ptr_S <= write_ptr_S + 1;
|
150 |
|
|
else
|
151 |
|
|
write_ptr_S <= (others => '0');
|
152 |
|
|
end if;
|
153 |
|
|
end if;
|
154 |
|
|
end if;
|
155 |
|
|
end if;
|
156 |
|
|
end process;
|
157 |
|
|
|
158 |
|
|
|
159 |
|
|
read_ptr : process(clk_S, rst_S, enable_S)
|
160 |
|
|
begin
|
161 |
|
|
if (clk_S'event and clk_S = '1') then
|
162 |
|
|
if rst_S='1' then
|
163 |
|
|
read_ptr_S <= (others => '0');
|
164 |
|
|
else
|
165 |
|
|
if (enable_S ='1') then
|
166 |
|
|
if (read_ptr_S < MAX_RAM_ADDRESS) then
|
167 |
|
|
read_ptr_S <= read_ptr_S + 1;
|
168 |
|
|
else
|
169 |
|
|
read_ptr_S <= (others => '0');
|
170 |
|
|
end if;
|
171 |
|
|
end if;
|
172 |
|
|
end if;
|
173 |
|
|
end if;
|
174 |
|
|
end process;
|
175 |
|
|
|
176 |
|
|
end Behavioral;
|