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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : pipeline.vhd
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-- Description : fixed-length delayline / datapipe with a (generic-fixed) maximum size
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--
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity pipeline is
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generic (RAM_SIZE_PWR : natural := 1;
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DELAY : natural := 1
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);
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Port (clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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enable : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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data_valid : out std_logic;
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data_out : out STD_LOGIC_VECTOR
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);
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end pipeline;
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architecture Behavioral of pipeline is
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constant WIDTH : natural := data_in'length;
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constant MAX_RAM_ADDRESS : natural := 2**RAM_SIZE_PWR - 1;
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constant RAM_DEPTH : natural := DELAY - 2;
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-- constant ZERO : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
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component block_ram
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generic (RAM_SIZE_PWR : natural := 1);
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Port (clk : in STD_LOGIC := '0';
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enable : in STD_LOGIC := '0';
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write_ptr : in STD_LOGIC_VECTOR;
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read_ptr : in STD_LOGIC_VECTOR;
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data_in : in STD_LOGIC_VECTOR;
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data_out : out STD_LOGIC_VECTOR
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);
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end component;
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signal clk_S : STD_LOGIC := '0';
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signal rst_S : STD_LOGIC := '1';
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signal enable_S : STD_LOGIC := '0';
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signal data_valid_S : STD_LOGIC := '0';
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signal data_in_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
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signal del_data_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
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signal data_out_S : STD_LOGIC_VECTOR(WIDTH - 1 downto 0) := (others => '0');
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signal write_ptr_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR);
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signal read_ptr_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR - 1 downto 0) := (others => '0');
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signal rst_count_S : STD_LOGIC_VECTOR(RAM_SIZE_PWR downto 0) := conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR + 1);
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begin
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-- BLOCKRAM read/write gives DEPTH+1 delay !!!
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-- DEPTH MUST be greater than 4 !!!
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pipe_ram : block_ram
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generic map(RAM_SIZE_PWR => RAM_SIZE_PWR)
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Port map(clk => clk_S,
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enable => enable_S,
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write_ptr => write_ptr_S,
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read_ptr => read_ptr_S,
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data_in => data_in_S,
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data_out => del_data_S
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);
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clk_S <= clk;
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rst_S <= rst;
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enable_S <= enable;
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data_in_S <= data_in;
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data_valid <= data_valid_S;
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data_out <= data_out_S;
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rst_fake : process (clk_S, rst_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if rst_S = '1' then
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rst_count_S <= conv_std_logic_vector(RAM_DEPTH + 1, RAM_SIZE_PWR + 1);
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else
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if (enable_S = '1' and rst_count_S > 0) then
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rst_count_S <= rst_count_S - 1;
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end if;
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end if;
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end if;
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end process;
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ram_reg : process (clk_S, rst_S, rst_count_S, del_data_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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data_out_S <= (others => '0');
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data_valid_S <= '0';
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else
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if (enable_S = '1') then
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if (rst_count_S > 0) then
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data_out_S <= (others => '0');
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data_valid_S <= '0';
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else
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data_out_S <= del_data_S;
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data_valid_S <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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write_ptr : process(clk_S, rst_S, enable_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if rst_S = '1' then
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write_ptr_S <= conv_std_logic_vector(RAM_DEPTH, RAM_SIZE_PWR);
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else
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if (enable_S ='1') then
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if (write_ptr_S < MAX_RAM_ADDRESS) then
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write_ptr_S <= write_ptr_S + 1;
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else
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write_ptr_S <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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read_ptr : process(clk_S, rst_S, enable_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if rst_S='1' then
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read_ptr_S <= (others => '0');
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else
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if (enable_S ='1') then
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if (read_ptr_S < MAX_RAM_ADDRESS) then
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read_ptr_S <= read_ptr_S + 1;
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else
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read_ptr_S <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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