Subversion Repositories pulse_processing_algorithm

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--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

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-- Company              :       KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author               :       P.J.J. Lemmens

-- Design Name  :       Feature Extraction

-- Module Name  :       adc_flow_control.vhd

-- Description  :       The SIS3301/2 shares memory between the ADCs and VME. On the adc side

--                                              each controlling fpga gets a base address and a chunk of memory to write into.

--                                              The memory is not directly written into but through a pair of FIFOs; one

--                                              for the data (32bit) and one for the address(32 bit) to which you want to

--                                              write. This module builds 32-bit words for the data fifo from 16-bit words

--                                              of data from the signal-processing. Each 2nd 32 bit data word is accompanied

--                                              by a 32-bit address. (also see the adc_flowcontrol describtion)

--                                              Data is writen twice, address only once.

--                                              

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ringbuffer_feed is

        port(   rst                             : in    std_logic;

                        clk                             : in    std_logic;

                        enable                  : in    std_logic;

                        data_in                 : in  STD_LOGIC_VECTOR(15 downto 0);

                        address_in              : in  STD_LOGIC_VECTOR(31 downto 0);

                        data_out_valid  : out   std_logic;

                        addr_out_valid  : out   std_logic;

                        data_out                        : out STD_LOGIC_VECTOR(31 downto 0);

                        address_out             : out STD_LOGIC_VECTOR(31 downto 0)

                );

        end ringbuffer_feed;

architecture Behavioral of ringbuffer_feed is

        type word_state_type is (word_a,word_b,word_c,word_d);

        signal word_state_S             : word_state_type := word_a;

   signal rst_S                         : std_logic := '1';

   signal clk_S                         : std_logic := '0';

   signal enable_S                      : std_logic := '0';

        signal data_in_S                        : std_logic_vector(15 downto 0) := (others => '0');

        signal address_in_S             : std_logic_vector(31 downto 0) := (others => '0');

   signal data_valid_S          : std_logic := '0';

   signal addr_valid_S          : std_logic := '0';

        signal data_out_S                       : std_logic_vector(31 downto 0) := (others => '0');

        signal address_out_S            : std_logic_vector(31 downto 0) := (others => '0');

        begin

        rst_S                           <= rst;

        clk_S                           <= clk;

        enable_S                        <= enable;

        data_out_valid  <= data_valid_S;

        addr_out_valid  <= addr_valid_S;

        data_out                        <= data_out_S;

        address_out             <= address_out_S;

        fsm_ringbuffer_feed : process(rst_S, clk_S, enable_S)

        begin

                if rising_edge(clk_S) then

                        data_in_S               <= data_in;

                        address_in_S    <= address_in;

                        if (rst_S = '1') then

                                word_state_S                                                    <= word_a;

                                data_valid_S                                                    <= '0';

                                addr_valid_S                                                    <= '0';

                                data_in_S                                                               <= (others => '0');

                                address_in_S                                                    <= (others => '0');

                                data_out_S                                                              <= (others => '0');

                                address_out_S                                                   <= (others => '0');

                        elsif (enable_S = '1') then

                                case word_state_S is

                                        when    word_a  =>

                                                word_state_S                                    <= word_b;

                                                data_out_S(15 downto 0)          <= data_in_S;

                                                data_valid_S                                    <= '0';

                                                addr_valid_S                                    <= '0';

                                        when    word_b  =>

                                                word_state_S                                    <= word_c;

                                                data_out_S(31 downto 16)        <= data_in_S;

                                                address_out_S                                   <= address_in_S(31 downto 2) & b"00";

                                                data_valid_S                                    <= '1';

                                                addr_valid_S                                    <= '0';

                                        when    word_c  =>

                                                word_state_S                                    <= word_d;

                                                data_out_S(15 downto 0)          <= data_in_S;

                                                data_valid_S                                    <= '0';

                                                addr_valid_S                                    <= '0';

                                        when    word_d  =>

                                                word_state_S                                    <= word_a;

                                                data_out_S(31 downto 16)        <= data_in_S;

                                                address_out_S                                   <= address_in_S(31 downto 2) & b"00";

                                                data_valid_S                                    <= '1';

                                                addr_valid_S                                    <= '1';

                                        when others =>

                                                word_state_S                                    <= word_a;

                                                data_valid_S                                    <= '0';

                                                addr_valid_S                                    <= '0';

                                end case;

                        else

                                data_valid_S                                    <= '0';

                                addr_valid_S                                    <= '0';

                        end if;

                end if;

        end process;

end Behavioral;