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panda_emc |
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--
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-- Copyright (C) 2011 Peter Lemmens, PANDA collaboration
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-- p.j.j.lemmens@rug.nl
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-- http://www-panda.gsi.de
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--
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-- As a reference, please use:
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-- E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,
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-- "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"
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-- Nuclear Inst. and Methods in Physics Research, A ....
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA
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--
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-----------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------------------
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-- Company : KVI (Kernfysisch Versneller Instituut -- Groningen, The Netherlands
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-- Author : P.J.J. Lemmens
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-- Design Name : Feature Extraction
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-- Module Name : timing_linear_interp
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-- Description : calculates a binary time-fraction through linear interpolation between
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-- two neighbouring samples; "INTERP_CYCLES" determines the number of bits
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-- bits are right-alligned with the msb on the left (as usual)
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-- msb=1/2, msb+1=1/4, msb+2=1/8 etc.
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-----------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity timing_linear_interp is
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generic( INTERP_CYCLES : natural := 1);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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trigger : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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samplenr_in : in STD_LOGIC_VECTOR;
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eventnr_out : out STD_LOGIC_VECTOR;
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fraction_out : out STD_LOGIC_VECTOR;
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eventdata_valid : out STD_LOGIC
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);
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end timing_linear_interp;
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architecture Behavioral of timing_linear_interp is
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constant WIDTH : natural := data_in'length;
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-- constant ZEROX_WINDOW : natural := 2**ZEROX_WINDOW_PWR;
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-- constant MAX_PIPE_IDX : natural := ZEROX_WINDOW - 1;
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constant FRACTION_SIZE : natural := INTERP_CYCLES; -- - ZEROX_WINDOW_PWR; --all interp bits are fraction now !! interp between 2 samples
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component window_diff
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-- generic( DEPTH_PWR : natural);
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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trigger : in STD_LOGIC;
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data_in : in STD_LOGIC_VECTOR;
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base_out : out STD_LOGIC_VECTOR;
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diff_out : out STD_LOGIC_VECTOR
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);
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end component;
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component successive_interp
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generic( ITERATIONS : natural := 1
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);
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Port (rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC := '1';
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trigger : in STD_LOGIC;
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samplenr_in : in STD_LOGIC_VECTOR;
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base_in : in STD_LOGIC_VECTOR;
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diff_in : in STD_LOGIC_VECTOR;
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output_valid : out STD_LOGIC;
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fraction_out : out STD_LOGIC_VECTOR;
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eventnr_out : out STD_LOGIC_VECTOR
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);
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end component;
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--------------------------------------------------------------------------------------------------
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signal rst_S : std_logic := '1';
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signal clk_S : std_logic := '0';
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signal enable_S : std_logic := '0';
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signal data_in_S : std_logic_vector (WIDTH - 1 downto 0) := (others => '0');
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signal trigger_S : std_logic := '0';
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signal base_val_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal window_diff_S : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
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signal samplenr_in_S : std_logic_vector(samplenr_in'high downto 0) := (others => '0');
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signal eventdata_valid_S : std_logic := '0';
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signal eventnr_out_S : std_logic_vector(samplenr_in'high downto 0) := (others => '0');
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signal fraction_out_S : std_logic_vector(FRACTION_SIZE - 1 downto 0) := (others => '0');
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--------------------------------------------------------------------------------------------------
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begin
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window_slope : window_diff
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port map ( rst => rst_S,
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clk => clk_S,
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enable => enable_S, -- this pipe is allways running !!
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trigger => trigger_S,
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data_in => data_in_S,
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base_out => base_val_S,
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diff_out => window_diff_S
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);
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interp : successive_interp
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generic map ( ITERATIONS => INTERP_CYCLES)
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port map ( rst => rst_S,
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clk => clk_S,
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enable => enable_S, -- this pipe is allways running !!
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trigger => trigger_S,
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samplenr_in => samplenr_in_S,
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base_in => base_val_S,
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diff_in => window_diff_S,
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output_valid => eventdata_valid_S,
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fraction_out => fraction_out_S,
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eventnr_out => eventnr_out_S
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);
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rst_S <= rst;
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clk_S <= clk;
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enable_S <= enable;
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data_in_S <= data_in;
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samplenr_in_S <= samplenr_in;
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eventnr_out <= eventnr_out_S;
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fraction_out <= fraction_out_S;
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eventdata_valid <= eventdata_valid_S;
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sync_proc : process(rst_S, clk_S, enable_S, trigger, eventnr_out_S)
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begin
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if (clk_S'event and clk_S = '1') then
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if (rst_S = '1') then
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trigger_S <= '0';
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else
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if (enable_S = '1') then
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trigger_S <= trigger;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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