Subversion Repositories pulse_processing_algorithm

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--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

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-- Company              :       KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author               :       P.J.J. Lemmens

-- Design Name  :       Feature Extraction

-- Module Name  :       timing_linear_interp

-- Description  :       calculates a binary time-fraction through linear interpolation between

--                                              two neighbouring samples; "INTERP_CYCLES" determines the number of bits

--                                              bits are right-alligned with the msb on the left (as usual)

--                                              msb=1/2, msb+1=1/4, msb+2=1/8 etc.

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity timing_linear_interp is

        generic(        INTERP_CYCLES                   :       natural :=      1);

        Port (  rst                                     :       in              STD_LOGIC;

                                clk                                     :       in              STD_LOGIC;

                                enable                          :       in              STD_LOGIC := '1';

                                trigger                         :       in              STD_LOGIC;

                                data_in                         :       in              STD_LOGIC_VECTOR;

                                samplenr_in                     :       in              STD_LOGIC_VECTOR;

                                eventnr_out                     :       out     STD_LOGIC_VECTOR;

                                fraction_out            :       out     STD_LOGIC_VECTOR;

                                eventdata_valid :       out     STD_LOGIC

                        );

end timing_linear_interp;

architecture Behavioral of timing_linear_interp is

        constant        WIDTH                           :       natural := data_in'length;

--      constant        ZEROX_WINDOW    :       natural := 2**ZEROX_WINDOW_PWR;

--      constant        MAX_PIPE_IDX    :       natural :=      ZEROX_WINDOW - 1;

        constant FRACTION_SIZE  :       natural := INTERP_CYCLES; --    - ZEROX_WINDOW_PWR; --all  interp bits are fraction now !! interp between 2 samples

        component window_diff

--              generic(        DEPTH_PWR       :       natural);

                Port (  rst                     : in    STD_LOGIC;

                                        clk                     : in    STD_LOGIC;

                                        enable          : in  STD_LOGIC := '1';

                                        trigger         : in    STD_LOGIC;

                                        data_in         : in    STD_LOGIC_VECTOR;

                                        base_out                : out   STD_LOGIC_VECTOR;

                                        diff_out                : out   STD_LOGIC_VECTOR

                                );

        end component;

        component successive_interp

                generic(        ITERATIONS                      :       natural :=      1

                                );

                Port (rst                               : in    STD_LOGIC;

                                clk                             : in    STD_LOGIC;

                                enable                  : in  STD_LOGIC := '1';

                                trigger                 : in    STD_LOGIC;

                                samplenr_in             : in    STD_LOGIC_VECTOR;

                                base_in                 : in    STD_LOGIC_VECTOR;

                                diff_in                 : in    STD_LOGIC_VECTOR;

                                output_valid    : out   STD_LOGIC;

                                fraction_out    : out   STD_LOGIC_VECTOR;

                                eventnr_out             : out   STD_LOGIC_VECTOR

                                );

        end component;

--------------------------------------------------------------------------------------------------

        signal rst_S                                    : std_logic := '1';

        signal clk_S                                    : std_logic := '0';

        signal enable_S                         : std_logic := '0';

        signal data_in_S                                : std_logic_vector (WIDTH - 1 downto 0) := (others => '0');

        signal trigger_S                                : std_logic := '0';

        signal base_val_S                               : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal window_diff_S                    : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal samplenr_in_S                    : std_logic_vector(samplenr_in'high downto 0) := (others => '0');

        signal eventdata_valid_S        : std_logic := '0';

        signal eventnr_out_S                    : std_logic_vector(samplenr_in'high downto 0) := (others => '0');

        signal fraction_out_S           : std_logic_vector(FRACTION_SIZE - 1 downto 0) := (others => '0');

--------------------------------------------------------------------------------------------------

        begin

                window_slope : window_diff

                        port map        (       rst                     => rst_S,

                                                        clk                     => clk_S,

                                                        enable          =>      enable_S,                       -- this pipe is allways running !!

                                                        trigger         =>      trigger_S,

                                                        data_in         =>      data_in_S,

                                                        base_out                =>      base_val_S,

                                                        diff_out                =>      window_diff_S

                                                );

                interp : successive_interp

                        generic map     (       ITERATIONS                      =>      INTERP_CYCLES)

                        port map        (       rst                             => rst_S,

                                                        clk                             => clk_S,

                                                        enable                  =>      enable_S,                       -- this pipe is allways running !!

                                                        trigger                 =>      trigger_S,

                                                        samplenr_in             => samplenr_in_S,

                                                        base_in                 =>      base_val_S,

                                                        diff_in                 =>      window_diff_S,

                                                        output_valid    => eventdata_valid_S,

                                                        fraction_out    =>      fraction_out_S,

                                                        eventnr_out             => eventnr_out_S

                                                );

                rst_S                                   <=      rst;

                clk_S                                   <=      clk;

                enable_S                                <=      enable;

                data_in_S                       <=      data_in;

                samplenr_in_S           <= samplenr_in;

                eventnr_out                     <= eventnr_out_S;

                fraction_out            <=      fraction_out_S;

                eventdata_valid <= eventdata_valid_S;

        sync_proc : process(rst_S, clk_S, enable_S, trigger, eventnr_out_S)

                begin

                        if (clk_S'event and clk_S = '1') then

                                if (rst_S = '1') then

                                        trigger_S               <=      '0';

                                else

                                        if  (enable_S = '1') then

                                                trigger_S               <=      trigger;

                                        end if;

                                end if;

                        end if;

        end process;

end Behavioral;