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[/] [pulse_processing_algorithm/] [top.vhd] - Blame information for rev 2

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1 2 panda_emc 
-- *****************************************************************************************
2 
-- *                    top.vhd                                                                        *
3 
-- *                    SIS3302 ADC FPGA                                                               *
4 
-- *****************************************************************************************
5 
-- * date:                 02.05.2005                                                                                                    *
6 
-- *****************************************************************************************
7 
-- *                                                                                                                                                         *
8 
-- * Version 33021405 PSA                                                                                                                        *
9 
-- * last modification: 02.09.2009                                                                              *
10 
-- * ADC FPGA: -                                                                                                                             *
11 
-- *           -                                                                                                     *
12 
-- *                                                                                                                                                         *
13 
-- *****************************************************************************************
14 
library IEEE;
15 
use IEEE.STD_LOGIC_1164.ALL;
16 
use IEEE.STD_LOGIC_ARITH.ALL;
17 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
18 
 
19 
library UNISIM;
20 
use UNISIM.VComponents.all;
21 
 
22 
entity top is
23 
port(
24 
    system_clk_p                                : in std_logic := '0';
25 
    system_clk_n                                : in std_logic := '0';
26 
 
27 
    system_adc_clk_p                    : in std_logic := '0';
28 
    system_adc_clk_n                    : in std_logic := '0';
29 
 
30 
    adc1_clk_out_p                      : OUT std_logic := '0';
31 
    adc1_clk_out_n                      : OUT std_logic := '0';
32 
 
33 
    adc2_clk_out_p                      : OUT std_logic := '0';
34 
    adc2_clk_out_n                      : OUT std_logic := '0';
35 
 
36 
 
37 
    adc1_dco_p                                  : in std_logic := '0';
38 
    adc1_dco_n                                  : in std_logic := '0';
39 
    adc1_din_p                                  : in std_logic_vector(15 downto 0);
40 
    adc1_din_n                                  : in std_logic_vector(15 downto 0);
41 
 
42 
    adc2_dco_p                                  : in std_logic := '0';
43 
    adc2_dco_n                                  : in std_logic := '0';
44 
    adc2_din_p                                  : in std_logic_vector(15 downto 0);
45 
    adc2_din_n                                  : in std_logic_vector(15 downto 0);
46 
 
47 
 
48 
-- VME-ADC FPGA Interface
49 
 
50 
                i_fpga_reset_l : in std_logic ; -- -- FPGA_PROT_0 ; für clock und ddr logic
51 
                i_fpga_key_reset_l : in std_logic ; -- FPGA_PROT_9
52 
                i_fpga_sel_l : in std_logic ;
53 
                i_fpga_write_l : in std_logic ;
54 
                i_fpga_block_l : in std_logic ;
55 
                i_fpga_ds_l : in std_logic ;
56 
                wst_out_l_oreg  : OUT std_logic := '0';
57 
                io_fpga_ad: inout std_logic_VECTOR(31 downto 0);
58 
 
59 
                FPGA_ADC_B1_SAMPLE_ENABLED_L: in STD_LOGIC  ;   -- FPGA_PROT_5 = start_buffer(0)
60 
                FPGA_ADC_B2_SAMPLE_ENABLED_L: in STD_LOGIC  ;   -- FPGA_PROT_6 = start_buffer(1)
61 
                FPGA_ADC_SAMPLE_START_L: in STD_LOGIC  ;        -- FPGA_PROT_7 = externaltrigger = trigger_pulse
62 
 
63 
                FPGA_ADC_SAMPLE_STOP_L: in STD_LOGIC  ; -- FPGA_PROT_8 = ext_lemo_in3_ifd_l
64 
                FPGA_ADC_PROT13_L: in STD_LOGIC  ;      -- FPGA_prot13 = ext_lemo_in2_ifd_l
65 
                FPGA_ADC_PROT14_L: in STD_LOGIC  ;      -- FPGA_prot14 = ext_lemo_in1_ifd_l
66 
 
67 
                FPGA_LEMO_USER_IN_L: in STD_LOGIC  ;    -- FPGA_PROT_10 = stop_events
68 
 
69 
      FPGA_ADC_TIMESTAMP_CLR_L:in STD_LOGIC  ;  -- FPGA_PROT_11
70 
      FPGA_ADC_SAMPLE_LOGIC_RESET_L: in STD_LOGIC  ;    -- FPGA_PROT_12
71 
      FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L: out STD_LOGIC  ; -- FPGA_PROT_15
72 
 
73 
                FPGA_ADC1_TRIGGER_L: out STD_LOGIC  ; -- FPGA1_SEL1
74 
                FPGA_ADC2_TRIGGER_L: out STD_LOGIC  ; -- FPGA1_SEL2
75 
 
76 
                FPGA_ADC12_BUSY_L: out STD_LOGIC  ; -- FPGA1_SEL3
77 
                FPGA_ADC12_EVENT_END_L: out STD_LOGIC  ; -- FPGA1_SEL4
78 
 
79 
 
80 
                CON_WITH_ADC12_OUT1_L: out std_logic := '0'; -- not used
81 
                CON_WITH_ADC12_IN1_L: in  std_logic := '0'; -- enable_externaltrigger signal cascade from neighbour
82 
                CON_WITH_ADC12_OUT2_L: out std_logic := '0'; -- not used
83 
                CON_WITH_ADC12_IN2_L: in  std_logic := '0'; -- alleventsdone signal cascade from neighbour
84 
 
85 
                CON_WITH_ADC78_IN1_L: in std_logic := '0'; -- not used
86 
                CON_WITH_ADC78_OUT1_L: out  std_logic := '0'; -- enable_externaltrigger signal cascade to neighbour
87 
                CON_WITH_ADC78_IN2_L: in std_logic := '0'; -- not used
88 
                CON_WITH_ADC78_OUT2_L: out  std_logic := '0'; -- alleventsdone signal cascade to neighbour
89 
 
90 
 
91 
 
92 
                ddr1_clk             : out std_logic ;
93 
                ddr1_clkb            : out std_logic := '0';
94 
 
95 
                ddr1_dqs_reserve : OUT std_logic_vector(1 downto 0);
96 
                ddr1_ba2_reserve : OUT std_logic := '0';
97 
 
98 
 
99 
        ddr1_rst_dqs_div_iob : INOUT std_logic  ;
100 
 
101 
                ddr1_dqs : INOUT std_logic_vector(1 downto 0):= (others => 'Z');
102 
                ddr1_dq  : INOUT std_logic_vector(15 downto 0):= (others => 'Z');
103 
                ddr1_dm : OUT std_logic_vector(1 downto 0);
104 
 
105 
                ddr1_ba : OUT std_logic_vector(1 downto 0);
106 
                ddr1_address : OUT std_logic_vector(15 downto 0);
107 
                ddr1_rasb : OUT std_logic := '0';
108 
                ddr1_casb : OUT std_logic := '0';
109 
                ddr1_web : OUT std_logic := '0';
110 
                ddr1_cke : OUT std_logic := '0';
111 
                ddr1_csb : OUT std_logic ;
112 
                ddr1_ODT0 : OUT std_logic ;
113 
 
114 
                ddr2_clk             : out std_logic ;
115 
                ddr2_clkb            : out std_logic ;
116 
 
117 
                ddr2_dqs_reserve : OUT std_logic_vector(1 downto 0);
118 
                ddr2_ba2_reserve : OUT std_logic := '0';
119 
 
120 
 
121 
                ddr2_dqs : INOUT std_logic_vector(1 downto 0):= (others => 'Z');
122 
                ddr2_dq  : INOUT std_logic_vector(15 downto 0):= (others => 'Z');
123 
                ddr2_dm : OUT std_logic_vector(1 downto 0);
124 
 
125 
                ddr2_ba : OUT std_logic_vector(1 downto 0);
126 
                ddr2_address : OUT std_logic_vector(15 downto 0);
127 
                ddr2_rasb : OUT std_logic := '0';
128 
                ddr2_casb : OUT std_logic := '0';
129 
                ddr2_web : OUT std_logic := '0';
130 
                ddr2_cke : OUT std_logic := '0';
131 
                ddr2_csb : OUT std_logic := '0';
132 
                ddr2_ODT0 : OUT std_logic := '0';
133 
 
134 
        ddr2_rst_dqs_div_iob : INOUT std_logic := '0';
135 
 
136 
                FPGA_ID_D0 : IN std_logic := '0';
137 
                FPGA_ID_D1 : IN std_logic
138 
 
139 
                );
140 
end top;
141 
 
142 
 
143 
 
144 
architecture Behavioral of top is
145 
 
146 
   Function to_std_logic(X: in Boolean) return Std_Logic is
147 
   variable ret : std_logic := '0';
148 
   begin
149 
   if x then ret := '1';  else ret := '0'; end if;
150 
   return ret;
151 
   end to_std_logic;
152 
 
153 
signal i_system_clk                                                                     : std_logic := '0';
154 
signal system_clk_ibufg                                                         : std_logic := '0';
155 
 
156 
signal sys_clk_100                                                                      : std_logic     := '0';
157 
 
158 
signal clk_int                                                                                  : std_logic := '0';
159 
signal clk180_int                                                                               : std_logic := '0';
160 
signal clk90_int                                                                                : std_logic := '0';
161 
signal clk270_int                                                                               : std_logic := '0';
162 
signal clk_int_dcm_lock                                                         : std_logic := '0';
163 
--signal sys_clk_div2                                                                   : std_logic := '0'; --peter
164 
 
165 
signal ddr2_clk_system_reset                                            : std_logic := '0';
166 
signal ddr2_clk_system_reset_cnt                                        : std_logic_VECTOR(5 downto 0);
167 
 
168 
signal i_system_adc_clk                                                         : std_logic := '0';
169 
signal system_adc_clk                                                           : std_logic := '0';
170 
 
171 
signal fpga_sel_ireg                                                                    : std_logic := '0';
172 
signal fpga_ds_ireg                                                                     : std_logic := '0';
173 
signal fpga_write_ireg                                                          : std_logic := '0';
174 
signal fpga_block_ireg                                                          : std_logic := '0';
175 
signal fpga_reset_ibuf                                                          : std_logic := '0';
176 
signal fpga_key_reset_ibuf                                                      : std_logic := '0';
177 
signal fpga_key_reset_delay1                                            : std_logic := '0';
178 
signal fpga_key_reset_delay2                                            : std_logic := '0';
179 
signal fpga_key_reset_degliched                                 : std_logic := '0';
180 
 
181 
signal vme_out_ad_en                                                                    : std_logic := '0';
182 
signal vme_ad_oreg                                                                      : std_logic_VECTOR (31 downto 0);
183 
signal vme_ad_ireg                                                                      : std_logic_VECTOR (31 downto 0);
184 
signal wst_out_en                                                                               : std_logic := '0';
185 
signal vme_out_wst                                                                      : std_logic := '0';
186 
 
187 
signal adc1_dco_clk                                                                     : std_logic := '0';
188 
signal adc1_clk_l                                                                               : std_logic := '0';
189 
signal adc1_clk                                                                         : std_logic := '0';
190 
 
191 
signal adc1_buf_din                                                                     : std_logic_vector(15 downto 0);
192 
signal adc1_din                                                                         : std_logic_vector(15 downto 0);
193 
 
194 
signal adc1_ram_fifo_data_wr_data                               : std_logic_VECTOR(31 downto 0);
195 
signal adc1_ram_fifo_data_wr_ce                                 : std_logic := '0';
196 
signal adc1_ram_fifo_addr_wr_ce                                 : std_logic := '0';
197 
signal adc1_ram_fifo_addr_wr_addr                               : std_logic_VECTOR(31 downto 0);
198 
signal adc1_last_buffer_adc_ram_fifo_wr_addr    : std_logic_VECTOR(31 downto 0);
199 
 
200 
signal adc2_dco_clk                                                                     : std_logic := '0';
201 
signal adc2_clk_l                                                                               : std_logic := '0';
202 
signal adc2_clk                                                                         : std_logic := '0';
203 
 
204 
signal adc2_buf_din                                                                     : std_logic_vector(15 downto 0);
205 
signal adc2_din                                                                                 : std_logic_vector(15 downto 0);
206 
 
207 
signal adc2_ram_fifo_data_wr_data                               : std_logic_VECTOR(31 downto 0);
208 
signal adc2_ram_fifo_data_wr_ce                                 : std_logic := '0';
209 
signal adc2_ram_fifo_addr_wr_ce                                 : std_logic := '0';
210 
signal adc2_ram_fifo_addr_wr_addr                               : std_logic_VECTOR(31 downto 0);
211 
signal adc2_last_buffer_adc_ram_fifo_wr_addr    : std_logic_VECTOR(31 downto 0);
212 
 
213 
signal vme_0x20_reg_S                                                           : std_logic_vector(31 downto 0);
214 
 
215 
signal vme_b1_addr_ld                                                           : std_logic := '0';
216 
signal vme_b2_addr_ld                                                           : std_logic := '0';
217 
 
218 
signal rst                                                                                              : std_logic := '1';
219 
 
220 
 
221 
signal ram1_vme_wr_addr_fifo_q                                  : std_logic_VECTOR(31 downto 0);
222 
signal ram1_fifo_pipe_wr_count                                  : std_logic_VECTOR(8 downto 0);
223 
 
224 
signal ram1_vme_wr_addr_fifo_pipe_rd_en         : std_logic := '0';
225 
signal ram1_vme_wr_addr_fifo_pipe_valid         : std_logic := '0';
226 
 
227 
signal ram1_wr_bank_row_last_addr_flag                  : std_logic := '0';
228 
signal ram1_wr_bank_row_addr_conflict_flag      : std_logic := '0';
229 
signal ram1_wr_addr_fifo_pipe_burst_valid               : std_logic := '0';
230 
 
231 
signal ram1_vme_wr_fifo_rd_en                                           : std_logic := '0';
232 
 
233 
signal ram1_vme_rd_addr_fifo_d                                  : std_logic_VECTOR(31 downto 0);
234 
signal ram1_vme_rd_addr_fifo_q                                  : std_logic_VECTOR(31 downto 0);
235 
 
236 
signal ram1_vme_rd_addr_wr_fifo_pipe_empty      : std_logic := '0'; -- new 14.08.2009
237 
 
238 
signal ram1_vme_rd_addr_fifo_pipe_wr_count      : std_logic_VECTOR(8 downto 0);
239 
signal ram1_vme_rd_data_fifo_pipe_rd_count      : std_logic_VECTOR(8 downto 0);
240 
 
241 
 
242 
signal ram1_vme_rd_data_fifo_aint                               : std_logic := '0';
243 
signal ram1_vme_rd_addr_fifo_clr                                        : std_logic := '0';
244 
signal ram1_vme_rd_addr_fifo_wr_en                              : std_logic := '0';
245 
signal ram1_read_vme_address_fifo_pipe_asynch_reset: std_logic := '0';
246 
 
247 
 
248 
signal ram1_vme_rd_addr_fifo_pipe_rd_en         : std_logic := '0';
249 
 
250 
signal ram1_vme_rd_bank_row_last_addr_flag      : std_logic := '0';
251 
signal ram1_vme_rd_bank_row_addr_conflict_flag: std_logic := '0';
252 
signal ram1_vme_rd_addr_fifo_pipe_burst_valid: std_logic := '0';
253 
 
254 
signal ram1_vme_rd_addr_fifo_pipe_valid: std_logic := '0';
255 
signal ram1_rd_addr_mux_en: std_logic := '0';
256 
 
257 
signal ram1_vme_rd_fifo_rd_en: std_logic := '0';
258 
 
259 
signal ram1_rd_data_fifo_empty: std_logic := '0';
260 
signal ram1_rd_data_fifo_q: std_logic_VECTOR(31 downto 0);
261 
 
262 
 
263 
signal ram1_ddr2_user_output_data: std_logic_VECTOR(31 downto 0);
264 
signal ram1_ddr2_user_data_val: std_logic := '0';
265 
signal ram1_ddr2_user_input_data: std_logic_VECTOR(31 downto 0);
266 
 
267 
signal ram1_ddr2_command_register: std_logic_VECTOR(3 downto 0);         -- input
268 
signal ram1_ddr2_controller_address: std_logic_VECTOR(24 downto 0);              -- input
269 
 
270 
signal ram1_ddr2_burst_done: std_logic := '0';                            -- input
271 
signal ram1_ddr2_cmd_ack: std_logic := '0';                               -- output
272 
signal ram1_ddr2_autorefresh_done: std_logic := '0';                              -- output
273 
signal ram1_ddr2_init_done: std_logic := '0';                             -- output
274 
 
275 
signal ram1_ddr2_rst_calib1: std_logic := '0';
276 
signal ram1_ddr2_delay_sel: std_logic_VECTOR(4 downto 0);
277 
 
278 
signal ram1_ddr2_rasb_cntrl: std_logic := '0';
279 
signal ram1_ddr2_casb_cntrl: std_logic := '0';
280 
signal ram1_ddr2_web_cntrl: std_logic := '0';
281 
signal ram1_ddr2_cke_cntrl: std_logic := '0';
282 
signal ram1_ddr2_csb_cntrl: std_logic := '0';
283 
signal ram1_ddr2_ODT_cntrl: std_logic := '0';
284 
 
285 
signal ram1_ddr2_ba_cntrl: std_logic_VECTOR(1 downto 0);
286 
signal ram1_ddr2_address_cntrl: std_logic_VECTOR(12 downto 0);
287 
 
288 
signal ram1_ddr2_dqs_reset: std_logic := '0';
289 
signal ram1_ddr2_dqs_enable: std_logic := '0';
290 
signal ram1_ddr2_write_enable: std_logic := '0';
291 
signal ram1_ddr2_rst_dqs_div_int: std_logic := '0';
292 
signal ram1_ddr2_rst_dqs_div: std_logic := '0';
293 
 
294 
signal ram1_ddr2_sys_rst: std_logic := '0';
295 
signal ram1_ddr2_sys_rst90: std_logic := '0';
296 
signal ram1_ddr2_sys_rst180: std_logic := '0';
297 
signal ram1_ddr2_sys_rst180_orig: std_logic := '0';
298 
signal ram1_ddr2_sys_rst270: std_logic := '0';
299 
 
300 
signal ram1_ddr2_dqs_int_delay_in0: std_logic := '0';
301 
signal ram1_ddr2_dqs_int_delay_in1: std_logic := '0';
302 
signal ram1_ddr2_data_mask_f: std_logic_VECTOR(1 downto 0);
303 
signal ram1_ddr2_data_mask_r: std_logic_VECTOR(1 downto 0);
304 
signal ram1_ddr2_write_data_falling: std_logic_VECTOR(15 downto 0);
305 
signal ram1_ddr2_write_data_rising: std_logic_VECTOR(15 downto 0);
306 
signal ram1_ddr2_dq_in_rising: std_logic_VECTOR(15 downto 0);
307 
signal ram1_ddr2_dq_in_falling: std_logic_VECTOR(15 downto 0);
308 
 
309 
signal ram1_ddr2_write_en_val: std_logic := '0';
310 
signal ram1_ddr2_write_en_val1: std_logic := '0';
311 
signal ram1_ddr2_reset90_r: std_logic := '0';
312 
 
313 
signal ram2_vme_wr_addr_fifo_q: std_logic_VECTOR(31 downto 0);
314 
signal ram2_fifo_pipe_wr_count: std_logic_VECTOR(8 downto 0);
315 
 
316 
signal ram2_vme_wr_addr_fifo_pipe_rd_en: std_logic := '0';
317 
signal ram2_vme_wr_addr_fifo_pipe_valid: std_logic := '0';
318 
 
319 
signal ram2_wr_bank_row_last_addr_flag: std_logic := '0';
320 
signal ram2_wr_bank_row_addr_conflict_flag: std_logic := '0';
321 
signal ram2_wr_addr_fifo_pipe_burst_valid: std_logic := '0';
322 
 
323 
signal ram2_vme_wr_fifo_rd_en: std_logic := '0';
324 
 
325 
signal ram2_vme_rd_addr_fifo_d: std_logic_VECTOR(31 downto 0);
326 
signal ram2_vme_rd_addr_fifo_q: std_logic_VECTOR(31 downto 0);
327 
 
328 
signal ram2_vme_rd_addr_wr_fifo_pipe_empty: std_logic := '0'; -- new 14.08.2009
329 
 
330 
signal ram2_vme_rd_addr_fifo_pipe_wr_count: std_logic_VECTOR(8 downto 0);
331 
signal ram2_vme_rd_data_fifo_pipe_rd_count: std_logic_VECTOR(8 downto 0);
332 
 
333 
signal ram2_vme_rd_data_fifo_aint: std_logic := '0';
334 
signal ram2_vme_rd_addr_fifo_clr: std_logic := '0';
335 
signal ram2_vme_rd_addr_fifo_wr_en: std_logic := '0';
336 
signal ram2_read_vme_address_fifo_pipe_asynch_reset: std_logic := '0';
337 
 
338 
 
339 
signal ram2_vme_rd_addr_fifo_pipe_rd_en: std_logic := '0';
340 
signal ram2_vme_rd_bank_row_last_addr_flag: std_logic := '0';
341 
signal ram2_vme_rd_bank_row_addr_conflict_flag: std_logic := '0';
342 
signal ram2_vme_rd_addr_fifo_pipe_burst_valid: std_logic := '0';
343 
 
344 
signal ram2_vme_rd_addr_fifo_pipe_valid: std_logic := '0';
345 
signal ram2_rd_addr_mux_en: std_logic := '0';
346 
 
347 
signal ram2_vme_rd_fifo_rd_en: std_logic := '0';
348 
 
349 
signal ram2_rd_data_fifo_empty: std_logic := '0';
350 
signal ram2_rd_data_fifo_q: std_logic_VECTOR(31 downto 0);
351 
 
352 
 
353 
signal ram2_ddr2_controller_address: std_logic_VECTOR(24 downto 0);              -- input
354 
signal ram2_ddr2_command_register: std_logic_VECTOR(3 downto 0);         -- input
355 
 
356 
signal ram2_ddr2_burst_done: std_logic := '0';                            -- input
357 
signal ram2_ddr2_cmd_ack: std_logic := '0';                               -- output
358 
signal ram2_ddr2_autorefresh_done: std_logic := '0';                              -- output
359 
signal ram2_ddr2_init_done: std_logic := '0';                             -- output
360 
 
361 
signal ram2_ddr2_user_input_data: std_logic_VECTOR(31 downto 0);
362 
signal ram2_ddr2_user_output_data: std_logic_VECTOR(31 downto 0);
363 
signal ram2_ddr2_user_data_val: std_logic := '0';
364 
 
365 
 
366 
signal ddr_config_register1: std_logic_VECTOR(14 downto 0);
367 
signal ddr_config_register2: std_logic_VECTOR(12 downto 0);
368 
signal ramx_ddr2_delay_sel: std_logic_VECTOR(4 downto 0);
369 
 
370 
 
371 
signal ram2_ddr2_sys_rst: std_logic := '0';
372 
signal ram2_ddr2_sys_rst90: std_logic := '0';
373 
signal ram2_ddr2_sys_rst180: std_logic := '0';
374 
signal ram2_ddr2_sys_rst180_orig: std_logic := '0';
375 
signal ram2_ddr2_sys_rst270: std_logic := '0';
376 
 
377 
signal ram2_ddr2_delay_sel: std_logic_VECTOR(4 downto 0);
378 
signal ram2_ddr2_rst_calib1: std_logic := '0';
379 
signal ram2_ddr2_rst_dqs_div: std_logic := '0';
380 
 
381 
signal ram2_ddr2_write_enable: std_logic := '0';
382 
signal ram2_ddr2_rst_dqs_div_int: std_logic := '0';
383 
signal ram2_ddr2_dqs_enable: std_logic := '0';
384 
 
385 
signal ram2_ddr2_write_en_val                                           : std_logic := '0';
386 
signal ram2_ddr2_write_en_val1                                  : std_logic := '0';
387 
signal ram2_ddr2_reset90_r                                                      : std_logic := '0';
388 
 
389 
signal ram2_ddr2_dqs_int_delay_in0                              : std_logic := '0';
390 
signal ram2_ddr2_dqs_int_delay_in1                              : std_logic := '0';
391 
signal ram2_ddr2_data_mask_f                                            : std_logic_VECTOR(1 downto 0);
392 
signal ram2_ddr2_data_mask_r                                            : std_logic_VECTOR(1 downto 0);
393 
signal ram2_ddr2_write_data_falling                             : std_logic_VECTOR(15 downto 0);
394 
signal ram2_ddr2_write_data_rising                              : std_logic_VECTOR(15 downto 0);
395 
signal ram2_ddr2_dq_in_rising                                           : std_logic_VECTOR(15 downto 0);
396 
signal ram2_ddr2_dq_in_falling                                  : std_logic_VECTOR(15 downto 0);
397 
 
398 
 
399 
signal ram2_ddr2_rasb_cntrl                                             : std_logic := '0';
400 
signal ram2_ddr2_casb_cntrl                                             : std_logic := '0';
401 
signal ram2_ddr2_web_cntrl                                                      : std_logic := '0';
402 
signal ram2_ddr2_cke_cntrl                                                      : std_logic := '0';
403 
signal ram2_ddr2_csb_cntrl                                                      : std_logic := '0';
404 
signal ram2_ddr2_ODT_cntrl                                                      : std_logic := '0';
405 
 
406 
signal ram2_ddr2_ba_cntrl                                                       : std_logic_VECTOR(1 downto 0);
407 
signal ram2_ddr2_address_cntrl                                  : std_logic_VECTOR(12 downto 0);
408 
 
409 
 
410 
signal ram2_ddr2_dqs_reset                                                      : std_logic := '0';
411 
 
412 
 
413 
signal ch1_vme_test_write_ram_addr_fifo_ce      : std_logic := '0';
414 
signal ch1_vme_test_write_ram_addr_fifo_din     : std_logic_VECTOR(31 downto 0);
415 
signal ch1_vme_test_write_ram_data_fifo_ce      : std_logic := '0';
416 
signal ch1_vme_test_write_ram_data_fifo_din     : std_logic_VECTOR(31 downto 0);
417 
 
418 
signal mux_adc1_ram_fifo_addr_wr_ce                             : std_logic := '0';
419 
signal mux_adc1_ram_fifo_addr_wr_addr                   : std_logic_VECTOR(31 downto 0);
420 
signal mux_adc1_ram_fifo_data_wr_ce                             : std_logic := '0';
421 
signal mux_adc1_ram_fifo_data_wr_data                   : std_logic_VECTOR(31 downto 0);
422 
 
423 
signal ch2_vme_test_write_ram_addr_fifo_ce      : std_logic := '0';
424 
signal ch2_vme_test_write_ram_addr_fifo_din     : std_logic_VECTOR(31 downto 0);
425 
signal ch2_vme_test_write_ram_data_fifo_ce      : std_logic := '0';
426 
signal ch2_vme_test_write_ram_data_fifo_din     : std_logic_VECTOR(31 downto 0);
427 
 
428 
signal mux_adc2_ram_fifo_addr_wr_ce                             : std_logic := '0';
429 
signal mux_adc2_ram_fifo_addr_wr_addr                   : std_logic_VECTOR(31 downto 0);
430 
signal mux_adc2_ram_fifo_data_wr_ce                             : std_logic := '0';
431 
signal mux_adc2_ram_fifo_data_wr_data                   : std_logic_VECTOR(31 downto 0);
432 
 
433 
 
434 
 
435 
signal vme_ram1_wr_cycle                                                        : std_logic := '0';
436 
signal vme_ram2_wr_cycle                                                        : std_logic := '0';
437 
signal vme_ram1_wr_cmd_pulse                                            : std_logic := '0';
438 
signal vme_ram2_wr_cmd_pulse                                            : std_logic := '0';
439 
 
440 
 
441 
signal vme_b1_rd                                                                                : std_logic := '0';
442 
signal vme_b2_rd                                                                                : std_logic := '0';
443 
 
444 
signal ramx_vme_bx_rd_cycle                                             : std_logic := '0';
445 
signal ramx_vme_bx_rd_request                                           : std_logic := '0';
446 
signal ramx_vme_bx_rd_dma                                                       : std_logic := '0';
447 
 
448 
 
449 
signal vme_event_config_reg_S                                           : std_logic_VECTOR(31 downto 0)  := (others => '0');
450 
signal vme_0x04_reg_S                                                           : std_logic_VECTOR(23 downto 2) := (others => '0');
451 
 
452 
signal vme_0x30_reg_S                                                           : std_logic_VECTOR(31 downto 0)  := (others => '0');
453 
signal vme_0x34_reg_S                                                           : std_logic_VECTOR(26 downto 0)  := (others => '0');
454 
signal vme_0x38_reg_S                                                           : std_logic_VECTOR(31 downto 0)  := (others => '0');
455 
signal vme_0x3C_reg_S                                                           : std_logic_VECTOR(26 downto 0)  := (others => '0');
456 
 
457 
signal vme_adc1_ram_address_counter                             : std_logic_VECTOR(24 downto 0)  := (others => '0');
458 
signal vme_adc2_ram_address_counter                             : std_logic_VECTOR(24 downto 0)  := (others => '0');
459 
 
460 
 
461 
signal temp_24: std_logic_VECTOR(31 downto 0);
462 
signal temp_28: std_logic_VECTOR(31 downto 0);
463 
 
464 
signal ram1_ddr2_wr_data_wr_count: std_logic_VECTOR(9 downto 0);
465 
signal ram2_ddr2_wr_data_wr_count: std_logic_VECTOR(9 downto 0);
466 
 
467 
signal ram1_test_fifo_wr_addr: std_logic_VECTOR(15 downto 0);
468 
signal ram2_test_fifo_wr_addr: std_logic_VECTOR(15 downto 0);
469 
 
470 
signal ram1_ddr2_wr_data_rd_count: std_logic_VECTOR(9 downto 0);
471 
signal ram1_ddr2_wr_data_rd_empty: std_logic := '0';
472 
 
473 
signal adc1_clk_fpga_sel_ireg: std_logic := '0';
474 
signal adc2_clk_fpga_sel_ireg: std_logic := '0';
475 
 
476 
--signal adc1_sample_event_busy: std_logic := '0';
477 
--signal adc2_sample_event_busy: std_logic := '0';
478 
 
479 
signal adc12_event_logic_busy: std_logic := '0';
480 
 
481 
signal start_delay1     : std_logic := '0';
482 
signal start_delay2     : std_logic := '0';
483 
signal start_delay3     : std_logic := '0';
484 
signal start_delay4     : std_logic := '0';
485 
signal start_delay5     : std_logic := '0';
486 
signal start_delay6     : std_logic := '0';
487 
signal start_delay7     : std_logic := '0';
488 
signal start_delay8     : std_logic := '0';
489 
signal start_delay9     : std_logic := '0';
490 
signal start_delay10    : std_logic := '0';
491 
 
492 
signal fpga_reset_delay         : std_logic := '0';
493 
signal new_fpga_reset_ibuf      : std_logic := '0';
494 
 
495 
signal adc_sample_logic_reset_l                                 : std_logic := '0';
496 
signal adc_sample_logic_reset                                           : std_logic := '0';
497 
 
498 
 
499 
signal vme_0x08_reg_S                           : std_logic_vector(31 downto 0)  := (others => '0');
500 
signal vme_0x0C_reg_S                           : std_logic_vector(31 downto 0)  := (others => '0');
501 
signal vme_0x40_reg_S                           : std_logic_vector(31 downto 0)  := (others => '0');
502 
signal vme_0x44_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
503 
signal vme_0x48_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
504 
signal vme_0x4C_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
505 
signal vme_0x50_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
506 
signal vme_0x54_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
507 
signal vme_0x58_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
508 
signal vme_0x5C_reg_S                           : std_logic_vector(15 downto 0)  := (others => '0');
509 
signal vme_0x60_reg_S                           : std_logic_vector(31 downto 0)  := (others => '0');
510 
signal vme_0x64_reg_S                           : std_logic_vector(31 downto 0)  := (others => '0');
511 
signal vme_0x68_reg_S                           : std_logic_vector(7 downto 0)   := (others => '0');
512 
signal vme_0x80_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
513 
signal vme_0x84_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
514 
signal vme_0x88_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
515 
signal vme_0x8C_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
516 
 
517 
signal vme_0x90_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
518 
signal vme_0x94_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
519 
signal vme_0x98_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
520 
signal vme_0x9C_feedback_reg_S  : std_logic_vector(31 downto 0)  := (others => '0');
521 
 
522 
signal decay_correction_S                       : std_logic_vector(31 downto 0)  := (others      => '0');
523 
signal reshape_correction_S             : std_logic_vector(31 downto 0) := (others       => '0');
524 
signal buffer_size_S                                    : std_logic_vector(31 downto 0)  := (others => '0');
525 
signal int_signal_threshold_S           : STD_LOGIC_VECTOR(15 downto 0)  := conv_std_logic_vector(1024,16);              -- default value of 1024 decimal
526 
signal mwd_pwr_S                                                : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(5,     8);                                                     -- original default value
527 
signal cf_pwr_S                                         : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(4,     8);                                                     -- original default value = (mwd_power - 1)
528 
signal cf_integral_pwr_S                        : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(4,     8);                                                     -- original default value
529 
signal baseline_pwr_S                           : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(9,     10);                                                    -- original default value
530 
signal baseline_inhibit_cnt_S           : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(32,    8);                                                     -- original default value
531 
signal event_inhibit_cnt_S                      : STD_LOGIC_VECTOR(7 downto 0)   := conv_std_logic_vector(16,    8);                                                     -- original default value
532 
 
533 
signal FE1_running_S                                    : std_logic := '0';
534 
signal FE2_running_S                                    : std_logic := '0';
535 
signal FE1_enable_S                                     : std_logic := '0';
536 
signal FE2_enable_S                                     : std_logic := '0';
537 
signal cmd_invert_data_in_S             : std_logic := '0';
538 
 
539 
signal feedback_bus0_S                          : std_logic_vector(31 downto 0) := (others => '0');
540 
signal feedback_bus1_S                          : std_logic_vector(31 downto 0) := (others => '0');
541 
signal feedback_bus2_S                          : std_logic_vector(31 downto 0) := (others => '0');
542 
signal feedback_bus3_S                          : std_logic_vector(31 downto 0) := (others => '0');
543 
signal feedback_bus4_S                          : std_logic_vector(31 downto 0) := (others => '0');
544 
signal feedback_bus5_S                          : std_logic_vector(31 downto 0) := (others => '0');
545 
signal feedback_bus6_S                          : std_logic_vector(31 downto 0) := (others => '0');
546 
 
547 
 
548 
signal mca_ram1_rd_req                                                  : std_logic := '0';
549 
signal mca_ram1_rd_addr                                                 : std_logic_VECTOR(24 downto 0);
550 
signal mca_ram1_rd_gt                                                   : std_logic := '0';
551 
signal mca_ram1_rd_data_valid                                   : std_logic := '0';
552 
signal mca_ram1_rd_data_ld1                                     : std_logic := '0';
553 
signal mca_ram1_rd_data_ld2                                     : std_logic := '0';
554 
signal mca_ram1_rd_data_fifo_first_word : std_logic_VECTOR(31 downto 0);
555 
signal mca_ram1_rd_data_fifo_second_word        : std_logic_VECTOR(31 downto 0);
556 
 
557 
signal mca_ram2_rd_req                                                  : std_logic := '0';
558 
signal mca_ram2_rd_addr                                                 : std_logic_VECTOR(24 downto 0);
559 
signal mca_ram2_rd_gt                                                   : std_logic := '0';
560 
signal mca_ram2_rd_data_valid                                   : std_logic := '0';
561 
signal mca_ram2_rd_data_ld1                                     : std_logic := '0';
562 
signal mca_ram2_rd_data_ld2                                     : std_logic := '0';
563 
signal mca_ram2_rd_data_fifo_first_word : std_logic_VECTOR(31 downto 0);
564 
signal mca_ram2_rd_data_fifo_second_word        : std_logic_VECTOR(31 downto 0);
565 
 
566 
signal ram1_vme_rd_data_fifo_empty                      : std_logic := '0';
567 
signal ram2_vme_rd_data_fifo_empty                      : std_logic := '0';
568 
signal ram1_rd_fifo_rd_en                                               : std_logic := '0';
569 
signal ram2_rd_fifo_rd_en                                               : std_logic := '0';
570 
 
571 
signal adc1_ram_fifo_data_full                          : std_logic := '0';
572 
signal adc2_ram_fifo_data_full                          : std_logic := '0';
573 
 
574 
 component BUFG
575 
  port ( I : in std_logic := '0';
576 
         O : out std_logic);
577 
 end component;
578 
 
579 
 component IBUFG
580 
  port ( I : in std_logic := '0';
581 
         O : out std_logic);
582 
 end component;
583 
 
584 
 component IBUF
585 
  port ( I : in std_logic := '0';
586 
         O : out std_logic);
587 
 end component;
588 
 
589 
 
590 
        COMPONENT sys_clk_dcm
591 
                PORT(   sys_clk_in                              : IN std_logic := '0';
592 
                                rst                                             : IN std_logic := '0';
593 
                                sys_clk_out                             : OUT std_logic := '0';
594 
                                sys_clkfx_out                   : OUT std_logic := '0';
595 
                                dcm_sys_clock_locked    : OUT std_logic := '0';
596 
                                sys_clk_div2                    : out std_logic
597 
                        );
598 
        END COMPONENT;
599 
 
600 
 
601 
        COMPONENT ddr_clk_dcm
602 
                PORT(   sys_clk         : IN std_logic := '0';
603 
                                rst                     : IN std_logic := '0';
604 
                                clk_int         : OUT std_logic := '0';
605 
                                clk180_int      : OUT std_logic := '0';
606 
                                clk90_int       : OUT std_logic := '0';
607 
                                clk270_int      : OUT std_logic := '0';
608 
                                dcm_lock                : OUT std_logic := '0';
609 
                                ddr1_clk                : OUT std_logic := '0';
610 
                                ddr1_clkb       : OUT std_logic := '0';
611 
                                ddr2_clk                : OUT std_logic := '0';
612 
                                ddr2_clkb       : OUT std_logic
613 
                        );
614 
        END COMPONENT;
615 
 
616 
 
617 
  component IBUFDS is
618 
    port (
619 
        I : in STD_LOGIC;
620 
        IB : in STD_LOGIC;
621 
        O : out STD_LOGIC
622 
        );
623 
  end component;
624 
 
625 
  component IBUFGDS is
626 
    port(
627 
        I : in STD_LOGIC;
628 
        IB : in STD_LOGIC;
629 
        O : out STD_LOGIC
630 
        );
631 
  end component;
632 
 
633 
  component OBUFDS is
634 
    port (
635 
        I : in STD_LOGIC;
636 
        O : out STD_LOGIC;
637 
        OB : out STD_LOGIC
638 
        );
639 
  end component;
640 
 
641 
component OBUFT
642 
port(
643 
      I : in std_logic := '0';
644 
      T : in std_logic := '0';
645 
      O : out std_logic);
646 
end component;
647 
 
648 
COMPONENT FD
649 
        PORT(
650 
                C : IN std_logic := '0';
651 
                D : IN std_logic := '0';
652 
                Q : OUT std_logic
653 
                );
654 
END COMPONENT;
655 
 
656 
component OFD
657 
   port(
658 
      Q                              :  out   STD_LOGIC;
659 
      D                              :  in    STD_LOGIC;
660 
      C                              :  in    STD_LOGIC);
661 
end component ;
662 
 
663 
  component IFD is
664 
    port (
665 
        C : in STD_LOGIC;
666 
        D : in STD_LOGIC;
667 
        Q : out STD_LOGIC
668 
        );
669 
  end component;
670 
 
671 
 
672 
component Feature_Extraction
673 
        port(   uP_CLK                                                                  : in std_logic;
674 
                        Reset                                                                           : in std_logic;
675 
                        ADC_CLK                                                                 : in std_logic;
676 
                        ADCin                                                                           : in std_logic_vector(15 downto 0);
677 
                        invert_data_in                                                  : in std_logic;
678 
                        externaltrigger                                         : in std_logic;
679 
                        softwaretrigger                                         : in std_logic;
680 
 
681 
                        cmd_output_select                                               : in std_logic_vector(3 downto 0);
682 
                        cmd_start_adc                                                   : in std_logic;
683 
                        cmd_enableFE                                                    : in std_logic;
684 
                        cmd_baseline_enable                                     : in std_logic;
685 
                        cmd_double_CF                                                   : in std_logic;
686 
                        cmd_program_params                                      : in std_logic;
687 
                        cmd_bypass_mwd                                                  : in std_logic;
688 
                        cmd_bypass_reshape                                      : in std_logic;
689 
 
690 
                        decay_correction_in                                     : in STD_LOGIC_VECTOR(31 downto 0);
691 
                        reshape_correction_in                           : in STD_LOGIC_VECTOR(31 downto 0);
692 
                        buffer_size                                                             : in std_logic_vector(31 downto 0);  -- number of samples to read from buffer
693 
                        int_signal_threshold_in                         : in std_logic_vector(15 downto 0);  -- event-trigger threshold on the integrated input signal
694 
                        mwd_pwr_in                                                              : in std_logic_vector(7 downto 0);  -- power of 2 for mwd size
695 
                        cf_pwr_in                                                               : in std_logic_vector(7 downto 0);  -- power of 2 for cf delay
696 
                        cf_integral_pwr_in                                      : in std_logic_vector(7 downto 0);  -- power of 2 for cf-generation
697 
                        baseline_pwr_in                                         : in STD_LOGIC_VECTOR(7 downto 0);
698 
                        baseline_inhibit_cnt_in                         : in std_logic_vector(7 downto 0);  -- baseline data-collect inhibition after event
699 
                        event_inhibit_cnt_in                                    : in std_logic_vector(7 downto 0);  -- event detect inhibition after event
700 
 
701 
                        fb_flowctrl_running                                     : out std_logic := '0';
702 
                        fb_chain_enable                                         : out std_logic := '0';
703 
                        feedback_port0                                                  : out   std_logic_vector(31 downto 0);
704 
                        feedback_port1                                                  : out   std_logic_vector(31 downto 0);
705 
                        feedback_port2                                                  : out   std_logic_vector(15 downto 0);
706 
                        feedback_port3                                                  : out   std_logic_vector(31 downto 0);
707 
 
708 
                        adc_ram_fifo_data_wr_data                       : out std_logic_vector(31 downto 0);
709 
                        adc_ram_fifo_address                                    : out std_logic_vector(31 downto 0);
710 
                        adc_ram_fifo_data_wr_ce                         : out std_logic := '0';
711 
                        adc_ram_fifo_addr_wr_ce                         : out std_logic := '0';
712 
                        last_buffer_adc_ram_fifo_wr_addr        : out std_logic_vector(31 downto 0)
713 
                );
714 
end component;
715 
 
716 
 
717 
component blk_asy_fifo_1023x16
718 
    port(din: IN std_logic_VECTOR(15 downto 0);
719 
                        wr_en: IN std_logic := '0';
720 
                        wr_clk: IN std_logic := '0';
721 
                        rd_en: IN std_logic := '0';
722 
                        rd_clk: IN std_logic := '0';
723 
                        ainit: IN std_logic := '0';
724 
                        dout: OUT std_logic_VECTOR(15 downto 0);
725 
                        full: OUT std_logic := '0';
726 
                        empty: OUT std_logic := '0';
727 
                        wr_count: OUT std_logic_VECTOR(9 downto 0);
728 
                        rd_count: OUT std_logic_VECTOR(9 downto 0)
729 
                        );
730 
end component;
731 
 
732 
component blk_asy_fifo_511x32
733 
    port (
734 
    din: IN std_logic_VECTOR(31 downto 0);
735 
    wr_en: IN std_logic := '0';
736 
    wr_clk: IN std_logic := '0';
737 
    rd_en: IN std_logic := '0';
738 
    rd_clk: IN std_logic := '0';
739 
    ainit: IN std_logic := '0';
740 
    dout: OUT std_logic_VECTOR(31 downto 0);
741 
    full: OUT std_logic := '0';
742 
    empty: OUT std_logic := '0';
743 
    wr_count: OUT std_logic_VECTOR(8 downto 0);
744 
    rd_count: OUT std_logic_VECTOR(8 downto 0));
745 
end component;
746 
 
747 
COMPONENT ram_address_fifo_pipe
748 
        PORT(
749 
                clk_wr : IN std_logic := '0';
750 
                clk180 : IN std_logic := '0';
751 
                asynch_reset : IN std_logic := '0';
752 
                fifo_input_d : IN std_logic_vector(31 downto 0);
753 
                fifo_input_wr_en : IN std_logic := '0';
754 
                fifo_pipe_rd_en : IN std_logic := '0';
755 
                sy_clk_wr_fifo_pipe_empty : OUT std_logic := '0';
756 
                bank_row_last_addr_flag : OUT std_logic := '0';
757 
                bank_row_addr_conflict_flag : OUT std_logic := '0';
758 
                fifo_pipe_burst_valid : OUT std_logic := '0';
759 
                fifo_pipe_valid : OUT std_logic := '0';
760 
                fifo_pipe_out_reg : OUT std_logic_vector(31 downto 0);
761 
                fifo_pipe_wr_count : OUT std_logic_vector(8 downto 0)
762 
                );
763 
        END COMPONENT;
764 
 
765 
 
766 
COMPONENT cal_top
767 
        PORT(
768 
                clk0 : IN std_logic := '0';
769 
                reset : IN std_logic := '0';
770 
                flop2 : OUT std_logic_vector(31 downto 0);
771 
                tapForDqs : OUT std_logic_vector(4 downto 0)
772 
                );
773 
        END COMPONENT;
774 
 
775 
COMPONENT infrastructure
776 
        PORT(
777 
                reset_in : IN std_logic := '0';
778 
                clk_int : IN std_logic := '0';
779 
                clk180_int : IN std_logic := '0';
780 
                clk90_int : IN std_logic := '0';
781 
                dcm_lock : IN std_logic := '0';
782 
                rst_calib1 : IN std_logic := '0';
783 
                ramx_ddr2_delay_sel_val : IN std_logic_vector(4 downto 0);
784 
                delay_sel_val1_val : OUT std_logic_vector(4 downto 0);
785 
                sys_rst_val : OUT std_logic := '0';
786 
                sys_rst90_val : OUT std_logic := '0';
787 
                sys_rst180_val : OUT std_logic := '0';
788 
                sys_rst270_val : OUT std_logic
789 
                );
790 
        END COMPONENT;
791 
 
792 
COMPONENT ddr2_readwrite_fsm
793 
        PORT(
794 
                clk180_int : IN std_logic := '0';
795 
                clk_int_dcm_lock : IN std_logic := '0';
796 
                rst180 : IN std_logic := '0';
797 
                wr_bank_row_last_addr_flag : IN std_logic := '0';
798 
                wr_bank_row_addr_conflict_flag : IN std_logic := '0';
799 
                wr_addr_fifo_pipe_burst_valid : IN std_logic := '0';
800 
                wr_addr_fifo_pipe_valid : IN std_logic := '0';
801 
                ram_fifo_pipe_wr_count : IN std_logic_vector(8 downto 0);
802 
                rd_bank_row_last_addr_flag : IN std_logic := '0';
803 
                rd_bank_row_addr_conflict_flag : IN std_logic := '0';
804 
                rd_addr_fifo_pipe_burst_valid : IN std_logic := '0';
805 
                rd_addr_fifo_pipe_valid : IN std_logic := '0';
806 
                ddr2_ctrl_cmd_ack : IN std_logic := '0';
807 
                ddr2_ctrl_init : IN std_logic := '0';
808 
                ddr2_ctrl_ar_done : IN std_logic := '0';
809 
                wr_addr_fifo_pipe_rd_en : OUT std_logic := '0';
810 
                wr_data_fifo_rd_en : OUT std_logic := '0';
811 
                rd_addr_fifo_pipe_rd_en : OUT std_logic := '0';
812 
                rd_addr_mux_en : OUT std_logic := '0';
813 
                ddr2_ctrl_command_register : OUT std_logic_vector(3 downto 0);
814 
                ddr2_ctrl_burst_done : OUT std_logic
815 
                );
816 
        END COMPONENT;
817 
 
818 
COMPONENT controller
819 
        PORT(
820 
                clk : IN std_logic := '0';
821 
                clk180_int : IN std_logic := '0';
822 
                rst0 : IN std_logic := '0';
823 
                rst180 : IN std_logic := '0';
824 
                address : IN std_logic_vector(22 downto 0);
825 
                bank_address : IN std_logic_vector(1 downto 0);
826 
                config_register1 : IN std_logic_vector(14 downto 0);
827 
                config_register2 : IN std_logic_vector(12 downto 0);
828 
                command_register : IN std_logic_vector(3 downto 0);
829 
                burst_done : IN std_logic := '0';
830 
                ddr_rasb_cntrl : OUT std_logic := '0';
831 
                ddr_casb_cntrl : OUT std_logic := '0';
832 
                ddr_web_cntrl : OUT std_logic := '0';
833 
                ddr_ba_cntrl : OUT std_logic_vector(1 downto 0);
834 
                ddr_address_cntrl : OUT std_logic_vector(12 downto 0);
835 
                ddr_cke_cntrl : OUT std_logic := '0';
836 
                ddr_csb_cntrl : OUT std_logic := '0';
837 
                ddr_ODT_cntrl : OUT std_logic := '0';
838 
                dqs_enable : OUT std_logic := '0';
839 
                dqs_reset : OUT std_logic := '0';
840 
                write_enable : OUT std_logic := '0';
841 
                rst_calib : OUT std_logic := '0';
842 
                rst_dqs_div_int : OUT std_logic := '0';
843 
                cmd_ack : OUT std_logic := '0';
844 
                init : OUT std_logic := '0';
845 
                ar_done : OUT std_logic
846 
                );
847 
        END COMPONENT;
848 
 
849 
 
850 
        COMPONENT ddr2_data_path
851 
        PORT(
852 
                user_input_data : IN std_logic_vector(31 downto 0);
853 
                clk : IN std_logic := '0';
854 
                clk180 : IN std_logic := '0';
855 
                clk90 : IN std_logic := '0';
856 
                reset : IN std_logic := '0';
857 
                reset90 : IN std_logic := '0';
858 
                reset180 : IN std_logic := '0';
859 
                reset270 : IN std_logic := '0';
860 
                write_enable : IN std_logic := '0';
861 
                rst_dqs_div_in : IN std_logic := '0';
862 
                delay_sel : IN std_logic_vector(4 downto 0);
863 
                dqs_int_delay_in0 : IN std_logic := '0';
864 
                dqs_int_delay_in1 : IN std_logic := '0';
865 
                dq_in_rising : IN std_logic_vector(15 downto 0);
866 
                dq_in_falling : IN std_logic_vector(15 downto 0);
867 
                u_data_val : OUT std_logic := '0';
868 
                user_output_data : OUT std_logic_vector(31 downto 0);
869 
                write_en_val : OUT std_logic := '0';
870 
                write_en_val1 : OUT std_logic := '0';
871 
                reset90_r_val : OUT std_logic := '0';
872 
                data_mask_f : OUT std_logic_vector(1 downto 0);
873 
                data_mask_r : OUT std_logic_vector(1 downto 0);
874 
                write_data_falling : OUT std_logic_vector(15 downto 0);
875 
                write_data_rising : OUT std_logic_vector(15 downto 0);
876 
                test_fifo_wr_addr : OUT std_logic_vector(15 downto 0)
877 
                );
878 
        END COMPONENT;
879 
 
880 
 
881 
        COMPONENT ddr2_iobs
882 
        PORT(
883 
                clk0 : IN std_logic := '0';
884 
                clk180 : IN std_logic := '0';
885 
                clk90 : IN std_logic := '0';
886 
                ddr_rasb_cntrl : IN std_logic := '0';
887 
                ddr_ODT_cntrl : IN std_logic := '0';
888 
                ddr_casb_cntrl : IN std_logic := '0';
889 
                ddr_web_cntrl : IN std_logic := '0';
890 
                ddr_cke_cntrl : IN std_logic := '0';
891 
                ddr_csb_cntrl : IN std_logic := '0';
892 
                ddr_address_cntrl : IN std_logic_vector(12 downto 0);
893 
                ddr_ba_cntrl : IN std_logic_vector(1 downto 0);
894 
                rst_dqs_div_int : IN std_logic := '0';
895 
                dqs_reset : IN std_logic := '0';
896 
                dqs_enable : IN std_logic := '0';
897 
                write_data_falling : IN std_logic_vector(15 downto 0);
898 
                write_data_rising : IN std_logic_vector(15 downto 0);
899 
                write_en_val : IN std_logic := '0';
900 
                write_en_val1 : IN std_logic := '0';
901 
                reset90_r : IN std_logic := '0';
902 
                data_mask_f : IN std_logic_vector(1 downto 0);
903 
                data_mask_r : IN std_logic_vector(1 downto 0);
904 
                ddr_dqs : INOUT std_logic_vector(1 downto 0);
905 
                ddr_dq : INOUT std_logic_vector(15 downto 0);
906 
                ddr_ODT0 : OUT std_logic := '0';
907 
                ddr_rasb : OUT std_logic := '0';
908 
                ddr_casb : OUT std_logic := '0';
909 
                ddr_web : OUT std_logic := '0';
910 
                ddr_ba : OUT std_logic_vector(1 downto 0);
911 
                ddr_address : OUT std_logic_vector(15 downto 0);
912 
                ddr_cke : OUT std_logic := '0';
913 
                ddr_csb : OUT std_logic := '0';
914 
                rst_dqs_div_iob : INOUT std_logic := '0';
915 
                rst_dqs_div : OUT std_logic := '0';
916 
                dqs_int_delay_in0 : OUT std_logic := '0';
917 
                dqs_int_delay_in1 : OUT std_logic := '0';
918 
                dq_in_rising : OUT std_logic_vector(15 downto 0);
919 
                dq_in_falling : OUT std_logic_vector(15 downto 0);
920 
                ddr_dm : OUT std_logic_vector(1 downto 0)
921 
                );
922 
        END COMPONENT;
923 
 
924 
 
925 
        COMPONENT vme_mca_ram_read_controller
926 
        PORT(
927 
                sys_clk_100 : IN std_logic := '0';
928 
                reset : IN std_logic := '0';
929 
                vme_ad_ireg : IN std_logic_vector(31 downto 0);
930 
                vme_adcx_addr_ld : IN std_logic := '0';
931 
                vme_adcx_rd : IN std_logic := '0';
932 
                ramx_vme_adcx_rd_dma : IN std_logic := '0';
933 
                ramx_vme_adcx_rd_cycle : IN std_logic := '0';
934 
                ramx_vme_bx_rd_request : IN std_logic := '0';
935 
                ramx_vme_rd_fifo_rd_en : IN std_logic := '0';
936 
                mca_ram_rd_req : IN std_logic := '0';
937 
                mca_ram_rd_addr : IN std_logic_vector(24 downto 0);
938 
                ram_vme_rd_data_fifo_empty : IN std_logic := '0';
939 
                ram_vme_rd_addr_wr_fifo_pipe_empty : IN std_logic := '0';
940 
                ram_vme_rd_addr_fifo_pipe_wr_count : IN std_logic_vector(8 downto 0);
941 
                ram_vme_rd_data_fifo_pipe_rd_count : IN std_logic_vector(8 downto 0);
942 
                ramx_vme_rd_fifo_empty_out : OUT std_logic := '0';
943 
                ramx_vme_rd_gt_out : OUT std_logic := '0';
944 
                mca_ram_rd_gt_out : OUT std_logic := '0';
945 
                mca_ram_rd_data_valid_out : OUT std_logic := '0';
946 
                mca_ram_rd_data_ld1_out : OUT std_logic := '0';
947 
                mca_ram_rd_data_ld2_out : OUT std_logic := '0';
948 
                ram_vme_rd_data_fifo_rd_en_out : OUT std_logic := '0';
949 
                ram_vme_rd_data_fifo_aint_out : OUT std_logic := '0';
950 
                ram_vme_rd_addr_fifo_clr_out : OUT std_logic := '0';
951 
                ram_vme_rd_addr_fifo_wr_en_out : OUT std_logic := '0';
952 
                ram_vme_rd_addr_fifo_d_out : OUT std_logic_vector(31 downto 0)
953 
                );
954 
        END COMPONENT;
955 
 
956 
 
957 
        COMPONENT vme_ram_test_write_controller
958 
        PORT(
959 
                sys_clk_100                                                                             : IN std_logic := '0';
960 
                ram_write_clk                                                                   : IN std_logic := '0';
961 
                vme_ad_ireg                                                                             : IN std_logic_vector(31 downto 0);
962 
                vme_adcx_addr_ld                                                                : IN std_logic := '0';
963 
                vme_ram_wr_cycle                                                                : IN std_logic := '0';
964 
                vme_ram_wr_cmd_pulse                                                    : IN std_logic := '0';
965 
                vme_fpga_test_write_ram_addr_fifo_ce    : OUT std_logic := '0';
966 
                vme_fpga_test_write_ram_data_fifo_ce    : OUT std_logic := '0';
967 
                vme_fpga_test_write_ram_addr_fifo_din   : OUT std_logic_vector(31 downto 0);
968 
                vme_fpga_test_write_ram_data_fifo_din   : OUT std_logic_vector(31 downto 0)
969 
                );
970 
        END COMPONENT;
971 
 
972 
        COMPONENT vme_intf
973 
        PORT(
974 
                MHZ100 : IN std_logic := '0';
975 
                fpga_sel : IN std_logic := '0';
976 
                fpga_ds : IN std_logic := '0';
977 
                fpga_write : IN std_logic := '0';
978 
                fpga_block : IN std_logic := '0';
979 
                fpga_reset_ibuf : IN std_logic := '0';
980 
                fpga_key_reset_ibuf : IN std_logic := '0';
981 
                VME_IN_AD : IN std_logic_vector(31 downto 0);
982 
                adc1_ram_address_counter : IN std_logic_vector(24 downto 0);
983 
                adc2_ram_address_counter : IN std_logic_vector(24 downto 0);
984 
                adc1_last_buffer_ram_address_counter : IN std_logic_vector(24 downto 0);
985 
                adc2_last_buffer_ram_address_counter : IN std_logic_vector(24 downto 0);
986 
                actual_adc1_data_in : IN std_logic_vector(15 downto 0);
987 
                actual_adc2_data_in : IN std_logic_vector(15 downto 0);
988 
                test_in : IN std_logic_vector(31 downto 0);
989 
                test2_in : IN std_logic_vector(31 downto 0);
990 
                vme_0x80_feedback_reg : IN std_logic_vector(31 downto 0);
991 
                vme_0x84_feedback_reg : IN std_logic_vector(31 downto 0);
992 
                vme_0x88_feedback_reg : IN std_logic_vector(31 downto 0);
993 
                vme_0x8C_feedback_reg : IN std_logic_vector(31 downto 0);
994 
                vme_0x90_feedback_reg : IN std_logic_vector(31 downto 0);
995 
                vme_0x94_feedback_reg : IN std_logic_vector(31 downto 0);
996 
                vme_0x98_feedback_reg : IN std_logic_vector(31 downto 0);
997 
                vme_0x9C_feedback_reg : IN std_logic_vector(31 downto 0);
998 
                bank1_rd_data : IN std_logic_vector(31 downto 0);
999 
                bank2_rd_data : IN std_logic_vector(31 downto 0);
1000 
                vme_b1_ff_empty : IN std_logic := '0';
1001 
                vme_b2_ff_empty : IN std_logic := '0';
1002 
                vme_adc1_event_dir_data : IN std_logic_vector(31 downto 0);
1003 
                vme_adc2_event_dir_data : IN std_logic_vector(31 downto 0);
1004 
                event_config_reg : INOUT std_logic_vector(31 downto 0);
1005 
                vme_end_address_threshold_reg : INOUT std_logic_vector(23 downto 2);
1006 
                vme_pretrigger_delay_reg : INOUT std_logic_vector(15 downto 0);
1007 
                vme_trigger_gate_active_window_reg : INOUT std_logic_vector(15 downto 0);
1008 
                vme_buffer_copy_start_addr_reg : INOUT std_logic_vector(15 downto 0);
1009 
                vme_buffer_copy_length_reg : INOUT std_logic_vector(15 downto 0);
1010 
                trigger_flag_latch_cnt_register : INOUT std_logic_vector(31 downto 0);
1011 
                adc1_trigger_setup : INOUT std_logic_vector(31 downto 0);
1012 
                adc1_trigger_threshold : INOUT std_logic_vector(26 downto 0);
1013 
                adc2_trigger_setup : INOUT std_logic_vector(31 downto 0);
1014 
                adc2_trigger_threshold : INOUT std_logic_vector(26 downto 0);
1015 
                vme_0x40_reg : INOUT std_logic_vector(31 downto 0);
1016 
                vme_0x44_reg : INOUT std_logic_vector(15 downto 0);
1017 
                vme_0x48_reg : INOUT std_logic_vector(15 downto 0);
1018 
                vme_0x4C_reg : INOUT std_logic_vector(15 downto 0);
1019 
                vme_0x50_reg : INOUT std_logic_vector(15 downto 0);
1020 
                vme_0x54_reg : INOUT std_logic_vector(15 downto 0);
1021 
                vme_0x58_reg : INOUT std_logic_vector(15 downto 0);
1022 
                vme_0x5C_reg : INOUT std_logic_vector(15 downto 0);
1023 
                vme_0x60_reg : INOUT std_logic_vector(31 downto 0);
1024 
                vme_0x64_reg : INOUT std_logic_vector(31 downto 0);
1025 
                vme_0x68_reg : INOUT std_logic_vector(7 downto 0);
1026 
                vme_b1_rd : INOUT std_logic := '0';
1027 
                vme_b2_rd : INOUT std_logic := '0';
1028 
                vme_adc1_event_dir_rd_ce : INOUT std_logic := '0';
1029 
                vme_adc2_event_dir_rd_ce : INOUT std_logic := '0';
1030 
                vme_adcx_event_dir_addr_reg : INOUT std_logic_vector(8 downto 0);
1031 
                wst_out_en : OUT std_logic := '0';
1032 
                vme_out_wst_oreg : OUT std_logic := '0';
1033 
                vme_out_ad_en : OUT std_logic := '0';
1034 
                VME_OUT_AD : OUT std_logic_vector(31 downto 0);
1035 
                vme_b1_addr_ld : OUT std_logic := '0';
1036 
                vme_b2_addr_ld : OUT std_logic := '0';
1037 
                vme_b1_rd_cmd : OUT std_logic := '0';
1038 
                vme_b2_rd_cmd : OUT std_logic := '0';
1039 
                vme_bx_rd_dma : OUT std_logic := '0';
1040 
                vme_bx_rd_cycle : OUT std_logic := '0';
1041 
                vme_bx_rd_request : OUT std_logic := '0';
1042 
                vme_b1_wr_cycle : OUT std_logic := '0';
1043 
                vme_b2_wr_cycle : OUT std_logic := '0';
1044 
                vme_b1_wr_cmd_pulse : OUT std_logic := '0';
1045 
                vme_b2_wr_cmd_pulse : OUT std_logic
1046 
                );
1047 
        END COMPONENT;
1048 
 
1049 
 
1050 
component postransition_to_pulse is
1051 
  port (
1052 
    clock     : in  std_logic := '0';
1053 
    en_clk    : in  std_logic := '0';
1054 
    signal_in : in  std_logic := '0';
1055 
    pulse     : out std_logic);
1056 
end component;
1057 
 
1058 
 
1059 
attribute IOB : string;
1060 
 
1061 
attribute IOB of InputFD1s: label is "TRUE";
1062 
attribute IOB of InputFD2s: label is "TRUE";
1063 
 
1064 
attribute IOB of Inst_IFD_SAMPLE_LOGIC_RESET: label is "TRUE";
1065 
 
1066 
signal sys_clkfx_out                                                            : std_logic := '0';
1067 
signal dcm_sys_clock_locked                                     : std_logic := '0';
1068 
signal dcm_sys_clock_locked_l                                   : std_logic := '0';
1069 
 
1070 
 
1071 
signal ext_trigger_S                                                            : std_logic := '0';
1072 
signal cmd_start_adc_S                                                  : std_logic := '0';
1073 
signal cmd_soft_trigger_S                                               : std_logic := '0';
1074 
signal cmd_output_select_S                                              : std_logic_vector(3 downto 0) := "0000";
1075 
signal cmd_baseline_enable_S                                    : std_logic := '0';
1076 
signal cmd_double_CF_S                                                  : std_logic := '0';
1077 
signal cmd_program_params_S                                     : std_logic := '0';
1078 
signal cmd_bypass_mwd_S                                                 : std_logic := '0';
1079 
signal cmd_bypass_reshape_S                                     : std_logic := '0';
1080 
 
1081 
signal cmd_enableFE1_S                                                  : std_logic := '0';
1082 
signal cmd_enableFE2_S                                                  : std_logic := '0';
1083 
 
1084 
signal ram1_rd_data_fifo_full : std_logic := '0';
1085 
signal ram2_rd_data_fifo_full : std_logic := '0';
1086 
 
1087 
 
1088 
signal vme_event_config_ADC1 : std_logic_vector(15 downto 0) := (others => '0');
1089 
 
1090 
 attribute syn_keep : boolean;  -- Using Syn_Keep Derictive
1091 
 attribute syn_keep of clk_int : signal is true;
1092 
 
1093 
------------------------------------------------------------------------------------------------------
1094 
begin
1095 
 
1096 
-- fix all undriven pins
1097 
FPGA_ADC1_TRIGGER_L                     <= '0';
1098 
FPGA_ADC2_TRIGGER_L                     <= '0';
1099 
CON_WITH_ADC78_OUT1_L           <= '0';
1100 
FPGA_ADC12_EVENT_END_L          <= '0';
1101 
 
1102 
 
1103 
-- start_up_logic new 25.10.2006
1104 
--start_up_logic:process(system_clk_ibufg)
1105 
-- PL:
1106 
start_up_logic:process(system_clk_ibufg, new_fpga_reset_ibuf, start_delay10)
1107 
begin
1108 
 
1109 
 if rising_edge(system_clk_ibufg) then
1110 
   start_delay1                 <=      '1' ;
1111 
   start_delay2                 <=      start_delay1 ;
1112 
   start_delay3                 <=      start_delay2 ;
1113 
   start_delay4                 <=      start_delay3 ;
1114 
   start_delay5                 <=      start_delay4 ;
1115 
   start_delay6                 <=      start_delay5 ;
1116 
   start_delay7                 <=      start_delay6 ;
1117 
   start_delay8                 <=      start_delay7 ;
1118 
   start_delay9                 <=      start_delay8 ;
1119 
   start_delay10                        <=      start_delay9 ;
1120 
        fpga_reset_ibuf         <=      (NOT i_fpga_reset_l) or (NOT i_fpga_key_reset_l); -- Peter !!
1121 
   fpga_reset_delay             <=      fpga_reset_ibuf  ;
1122 
   new_fpga_reset_ibuf  <=      fpga_reset_ibuf and fpga_reset_delay ;
1123 
 end if;
1124 
 
1125 
   rst  <=    new_fpga_reset_ibuf -- ist nun synchronisiert und deglitched (2 clocks)    ;
1126 
           or not start_delay10 ;
1127 
 
1128 
end process;
1129 
 
1130 
--******************************************************************
1131 
-- system (DDR) clock
1132 
 
1133 
   SYS_CLK_INST : IBUFDS port map (I => system_clk_p, IB => system_clk_n, O => i_system_clk);
1134 
   sys_bufg : BUFG port map ( I => i_system_clk, O => system_clk_ibufg);
1135 
 
1136 
 
1137 
        Inst_sys_clk_dcm: sys_clk_dcm
1138 
                PORT MAP(sys_clk_in                             => system_clk_ibufg,
1139 
                                        rst                                             => rst, -- reset ist wichtig; muss active sein , bis system_clk_ibufg
1140 
                                        sys_clk_out                     => sys_clk_100,
1141 
                                        sys_clkfx_out                   => sys_clkfx_out,
1142 
                                        dcm_sys_clock_locked => dcm_sys_clock_locked,
1143 
                                        sys_clk_div2                    => open --sys_clk_div2 --peter
1144 
        );
1145 
 
1146 
 
1147 
dcm_sys_clock_locked_l <= not dcm_sys_clock_locked ;
1148 
 
1149 
        Inst_ddr_clk_dcm: ddr_clk_dcm PORT MAP(
1150 
                sys_clk => sys_clkfx_out,
1151 
                rst => dcm_sys_clock_locked_l,
1152 
                clk_int => clk_int,
1153 
                clk180_int => clk180_int,
1154 
                clk90_int => clk90_int,
1155 
                clk270_int => clk270_int,
1156 
                dcm_lock => clk_int_dcm_lock,
1157 
                ddr1_clk => ddr1_clk,
1158 
                ddr1_clkb => ddr1_clkb,
1159 
                ddr2_clk => ddr2_clk,
1160 
                ddr2_clkb => ddr2_clkb
1161 
        );
1162 
 
1163 
 
1164 
--******************************************************************
1165 
-- DDR Ram System Reset
1166 
 
1167 
--PL:
1168 
--ram_reset_logic:process(clk180_int)
1169 
ram_reset_logic:process(clk180_int, rst, clk_int_dcm_lock)
1170 
begin
1171 
 
1172 
 if ((rst = '1') or (clk_int_dcm_lock = '0') )  then
1173 
         ddr2_clk_system_reset_cnt <=   "000000";
1174 
         ddr2_clk_system_reset     <=   '1' ;
1175 
  elsif rising_edge(clk180_int) then
1176 
     if (ddr2_clk_system_reset_cnt(5) = '1') then
1177 
         ddr2_clk_system_reset_cnt <=   ddr2_clk_system_reset_cnt ;
1178 
         ddr2_clk_system_reset     <=   '0' ;
1179 
                else
1180 
         ddr2_clk_system_reset_cnt <=   ddr2_clk_system_reset_cnt +  "000001";
1181 
         ddr2_clk_system_reset     <=   '1' ;
1182 
     end if;
1183 
 end if;
1184 
 
1185 
end process;
1186 
 
1187 
 
1188 
--******************************************************************
1189 
-- adc system clock
1190 
--******************************************************************
1191 
 
1192 
SYS_ADC_CLK_INST : IBUFDS port map (I => system_adc_clk_p, IB => system_adc_clk_n, O => i_system_adc_clk);
1193 
sys_adc_bufg : BUFG port map ( I => i_system_adc_clk, O => system_adc_clk);
1194 
 
1195 
OB_OBUFDS1: OBUFDS port map (I => system_adc_clk, O => adc1_clk_out_p, OB => adc1_clk_out_n);
1196 
OB_OBUFDS2: OBUFDS port map (I => system_adc_clk, O => adc2_clk_out_p, OB => adc2_clk_out_n);
1197 
 
1198 
 
1199 
--******************************************************************
1200 
-- inputs
1201 
-- MCA Mode Erweiterung
1202 
-- inputs
1203 
-- ----------------------
1204 
 
1205 
 
1206 
--Inst_IFD_TIMESTAMP_CLR: FD port map (C => system_adc_clk, D => FPGA_ADC_TIMESTAMP_CLR_L, Q => timestamp_clr_l) ;        --
1207 
Inst_IFD_SAMPLE_LOGIC_RESET: FD port map (C => system_adc_clk, D => FPGA_ADC_SAMPLE_LOGIC_RESET_L, Q => adc_sample_logic_reset_l) ;       --
1208 
 
1209 
 
1210 
 
1211 
-- tristate (open col.) outputs
1212 
--PL: was de onderste maar gewoon '0' en '1' op T geeft een tri-state buf voorkomt een drc fout
1213 
Inst_OBUFT_LED_TIMESTAMP_OVERFLOW : OBUFT  port map ( I => '0', T => '1' , O => FPGA_ADC_LED_TIMESTAMP_OVERFLOW_PULSE_L);
1214 
 
1215 
adc12_event_logic_busy   <=    '0' ;  -- wijziging van PL
1216 
iob_adc12_busy : FD port map (Q => FPGA_ADC12_BUSY_L, D => not adc12_event_logic_busy, C => system_adc_clk);
1217 
 
1218 
 
1219 
--******************************************************************
1220 
 
1221 
system_adc_clock_sample_logic: process(system_adc_clk)
1222 
begin
1223 
 
1224 
 
1225 
   if rising_edge (system_adc_clk) then
1226 
       adc_sample_logic_reset <=  not adc_sample_logic_reset_l ;
1227 
   end if;
1228 
 
1229 
end process;
1230 
 
1231 
--******************************************************************
1232 
-- ADC 1        clock
1233 
--******************************************************************
1234 
 
1235 
--**********************************
1236 
-- Inputs : clock and data
1237 
 
1238 
   UIBUFG1 : IBUFDS port map (I => adc1_dco_p, IB => adc1_dco_n, O => adc1_dco_clk);
1239 
    adc1_bufg : BUFG port map ( I => adc1_dco_clk, O => adc1_clk_l);
1240 
   adc1_clk <=  not adc1_clk_l ;
1241 
 
1242 
   InputBuffer: for I in 0 to 15 generate
1243 
                UB11: IBUFDS port map (I => adc1_din_p(I), IB => adc1_din_n(I), O => adc1_buf_din(I));
1244 
   end generate;
1245 
 
1246 
   InputFD1s: for I in 0 to 15 generate
1247 
                UB12: FD port map (C => adc1_clk, D => adc1_buf_din(I), Q => adc1_din(I));
1248 
   end generate;
1249 
 
1250 
 
1251 
 
1252 
--******************************************************************
1253 
-- Protocol and triggering
1254 
--******************************************************************
1255 
vme_event_config_ADC1 <= vme_event_config_reg_S(15 downto 0);
1256 
process(system_adc_clk)
1257 
begin
1258 
   if rising_edge (system_adc_clk) then
1259 
                if vme_event_config_ADC1(14) = '0' then
1260 
                        ext_trigger_S <= FPGA_ADC_PROT14_L; -- trigger_pulse
1261 
                else
1262 
                        ext_trigger_S <= (NOT FPGA_ADC_PROT14_L); -- trigger pulse
1263 
                end if;
1264 
        end if;
1265 
end process;
1266 
 
1267 
 
1268 
        CON_WITH_ADC78_OUT2_L <= '0';
1269 
 
1270 
 
1271 
--******************************************************************
1272 
-- ADC 1        sampling
1273 
--******************************************************************
1274 
Feature_Extraction1: Feature_Extraction
1275 
        port map(uP_CLK                                                                 => clk180_int,
1276 
                                Reset                                                                           => adc_sample_logic_reset,
1277 
                                ADC_CLK                                                                 => adc1_clk,
1278 
                                ADCin                                                                           => adc1_din(15 downto 0),
1279 
                                invert_data_in                                                  => cmd_invert_data_in_S,
1280 
                                externaltrigger                                         => ext_trigger_S,
1281 
                                softwaretrigger                                         => cmd_soft_trigger_S,
1282 
 
1283 
                                cmd_output_select                                               => cmd_output_select_S, --vme_event_config_ADC1(3 downto 0),
1284 
                                cmd_start_adc                                                   => cmd_start_adc_S,
1285 
                                cmd_enableFE                                                    => cmd_enableFE1_S,     --'1',
1286 
                                cmd_baseline_enable                                     => cmd_baseline_enable_S,
1287 
                                cmd_double_CF                                                   => cmd_double_CF_S,
1288 
                                cmd_program_params                                      => cmd_program_params_S,
1289 
                                cmd_bypass_mwd                                                  => cmd_bypass_mwd_S,
1290 
                                cmd_bypass_reshape                                      => cmd_bypass_reshape_S,
1291 
 
1292 
                                decay_correction_in                                     =>      decay_correction_S,
1293 
                                reshape_correction_in                           =>      reshape_correction_S,
1294 
                                buffer_size                                                             => buffer_size_S,
1295 
                                int_signal_threshold_in                         => int_signal_threshold_S,
1296 
                                mwd_pwr_in                                                              => mwd_pwr_S,
1297 
                                cf_pwr_in                                                               => cf_pwr_S,
1298 
                                cf_integral_pwr_in                                      => cf_integral_pwr_S,
1299 
                                baseline_pwr_in                                         => baseline_pwr_S,
1300 
                                baseline_inhibit_cnt_in                         =>      baseline_inhibit_cnt_S,
1301 
                                event_inhibit_cnt_in                                    =>      event_inhibit_cnt_S,
1302 
 
1303 
                                fb_flowctrl_running                                     =>      FE1_running_S,
1304 
                                fb_chain_enable                                         =>      FE1_enable_S,
1305 
                                feedback_port0                                                  =>      feedback_bus0_S,
1306 
                                feedback_port1                                                  =>      feedback_bus1_S,
1307 
                                feedback_port2                                                  => feedback_bus4_S(15 downto 0),
1308 
                                feedback_port3                                                  =>      feedback_bus6_S,
1309 
 
1310 
                                adc_ram_fifo_data_wr_data                       => adc1_ram_fifo_data_wr_data,
1311 
                                adc_ram_fifo_address                                    => adc1_ram_fifo_addr_wr_addr,
1312 
                                adc_ram_fifo_data_wr_ce                         => adc1_ram_fifo_data_wr_ce,
1313 
                                adc_ram_fifo_addr_wr_ce                         => adc1_ram_fifo_addr_wr_ce,
1314 
                                last_buffer_adc_ram_fifo_wr_addr        => adc1_last_buffer_adc_ram_fifo_wr_addr
1315 
                        );
1316 
 
1317 
vme_0x20_reg_S                                          <= (others => '0');      -- to avoid warning
1318 
feedback_bus4_S(31 downto 16)   <=      (others => '0'); -- to avoid warning
1319 
feedback_bus5_S(31 downto 16)   <=      (others => '0'); -- to avoid warning
1320 
 
1321 
mca_ram1_rd_req               <=  '0' ;
1322 
mca_ram1_rd_addr(24)          <=  '0' ;
1323 
mca_ram1_rd_addr(23 downto 0) <=  X"000000" ;
1324 
 
1325 
mca_ram2_rd_req               <=  '0' ;
1326 
mca_ram2_rd_addr(24)          <=  '0' ;
1327 
mca_ram2_rd_addr(23 downto 0) <=  X"000000" ;
1328 
 
1329 
 
1330 
--******************************************************************
1331 
-- ADC 1        Freeze of actual read out values during access
1332 
--******************************************************************
1333 
 
1334 
freeze1_actual_value_logic: process(adc1_clk)
1335 
  begin
1336 
   if rising_edge (adc1_clk) then
1337 
      adc1_clk_fpga_sel_ireg  <=  fpga_sel_ireg ;
1338 
   end if;
1339 
end process;
1340 
 
1341 
--******************************************************************
1342 
-- ADC 2         clock
1343 
--******************************************************************
1344 
 
1345 
-- Inputs : clock and data
1346 
   UIBUFG2 : IBUFDS port map (I => adc2_dco_p, IB => adc2_dco_n, O => adc2_dco_clk);
1347 
   adc2_bufg : BUFG port map ( I => adc2_dco_clk, O => adc2_clk_l);
1348 
   adc2_clk <=  not adc2_clk_l ;
1349 
 
1350 
   InputBuffer2: for I in 0 to 15 generate
1351 
                UB21: IBUFDS port map (I => adc2_din_p(I), IB => adc2_din_n(I), O => adc2_buf_din(I));
1352 
   end generate;
1353 
 
1354 
 
1355 
   InputFD2s: for I in 0 to 15 generate
1356 
                UB22: FD port map (C => adc2_clk, D => adc2_buf_din(I), Q => adc2_din(I));
1357 
   end generate;
1358 
 
1359 
--      FD_ddr_ba1: FD PORT MAP(C => clk180,D => ddr_ba_out(1),Q => buf_ddr_ba(1));
1360 
 
1361 
--******************************************************************
1362 
-- ADC 2        sampling
1363 
--******************************************************************
1364 
--vme_event_config_ADC2 <= vme_event_config_reg_S(31 downto 16);
1365 
 
1366 
Feature_Extraction2: Feature_Extraction
1367 
        port map(uP_CLK                                                                 => clk180_int,
1368 
                                Reset                                                                           => adc_sample_logic_reset,
1369 
                                ADC_CLK                                                                 => adc2_clk,
1370 
                                ADCin                                                                           => adc2_din(15 downto 0),
1371 
                                invert_data_in                                                  => cmd_invert_data_in_S,
1372 
                                externaltrigger                                         => ext_trigger_S,
1373 
                                softwaretrigger                                         => cmd_soft_trigger_S,
1374 
 
1375 
                                cmd_output_select                                               => cmd_output_select_S,
1376 
                                cmd_start_adc                                                   => cmd_start_adc_S,
1377 
                                cmd_enableFE                                                    => cmd_enableFE2_S,     --'1',
1378 
                                cmd_baseline_enable                                     => cmd_baseline_enable_S,
1379 
                                cmd_double_CF                                                   => cmd_double_CF_S,
1380 
                                cmd_program_params                                      => cmd_program_params_S,
1381 
                                cmd_bypass_mwd                                                  => cmd_bypass_mwd_S,
1382 
                                cmd_bypass_reshape                                      => cmd_bypass_reshape_S,
1383 
 
1384 
                                decay_correction_in                                     =>      decay_correction_S,
1385 
                                reshape_correction_in                           =>      reshape_correction_S,
1386 
                                buffer_size                                                             => buffer_size_S,
1387 
                                int_signal_threshold_in                         => int_signal_threshold_S,
1388 
                                mwd_pwr_in                                                              => mwd_pwr_S,
1389 
                                cf_pwr_in                                                               => cf_pwr_S,
1390 
                                cf_integral_pwr_in                                      => cf_integral_pwr_S,
1391 
                                baseline_pwr_in                                         => baseline_pwr_S,
1392 
                                baseline_inhibit_cnt_in                         =>      baseline_inhibit_cnt_S,
1393 
                                event_inhibit_cnt_in                                    =>      event_inhibit_cnt_S,
1394 
 
1395 
                                fb_flowctrl_running                                     =>      FE2_running_S,
1396 
                                fb_chain_enable                                         =>      FE2_enable_S,
1397 
                                feedback_port0                                                  =>      feedback_bus2_S,
1398 
                                feedback_port1                                                  =>      feedback_bus3_S,
1399 
                                feedback_port2                                                  => feedback_bus5_S(15 downto 0),
1400 
                                feedback_port3                                                  =>      open,
1401 
 
1402 
                                adc_ram_fifo_data_wr_data                       => adc2_ram_fifo_data_wr_data,
1403 
                                adc_ram_fifo_address                                    => adc2_ram_fifo_addr_wr_addr,
1404 
                                adc_ram_fifo_data_wr_ce                         => adc2_ram_fifo_data_wr_ce,
1405 
                                adc_ram_fifo_addr_wr_ce                         => adc2_ram_fifo_addr_wr_ce,
1406 
                                last_buffer_adc_ram_fifo_wr_addr        => adc2_last_buffer_adc_ram_fifo_wr_addr
1407 
                        );
1408 
 
1409 
 
1410 
 
1411 
--******************************************************************
1412 
-- ADC 2        Freeze of actual read out values during access
1413 
--******************************************************************
1414 
 
1415 
freeze2_actual_value_logic: process(adc2_clk)
1416 
  begin
1417 
   if rising_edge (adc2_clk) then
1418 
      adc2_clk_fpga_sel_ireg  <=  fpga_sel_ireg ;
1419 
   end if;
1420 
 
1421 
end process;
1422 
 
1423 
--*** DDR2 Configuration  --
1424 
 
1425 
ddr_config_register1 <= "001100001000010" ; -- WR=4 CAS Latency 4,   Burst Length = 4
1426 
ddr_config_register2 <= "0010000000000" ; -- DQS disable
1427 
 
1428 
ramx_ddr2_delay_sel <= "10111" ; -- B8
1429 
 
1430 
 
1431 
--*********************************************************************************************
1432 
--*** RAM1  DDR2 Controller  --
1433 
--*********************************************************************************************
1434 
 
1435 
        vme_mca_ram1_read_controller: vme_mca_ram_read_controller
1436 
                PORT MAP(sys_clk_100                                                                    => sys_clk_100,
1437 
                                        reset                                                                                   => ddr2_clk_system_reset,
1438 
                                        vme_ad_ireg                                                                     => vme_ad_ireg,
1439 
                                        vme_adcx_addr_ld                                                        => vme_b1_addr_ld,
1440 
                                        vme_adcx_rd                                                                     => vme_b1_rd,
1441 
                                        ramx_vme_adcx_rd_dma                                            => ramx_vme_bx_rd_dma,
1442 
                                        ramx_vme_adcx_rd_cycle                                  => ramx_vme_bx_rd_cycle,
1443 
                                        ramx_vme_bx_rd_request                                  => ramx_vme_bx_rd_request,
1444 
 
1445 
                                        ramx_vme_rd_fifo_rd_en                                  => ram1_vme_rd_fifo_rd_en,
1446 
                                        ramx_vme_rd_fifo_empty_out                              => ram1_vme_rd_data_fifo_empty,
1447 
                                        ramx_vme_rd_gt_out                                              => open,
1448 
 
1449 
                                        mca_ram_rd_req                                                          => mca_ram1_rd_req,
1450 
                                        mca_ram_rd_addr                                                 => mca_ram1_rd_addr(24 downto 0),
1451 
                                        mca_ram_rd_gt_out                                                       => mca_ram1_rd_gt,
1452 
                                        mca_ram_rd_data_valid_out                               => mca_ram1_rd_data_valid,
1453 
                                        mca_ram_rd_data_ld1_out                                 => mca_ram1_rd_data_ld1,
1454 
                                        mca_ram_rd_data_ld2_out                                 => mca_ram1_rd_data_ld2,
1455 
 
1456 
                                        ram_vme_rd_data_fifo_empty                              => ram1_rd_data_fifo_empty,
1457 
                                        ram_vme_rd_addr_wr_fifo_pipe_empty      => ram1_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.8.2009
1458 
                                        ram_vme_rd_addr_fifo_pipe_wr_count      => ram1_vme_rd_addr_fifo_pipe_wr_count(8 downto 0),
1459 
                                        ram_vme_rd_data_fifo_pipe_rd_count      => ram1_vme_rd_data_fifo_pipe_rd_count(8 downto 0),
1460 
                                        ram_vme_rd_data_fifo_rd_en_out          => ram1_rd_fifo_rd_en,
1461 
                                        ram_vme_rd_data_fifo_aint_out                   => ram1_vme_rd_data_fifo_aint,
1462 
                                        ram_vme_rd_addr_fifo_clr_out                    => ram1_vme_rd_addr_fifo_clr,
1463 
                                        ram_vme_rd_addr_fifo_wr_en_out          => ram1_vme_rd_addr_fifo_wr_en,
1464 
                                        ram_vme_rd_addr_fifo_d_out                              => ram1_vme_rd_addr_fifo_d
1465 
                                );
1466 
 
1467 
 
1468 
mca_ram1_fifo_rd_logic: process(sys_clk_100)
1469 
begin
1470 
   if rising_edge (sys_clk_100) then
1471 
      if (mca_ram1_rd_data_ld1 = '1') then
1472 
          mca_ram1_rd_data_fifo_first_word  <=  ram1_rd_data_fifo_q ;
1473 
                 else
1474 
          mca_ram1_rd_data_fifo_first_word  <=  mca_ram1_rd_data_fifo_first_word ;
1475 
                end if ;
1476 
   end if;
1477 
   if rising_edge (sys_clk_100) then
1478 
      if (mca_ram1_rd_data_ld2 = '1') then
1479 
          mca_ram1_rd_data_fifo_second_word  <=  ram1_rd_data_fifo_q ;
1480 
                 else
1481 
          mca_ram1_rd_data_fifo_second_word  <=  mca_ram1_rd_data_fifo_second_word ;
1482 
                end if ;
1483 
   end if;
1484 
end process;
1485 
 
1486 
 
1487 
ram1_infrastructure: infrastructure
1488 
        PORT MAP(reset_in                                               => ddr2_clk_system_reset,
1489 
                                clk_int                                         => clk_int,
1490 
                                clk180_int                                      => clk180_int,
1491 
                                clk90_int                                       => clk90_int,
1492 
                                dcm_lock                                                => clk_int_dcm_lock,
1493 
                                rst_calib1                                      => ram1_ddr2_rst_calib1,
1494 
                                ramx_ddr2_delay_sel_val => ramx_ddr2_delay_sel,
1495 
                                delay_sel_val1_val              => ram1_ddr2_delay_sel,
1496 
                                sys_rst_val                                     => ram1_ddr2_sys_rst,
1497 
                                sys_rst90_val                           => ram1_ddr2_sys_rst90,
1498 
                                sys_rst180_val                          => ram1_ddr2_sys_rst180_orig,
1499 
                                sys_rst270_val                          => ram1_ddr2_sys_rst270
1500 
                        );
1501 
 
1502 
 
1503 
        ram1_ddr2_sys_rst180 <= '1' when (ram1_ddr2_sys_rst180_orig='1') else '0';
1504 
 
1505 
        ram1_read_vme_address_fifo_pipe_asynch_reset  <=  ram1_ddr2_sys_rst180 or ram1_vme_rd_addr_fifo_clr ;
1506 
 
1507 
 
1508 
ram1_read_vme_address_fifo_pipe: ram_address_fifo_pipe
1509 
        PORT MAP(clk_wr                                                         => sys_clk_100,
1510 
                                clk180                                                          => clk180_int,
1511 
                                asynch_reset                                            => ram1_read_vme_address_fifo_pipe_asynch_reset,
1512 
                                fifo_input_d                                            => ram1_vme_rd_addr_fifo_d,
1513 
                                fifo_input_wr_en                                        => ram1_vme_rd_addr_fifo_wr_en,
1514 
                                fifo_pipe_rd_en                                 => ram1_vme_rd_addr_fifo_pipe_rd_en,
1515 
                                sy_clk_wr_fifo_pipe_empty               => ram1_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.08.2009
1516 
                                bank_row_last_addr_flag                 => ram1_vme_rd_bank_row_last_addr_flag,
1517 
                                bank_row_addr_conflict_flag     => ram1_vme_rd_bank_row_addr_conflict_flag,
1518 
                                fifo_pipe_burst_valid                   => ram1_vme_rd_addr_fifo_pipe_burst_valid,
1519 
                                fifo_pipe_valid                                 => ram1_vme_rd_addr_fifo_pipe_valid,
1520 
                                fifo_pipe_out_reg                                       => ram1_vme_rd_addr_fifo_q,
1521 
                                fifo_pipe_wr_count                              => ram1_vme_rd_addr_fifo_pipe_wr_count
1522 
                        );
1523 
 
1524 
 
1525 
ram1_vme_rd_data_fifo : blk_asy_fifo_511x32
1526 
        port map (din           => ram1_ddr2_user_output_data,
1527 
                                                wr_en           => ram1_ddr2_user_data_val,
1528 
                                                wr_clk  => clk90_int,                                    -- daten werden mit clk90 uebernommen
1529 
                                                rd_en           => ram1_rd_fifo_rd_en,
1530 
                                                rd_clk  => sys_clk_100,
1531 
                                                ainit           => ram1_vme_rd_data_fifo_aint,
1532 
                                                dout            => ram1_rd_data_fifo_q,
1533 
                                                full            => ram1_rd_data_fifo_full,
1534 
                                                empty           => ram1_rd_data_fifo_empty,
1535 
                                                wr_count        => open,
1536 
                                                rd_count        => ram1_vme_rd_data_fifo_pipe_rd_count
1537 
                                        );
1538 
 
1539 
-- **********************************
1540 
-- write to DDR2
1541 
 
1542 
        ch1_vme_ram_test_write_controller: vme_ram_test_write_controller
1543 
                PORT MAP(sys_clk_100                                                                            => sys_clk_100,
1544 
                                        ram_write_clk                                                                   => clk180_int,
1545 
                                        vme_ad_ireg                                                                             => vme_ad_ireg,
1546 
                                        vme_adcx_addr_ld                                                                => vme_b1_addr_ld,
1547 
                                        vme_ram_wr_cycle                                                                => vme_ram1_wr_cycle,
1548 
                                        vme_ram_wr_cmd_pulse                                                    => vme_ram1_wr_cmd_pulse,
1549 
                                        vme_fpga_test_write_ram_addr_fifo_ce    => ch1_vme_test_write_ram_addr_fifo_ce,
1550 
                                        vme_fpga_test_write_ram_data_fifo_ce    => ch1_vme_test_write_ram_data_fifo_ce,
1551 
                                        vme_fpga_test_write_ram_addr_fifo_din   => ch1_vme_test_write_ram_addr_fifo_din,
1552 
                                        vme_fpga_test_write_ram_data_fifo_din   => ch1_vme_test_write_ram_data_fifo_din
1553 
                                );
1554 
 
1555 
 
1556 
ram1_ddr2_write_multiplexer: process (clk180_int)
1557 
begin
1558 
   if  rising_edge(clk180_int) then  --
1559 
              mux_adc1_ram_fifo_addr_wr_ce    <=   adc1_ram_fifo_addr_wr_ce  ; --
1560 
              mux_adc1_ram_fifo_addr_wr_addr  <=   adc1_ram_fifo_addr_wr_addr    ; --
1561 
              mux_adc1_ram_fifo_data_wr_ce    <=   adc1_ram_fifo_data_wr_ce  ; --
1562 
              mux_adc1_ram_fifo_data_wr_data  <=   adc1_ram_fifo_data_wr_data    ; --
1563 
   end if;
1564 
end process;
1565 
 
1566 
 
1567 
-- addr
1568 
ram1_write_address_fifo_pipe: ram_address_fifo_pipe
1569 
        PORT MAP(clk_wr => clk180_int,
1570 
                                clk180 => clk180_int,
1571 
                                asynch_reset                                            => ram1_ddr2_sys_rst180,
1572 
                                fifo_input_d                                            => mux_adc1_ram_fifo_addr_wr_addr,
1573 
                                fifo_input_wr_en                                        => mux_adc1_ram_fifo_addr_wr_ce,
1574 
                                fifo_pipe_rd_en                                 => ram1_vme_wr_addr_fifo_pipe_rd_en,
1575 
                                sy_clk_wr_fifo_pipe_empty               => open, -- new 14.08.2009
1576 
                                bank_row_last_addr_flag                 => ram1_wr_bank_row_last_addr_flag,
1577 
                                bank_row_addr_conflict_flag     => ram1_wr_bank_row_addr_conflict_flag,
1578 
                                fifo_pipe_burst_valid                   => ram1_wr_addr_fifo_pipe_burst_valid,
1579 
                                fifo_pipe_valid                                 => ram1_vme_wr_addr_fifo_pipe_valid,
1580 
                                fifo_pipe_out_reg                                       =>  ram1_vme_wr_addr_fifo_q,
1581 
                                fifo_pipe_wr_count                              =>  ram1_fifo_pipe_wr_count
1582 
                        );
1583 
 
1584 
 
1585 
 
1586 
ram1_vme_wr_data_fifoH : blk_asy_fifo_1023x16
1587 
        port map(din            => mux_adc1_ram_fifo_data_wr_data(15 downto 0),
1588 
                                wr_en           => mux_adc1_ram_fifo_data_wr_ce,
1589 
                                wr_clk  => clk180_int,
1590 
                                rd_en           => ram1_vme_wr_fifo_rd_en,
1591 
                                rd_clk  => clk180_int,
1592 
                                ainit           => ram1_ddr2_sys_rst180, --ram1_ddr2_sys_rst, mod. 25.10.2006
1593 
                                dout            => ram1_ddr2_user_input_data(15 downto 0), --
1594 
                                full            => adc1_ram_fifo_data_full,
1595 
                                empty           => ram1_ddr2_wr_data_rd_empty,
1596 
                                wr_count        => ram1_ddr2_wr_data_wr_count,
1597 
                                rd_count        => ram1_ddr2_wr_data_rd_count
1598 
                        );
1599 
 
1600 
ram1_vme_wr_data_fifoL : blk_asy_fifo_1023x16
1601 
        port map(din            => mux_adc1_ram_fifo_data_wr_data(31 downto 16),
1602 
                                wr_en           => mux_adc1_ram_fifo_data_wr_ce,
1603 
                                wr_clk  => clk180_int,
1604 
                                rd_en           => ram1_vme_wr_fifo_rd_en,
1605 
                                rd_clk  => clk180_int,
1606 
                                ainit           => ram1_ddr2_sys_rst180, --ram1_ddr2_sys_rst, mod. 25.10.2006
1607 
                                dout            => ram1_ddr2_user_input_data(31 downto 16), --
1608 
                                full            => open,
1609 
                                empty           => open,
1610 
                                wr_count        => open,
1611 
                                rd_count        => open
1612 
                        );
1613 
 
1614 
--temp_24(31)             <= ram1_test_error_flag ;
1615 
temp_24(31 downto 25)   <= "0000000" ;
1616 
temp_24(24 downto 16)   <= ram1_fifo_pipe_wr_count(8 downto 0) ;
1617 
 
1618 
temp_24(15 downto 10)   <= "000000" ;
1619 
temp_24(9 downto 0)     <= ram1_ddr2_wr_data_wr_count(9 downto 0) ;
1620 
 
1621 
temp_28(31 downto 25)   <= "0000000" ;
1622 
temp_28(24 downto 16)   <= ram2_fifo_pipe_wr_count(8 downto 0) ;
1623 
 
1624 
temp_28(15 downto 10)   <= "000000" ;
1625 
temp_28(9 downto 0)     <= ram2_ddr2_wr_data_wr_count(9 downto 0) ;
1626 
 
1627 
 
1628 
 
1629 
ram1_ddr2_readwrite_fsm: ddr2_readwrite_fsm
1630 
        PORT MAP(clk180_int                                                             => clk180_int,
1631 
                                clk_int_dcm_lock                                                => clk_int_dcm_lock,
1632 
                                rst180                                                                  => ram1_ddr2_sys_rst180,
1633 
 
1634 
                                wr_bank_row_last_addr_flag                      => ram1_wr_bank_row_last_addr_flag,
1635 
                                wr_bank_row_addr_conflict_flag  => ram1_wr_bank_row_addr_conflict_flag,
1636 
                                wr_addr_fifo_pipe_burst_valid           => ram1_wr_addr_fifo_pipe_burst_valid,
1637 
                                wr_addr_fifo_pipe_valid                         => ram1_vme_wr_addr_fifo_pipe_valid,
1638 
                                wr_addr_fifo_pipe_rd_en                         => ram1_vme_wr_addr_fifo_pipe_rd_en,
1639 
                                wr_data_fifo_rd_en                                      => ram1_vme_wr_fifo_rd_en,
1640 
                                ram_fifo_pipe_wr_count                          => ram1_fifo_pipe_wr_count,
1641 
 
1642 
                                rd_bank_row_last_addr_flag                      => ram1_vme_rd_bank_row_last_addr_flag,
1643 
                                rd_bank_row_addr_conflict_flag  => ram1_vme_rd_bank_row_addr_conflict_flag,
1644 
                                rd_addr_fifo_pipe_burst_valid           => ram1_vme_rd_addr_fifo_pipe_burst_valid,
1645 
                                rd_addr_fifo_pipe_valid                         => ram1_vme_rd_addr_fifo_pipe_valid,
1646 
                                rd_addr_fifo_pipe_rd_en                         => ram1_vme_rd_addr_fifo_pipe_rd_en,
1647 
                                rd_addr_mux_en                                                  => ram1_rd_addr_mux_en,
1648 
                                ddr2_ctrl_command_register                      => ram1_ddr2_command_register,
1649 
                                ddr2_ctrl_burst_done                                    => ram1_ddr2_burst_done,
1650 
                                ddr2_ctrl_cmd_ack                                               => ram1_ddr2_cmd_ack,
1651 
                                ddr2_ctrl_init                                                  => ram1_ddr2_init_done,
1652 
                                ddr2_ctrl_ar_done                                               => ram1_ddr2_autorefresh_done
1653 
                        );
1654 
 
1655 
 
1656 
        ram1_ddr2_controller_address(24 downto 0)  <=   ram1_vme_wr_addr_fifo_q(24 downto 0)  when  (ram1_rd_addr_mux_en = '0')    else
1657 
                                                        ram1_vme_rd_addr_fifo_q(24 downto 0) ;
1658 
 
1659 
        ram1_controller: controller
1660 
                PORT MAP(clk                                    => clk_int,
1661 
                                        clk180_int                      => clk180_int,
1662 
                                        rst0                                    => ram1_ddr2_sys_rst,
1663 
                                        rst180                          => ram1_ddr2_sys_rst180,
1664 
                                        address                         => ram1_ddr2_controller_address(22 downto 0),
1665 
                                        bank_address            => ram1_ddr2_controller_address(24 downto 23),
1666 
                                        config_register1        => ddr_config_register1,
1667 
                                        config_register2        => ddr_config_register2,
1668 
                                        command_register        => ram1_ddr2_command_register,
1669 
                                        burst_done                      => ram1_ddr2_burst_done,
1670 
                                        ddr_rasb_cntrl          => ram1_ddr2_rasb_cntrl,
1671 
                                        ddr_casb_cntrl          => ram1_ddr2_casb_cntrl,
1672 
                                        ddr_web_cntrl           => ram1_ddr2_web_cntrl,
1673 
                                        ddr_ba_cntrl            => ram1_ddr2_ba_cntrl,
1674 
                                        ddr_address_cntrl       => ram1_ddr2_address_cntrl,
1675 
                                        ddr_cke_cntrl           => ram1_ddr2_cke_cntrl,
1676 
                                        ddr_csb_cntrl           => ram1_ddr2_csb_cntrl,
1677 
                                        ddr_ODT_cntrl           => ram1_ddr2_ODT_cntrl,
1678 
                                        dqs_enable                      => ram1_ddr2_dqs_enable,
1679 
                                        dqs_reset                       => ram1_ddr2_dqs_reset,
1680 
                                        write_enable            => ram1_ddr2_write_enable,
1681 
                                        rst_calib                       => ram1_ddr2_rst_calib1,
1682 
                                        rst_dqs_div_int => ram1_ddr2_rst_dqs_div_int,
1683 
                                        cmd_ack                         => ram1_ddr2_cmd_ack,
1684 
                                        init                                    => ram1_ddr2_init_done,
1685 
                                        ar_done                         => ram1_ddr2_autorefresh_done    -- output
1686 
                                );
1687 
 
1688 
        ram1_ddr2_data_path: ddr2_data_path PORT MAP(
1689 
                user_input_data         => ram1_ddr2_user_input_data,
1690 
                clk                                             => clk_int,
1691 
                clk180                                  => clk180_int,
1692 
                clk90                                           => clk90_int,
1693 
                reset                                           => ram1_ddr2_sys_rst,
1694 
                reset90                                 => ram1_ddr2_sys_rst90,
1695 
                reset180                                        => ram1_ddr2_sys_rst180,
1696 
                reset270                                        => ram1_ddr2_sys_rst270,
1697 
                write_enable                    => ram1_ddr2_write_enable,
1698 
                rst_dqs_div_in                  => ram1_ddr2_rst_dqs_div,
1699 
                delay_sel                               => ram1_ddr2_delay_sel,
1700 
                dqs_int_delay_in0               => ram1_ddr2_dqs_int_delay_in0,
1701 
                dqs_int_delay_in1               => ram1_ddr2_dqs_int_delay_in1,
1702 
                dq_in_rising                    => ram1_ddr2_dq_in_rising,
1703 
                dq_in_falling                   => ram1_ddr2_dq_in_falling,
1704 
                u_data_val                              => ram1_ddr2_user_data_val,
1705 
                user_output_data                => ram1_ddr2_user_output_data,
1706 
                write_en_val                    => ram1_ddr2_write_en_val,
1707 
                write_en_val1                   => ram1_ddr2_write_en_val1,
1708 
                reset90_r_val                   => ram1_ddr2_reset90_r,
1709 
                data_mask_f                             => ram1_ddr2_data_mask_f,
1710 
                data_mask_r                             => ram1_ddr2_data_mask_r,
1711 
                write_data_falling      => ram1_ddr2_write_data_falling,
1712 
                write_data_rising               => ram1_ddr2_write_data_rising,
1713 
                test_fifo_wr_addr               => ram1_test_fifo_wr_addr
1714 
        );
1715 
 
1716 
 
1717 
        ram1_ddr2_iobs: ddr2_iobs PORT MAP(
1718 
                clk0                                            => clk_int,
1719 
                clk180                                  => clk180_int,
1720 
                clk90                                           => clk90_int,
1721 
                ddr_rasb_cntrl                  => ram1_ddr2_rasb_cntrl,
1722 
                ddr_ODT_cntrl                   => ram1_ddr2_ODT_cntrl,
1723 
                ddr_casb_cntrl                  => ram1_ddr2_casb_cntrl,
1724 
                ddr_web_cntrl                   => ram1_ddr2_web_cntrl,
1725 
                ddr_cke_cntrl                   => ram1_ddr2_cke_cntrl,
1726 
                ddr_csb_cntrl                   => ram1_ddr2_csb_cntrl,
1727 
                ddr_address_cntrl               => ram1_ddr2_address_cntrl,
1728 
                ddr_ba_cntrl                    => ram1_ddr2_ba_cntrl,
1729 
                rst_dqs_div_int         => ram1_ddr2_rst_dqs_div_int,
1730 
                dqs_reset                               => ram1_ddr2_dqs_reset,
1731 
                dqs_enable                              => ram1_ddr2_dqs_enable,
1732 
                ddr_dqs                                 => ddr1_dqs,
1733 
                ddr_dq                                  => ddr1_dq,
1734 
                write_data_falling      => ram1_ddr2_write_data_falling,
1735 
                write_data_rising               => ram1_ddr2_write_data_rising,
1736 
                write_en_val                    => ram1_ddr2_write_en_val,
1737 
                write_en_val1                   => ram1_ddr2_write_en_val1,
1738 
                reset90_r                               => ram1_ddr2_reset90_r,
1739 
                data_mask_f                             => ram1_ddr2_data_mask_f,
1740 
                data_mask_r                             => ram1_ddr2_data_mask_r,
1741 
                ddr_ODT0                                        => ddr1_ODT0,
1742 
                ddr_rasb                                        => ddr1_rasb,
1743 
                ddr_casb                                        => ddr1_casb,
1744 
                ddr_web                                 => ddr1_web,
1745 
                ddr_ba                                  => ddr1_ba,
1746 
                ddr_address                             => ddr1_address,
1747 
                ddr_cke                                 => ddr1_cke,
1748 
                ddr_csb                                 => ddr1_csb,
1749 
                rst_dqs_div                             => ram1_ddr2_rst_dqs_div,
1750 
                rst_dqs_div_iob         => ddr1_rst_dqs_div_iob,
1751 
                dqs_int_delay_in0               => ram1_ddr2_dqs_int_delay_in0,
1752 
                dqs_int_delay_in1               => ram1_ddr2_dqs_int_delay_in1,
1753 
                dq_in_rising                    => ram1_ddr2_dq_in_rising,
1754 
                dq_in_falling                   => ram1_ddr2_dq_in_falling,
1755 
                ddr_dm                                  => ddr1_dm
1756 
        );
1757 
 
1758 
 
1759 
--PL
1760 
U0      : OBUFT  port map (     I => '0',
1761 
                                                                T => '1' ,
1762 
                                                                O => CON_WITH_ADC12_OUT1_L);
1763 
U1 : OBUFT  port map (  I => '0',
1764 
                                                                T => '1' ,
1765 
                                                                O => CON_WITH_ADC12_OUT2_L);
1766 
--PL
1767 
 
1768 
U20 : OBUFT  port map ( I => '0',
1769 
                        T => '1' ,
1770 
                        O => ddr1_dqs_reserve(0));
1771 
U21 : OBUFT  port map ( I => '0',
1772 
                        T => '1' ,
1773 
                        O => ddr1_dqs_reserve(1));
1774 
 
1775 
 
1776 
ddr1_ba2_reserve <= '0' ; -- only to force to use the pad
1777 
 
1778 
 
1779 
 
1780 
--*********************************************************************************************
1781 
--*** RAM2  DDR2 Controller  --
1782 
--*********************************************************************************************
1783 
 
1784 
 
1785 
        vme_mca_ram2_read_controller: vme_mca_ram_read_controller PORT MAP(
1786 
                sys_clk_100                                                                     => sys_clk_100,
1787 
                reset                                                                                   => ddr2_clk_system_reset,
1788 
                vme_ad_ireg                                                                     => vme_ad_ireg,
1789 
                vme_adcx_addr_ld                                                        => vme_b2_addr_ld,
1790 
                vme_adcx_rd                                                                     => vme_b2_rd,
1791 
                ramx_vme_adcx_rd_dma                                            => ramx_vme_bx_rd_dma,
1792 
                ramx_vme_adcx_rd_cycle                                  => ramx_vme_bx_rd_cycle,
1793 
                ramx_vme_bx_rd_request                                  => ramx_vme_bx_rd_request,
1794 
 
1795 
                ramx_vme_rd_fifo_rd_en                                  => ram2_vme_rd_fifo_rd_en,
1796 
                ramx_vme_rd_fifo_empty_out                              => ram2_vme_rd_data_fifo_empty,
1797 
                ramx_vme_rd_gt_out                                              => open,
1798 
 
1799 
                mca_ram_rd_req                                                          => mca_ram2_rd_req,
1800 
                mca_ram_rd_addr                                                 => mca_ram2_rd_addr(24 downto 0),
1801 
                mca_ram_rd_gt_out                                                       => mca_ram2_rd_gt,
1802 
                mca_ram_rd_data_valid_out                               => mca_ram2_rd_data_valid,
1803 
                mca_ram_rd_data_ld1_out                                 => mca_ram2_rd_data_ld1,
1804 
                mca_ram_rd_data_ld2_out                                 => mca_ram2_rd_data_ld2,
1805 
 
1806 
                ram_vme_rd_data_fifo_empty                              => ram2_rd_data_fifo_empty,
1807 
                ram_vme_rd_addr_wr_fifo_pipe_empty      => ram2_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.8.2009
1808 
                ram_vme_rd_addr_fifo_pipe_wr_count      => ram2_vme_rd_addr_fifo_pipe_wr_count(8 downto 0),
1809 
                ram_vme_rd_data_fifo_pipe_rd_count      => ram2_vme_rd_data_fifo_pipe_rd_count(8 downto 0),
1810 
                ram_vme_rd_data_fifo_rd_en_out          => ram2_rd_fifo_rd_en,
1811 
                ram_vme_rd_data_fifo_aint_out                   => ram2_vme_rd_data_fifo_aint,
1812 
                ram_vme_rd_addr_fifo_clr_out                    => ram2_vme_rd_addr_fifo_clr,
1813 
                ram_vme_rd_addr_fifo_wr_en_out          => ram2_vme_rd_addr_fifo_wr_en,
1814 
                ram_vme_rd_addr_fifo_d_out                              => ram2_vme_rd_addr_fifo_d
1815 
        );
1816 
 
1817 
 
1818 
mca_ram2_fifo_rd_logic: process(sys_clk_100)
1819 
begin
1820 
   if rising_edge (sys_clk_100) then
1821 
      if (mca_ram2_rd_data_ld1 = '1') then
1822 
          mca_ram2_rd_data_fifo_first_word  <=  ram2_rd_data_fifo_q ;
1823 
                 else
1824 
          mca_ram2_rd_data_fifo_first_word  <=  mca_ram2_rd_data_fifo_first_word ;
1825 
                end if ;
1826 
   end if;
1827 
   if rising_edge (sys_clk_100) then
1828 
      if (mca_ram2_rd_data_ld2 = '1') then
1829 
          mca_ram2_rd_data_fifo_second_word  <=  ram2_rd_data_fifo_q ;
1830 
                 else
1831 
          mca_ram2_rd_data_fifo_second_word  <=  mca_ram2_rd_data_fifo_second_word ;
1832 
                end if ;
1833 
   end if;
1834 
end process;
1835 
 
1836 
 
1837 
----ram2_read_vme_address_fifo_pipe_asynch_reset  <=  ram2_ddr2_sys_rst180 or ram2_vme_rd_addr_fifo_clr ;
1838 
ram2_read_vme_address_fifo_pipe_asynch_reset  <=  ram2_ddr2_sys_rst180 ; -- or ram2_vme_rd_addr_fifo_clr ;
1839 
 
1840 
 
1841 
ram2_read_vme_address_fifo_pipe: ram_address_fifo_pipe
1842 
        PORT MAP(clk_wr                                                         => sys_clk_100,
1843 
                                clk180                                                          => clk180_int,
1844 
                                asynch_reset                                            => ram2_read_vme_address_fifo_pipe_asynch_reset,
1845 
                                fifo_input_d                                            => ram2_vme_rd_addr_fifo_d,
1846 
                                fifo_input_wr_en                                        => ram2_vme_rd_addr_fifo_wr_en,
1847 
                                fifo_pipe_rd_en                                 => ram2_vme_rd_addr_fifo_pipe_rd_en,
1848 
                                sy_clk_wr_fifo_pipe_empty               => ram2_vme_rd_addr_wr_fifo_pipe_empty, -- new 14.08.2009
1849 
                                bank_row_last_addr_flag                 => ram2_vme_rd_bank_row_last_addr_flag,
1850 
                                bank_row_addr_conflict_flag     => ram2_vme_rd_bank_row_addr_conflict_flag,
1851 
                                fifo_pipe_burst_valid                   => ram2_vme_rd_addr_fifo_pipe_burst_valid,
1852 
                                fifo_pipe_valid                                 => ram2_vme_rd_addr_fifo_pipe_valid,
1853 
                                fifo_pipe_out_reg                                       =>  ram2_vme_rd_addr_fifo_q,
1854 
                                fifo_pipe_wr_count                              =>  ram2_vme_rd_addr_fifo_pipe_wr_count
1855 
                        );
1856 
 
1857 
 
1858 
ram2_vme_rd_data_fifo : blk_asy_fifo_511x32
1859 
        port map(din            => ram2_ddr2_user_output_data,
1860 
                                wr_en           => ram2_ddr2_user_data_val,
1861 
                                wr_clk  => clk90_int,                                    -- daten werden mit clk90 uebernommen
1862 
                                rd_en           => ram2_rd_fifo_rd_en,
1863 
                                rd_clk  => sys_clk_100,
1864 
                                ainit           => ram2_vme_rd_data_fifo_aint,
1865 
                                dout            => ram2_rd_data_fifo_q,
1866 
                                full            => ram2_rd_data_fifo_full,
1867 
                                empty           => ram2_rd_data_fifo_empty,
1868 
                                wr_count        => open,
1869 
                                rd_count        => ram2_vme_rd_data_fifo_pipe_rd_count
1870 
                        );
1871 
 
1872 
-- **********************************
1873 
 
1874 
-- write to DDR2
1875 
 
1876 
ch2_vme_ram_test_write_controller: vme_ram_test_write_controller
1877 
        PORT MAP(sys_clk_100                                                                            => sys_clk_100,
1878 
                                ram_write_clk                                                                   => clk180_int,
1879 
                                vme_ad_ireg                                                                             => vme_ad_ireg,
1880 
                                vme_adcx_addr_ld                                                                => vme_b2_addr_ld,
1881 
                                vme_ram_wr_cycle                                                                => vme_ram2_wr_cycle,
1882 
                                vme_ram_wr_cmd_pulse                                                    => vme_ram2_wr_cmd_pulse,
1883 
                                vme_fpga_test_write_ram_addr_fifo_ce    => ch2_vme_test_write_ram_addr_fifo_ce,
1884 
                                vme_fpga_test_write_ram_data_fifo_ce    => ch2_vme_test_write_ram_data_fifo_ce,
1885 
                                vme_fpga_test_write_ram_addr_fifo_din   => ch2_vme_test_write_ram_addr_fifo_din,
1886 
                                vme_fpga_test_write_ram_data_fifo_din   => ch2_vme_test_write_ram_data_fifo_din
1887 
                        );
1888 
 
1889 
 
1890 
 
1891 
ram2_ddr2_write_multiplexer: process (clk180_int)
1892 
begin
1893 
   if  rising_edge(clk180_int) then  --
1894 
              mux_adc2_ram_fifo_addr_wr_ce    <=   adc2_ram_fifo_addr_wr_ce  ; --
1895 
              mux_adc2_ram_fifo_addr_wr_addr  <=   adc2_ram_fifo_addr_wr_addr    ; --
1896 
              mux_adc2_ram_fifo_data_wr_ce    <=   adc2_ram_fifo_data_wr_ce  ; --
1897 
              mux_adc2_ram_fifo_data_wr_data  <=   adc2_ram_fifo_data_wr_data    ; --
1898 
   end if;
1899 
end process;
1900 
 
1901 
 
1902 
ram2_write_address_fifo_pipe: ram_address_fifo_pipe
1903 
        PORT MAP(clk_wr                                                         => clk180_int,
1904 
                                clk180                                                          => clk180_int,
1905 
                                asynch_reset                                            => ram2_ddr2_sys_rst180,
1906 
                                fifo_input_d                                            => mux_adc2_ram_fifo_addr_wr_addr,
1907 
                                fifo_input_wr_en                                        => mux_adc2_ram_fifo_addr_wr_ce,
1908 
                                fifo_pipe_rd_en                                 => ram2_vme_wr_addr_fifo_pipe_rd_en,
1909 
                                sy_clk_wr_fifo_pipe_empty               => open, -- new 14.08.2009
1910 
                                bank_row_last_addr_flag                 => ram2_wr_bank_row_last_addr_flag,
1911 
                                bank_row_addr_conflict_flag     => ram2_wr_bank_row_addr_conflict_flag,
1912 
                                fifo_pipe_burst_valid                   => ram2_wr_addr_fifo_pipe_burst_valid,
1913 
                                fifo_pipe_valid                                 => ram2_vme_wr_addr_fifo_pipe_valid,
1914 
                                fifo_pipe_out_reg                                       =>  ram2_vme_wr_addr_fifo_q,
1915 
                                fifo_pipe_wr_count                              =>  ram2_fifo_pipe_wr_count
1916 
                        );
1917 
 
1918 
 
1919 
 
1920 
ram2_vme_wr_data_fifoH : blk_asy_fifo_1023x16
1921 
        port map(din            => mux_adc2_ram_fifo_data_wr_data(15 downto 0),
1922 
                                wr_en           => mux_adc2_ram_fifo_data_wr_ce,
1923 
                                wr_clk  => clk180_int,
1924 
                                rd_en           => ram2_vme_wr_fifo_rd_en,
1925 
                                rd_clk  => clk180_int,
1926 
                                ainit           => ram2_ddr2_sys_rst180, --ram2_ddr2_sys_rst, mod. 25.10.2006
1927 
                                dout            => ram2_ddr2_user_input_data(15 downto 0), -- daten werden mit clk90 uebernommen
1928 
                                full            => adc2_ram_fifo_data_full,
1929 
                                empty           => open,
1930 
                                wr_count        => ram2_ddr2_wr_data_wr_count,
1931 
                                rd_count        => open
1932 
                        );
1933 
 
1934 
ram2_vme_wr_data_fifoL : blk_asy_fifo_1023x16
1935 
        port map(din            => mux_adc2_ram_fifo_data_wr_data(31 downto 16),
1936 
                                wr_en           => mux_adc2_ram_fifo_data_wr_ce,
1937 
                                wr_clk  => clk180_int,
1938 
                                rd_en           => ram2_vme_wr_fifo_rd_en,
1939 
                                rd_clk  => clk180_int,
1940 
                                ainit           => ram2_ddr2_sys_rst180, --ram2_ddr2_sys_rst, mod. 25.10.2006
1941 
                                dout            => ram2_ddr2_user_input_data(31 downto 16), -- daten werden mit clk90 uebernommen
1942 
                                full            => open,
1943 
                                empty           => open,
1944 
                                wr_count        => open,
1945 
                                rd_count        => open
1946 
                        );
1947 
 
1948 
 
1949 
 
1950 
ram2_ddr2_readwrite_fsm: ddr2_readwrite_fsm
1951 
        PORT MAP(clk180_int                                                             => clk180_int,
1952 
                                clk_int_dcm_lock                                                => clk_int_dcm_lock,
1953 
                                rst180                                                                  => ram2_ddr2_sys_rst180,
1954 
                                wr_bank_row_last_addr_flag                      => ram2_wr_bank_row_last_addr_flag,
1955 
                                wr_bank_row_addr_conflict_flag  => ram2_wr_bank_row_addr_conflict_flag,
1956 
                                wr_addr_fifo_pipe_burst_valid           => ram2_wr_addr_fifo_pipe_burst_valid,
1957 
                                wr_addr_fifo_pipe_valid                         => ram2_vme_wr_addr_fifo_pipe_valid,
1958 
                                wr_addr_fifo_pipe_rd_en                         => ram2_vme_wr_addr_fifo_pipe_rd_en,
1959 
                                wr_data_fifo_rd_en                                      => ram2_vme_wr_fifo_rd_en,
1960 
                                ram_fifo_pipe_wr_count                          => ram2_fifo_pipe_wr_count,
1961 
                                rd_bank_row_last_addr_flag                      => ram2_vme_rd_bank_row_last_addr_flag,
1962 
                                rd_bank_row_addr_conflict_flag  => ram2_vme_rd_bank_row_addr_conflict_flag,
1963 
                                rd_addr_fifo_pipe_burst_valid           => ram2_vme_rd_addr_fifo_pipe_burst_valid,
1964 
                                rd_addr_fifo_pipe_valid                         => ram2_vme_rd_addr_fifo_pipe_valid,
1965 
                                rd_addr_fifo_pipe_rd_en                         => ram2_vme_rd_addr_fifo_pipe_rd_en,
1966 
                                rd_addr_mux_en                                                  => ram2_rd_addr_mux_en,
1967 
                                ddr2_ctrl_command_register                      => ram2_ddr2_command_register,
1968 
                                ddr2_ctrl_burst_done                                    => ram2_ddr2_burst_done,
1969 
                                ddr2_ctrl_cmd_ack                                               => ram2_ddr2_cmd_ack,
1970 
                                ddr2_ctrl_init                                                  => ram2_ddr2_init_done,
1971 
                                ddr2_ctrl_ar_done                                               => ram2_ddr2_autorefresh_done
1972 
                        );
1973 
 
1974 
 
1975 
ram2_infrastructure: infrastructure
1976 
        PORT MAP(reset_in                                               => '0',
1977 
                                clk_int                                         => clk_int,
1978 
                                clk180_int                                      => clk180_int,
1979 
                                clk90_int                                       => clk90_int,
1980 
                                dcm_lock                                                => clk_int_dcm_lock,
1981 
                                rst_calib1                                      => ram2_ddr2_rst_calib1,
1982 
                                ramx_ddr2_delay_sel_val => ramx_ddr2_delay_sel,
1983 
                                delay_sel_val1_val              => ram2_ddr2_delay_sel,
1984 
                                sys_rst_val                                     => ram2_ddr2_sys_rst,
1985 
                                sys_rst90_val                           => ram2_ddr2_sys_rst90,
1986 
                                sys_rst180_val                          => ram2_ddr2_sys_rst180_orig,
1987 
                                sys_rst270_val                          => ram2_ddr2_sys_rst270
1988 
                        );
1989 
 
1990 
        ram2_ddr2_sys_rst180 <= '1' when (ram2_ddr2_sys_rst180_orig='1') else '0';
1991 
 
1992 
        ram2_ddr2_controller_address(24 downto 0)  <=   ram2_vme_wr_addr_fifo_q(24 downto 0)  when  (ram2_rd_addr_mux_en = '0')    else
1993 
                                                        ram2_vme_rd_addr_fifo_q(24 downto 0) ;
1994 
 
1995 
 
1996 
        ram2_controller: controller
1997 
                PORT MAP(clk                                    => clk_int,
1998 
                                        clk180_int                      => clk180_int,
1999 
                                        rst0                                    => ram2_ddr2_sys_rst,
2000 
                                        rst180                          => ram2_ddr2_sys_rst180,
2001 
                                        address                         => ram2_ddr2_controller_address(22 downto 0),
2002 
                                        bank_address            => ram2_ddr2_controller_address(24 downto 23),
2003 
                                        config_register1        => ddr_config_register1,
2004 
                                        config_register2        => ddr_config_register2,
2005 
                                        command_register        => ram2_ddr2_command_register,
2006 
                                        burst_done                      => ram2_ddr2_burst_done,
2007 
                                        ddr_rasb_cntrl          => ram2_ddr2_rasb_cntrl,
2008 
                                        ddr_casb_cntrl          => ram2_ddr2_casb_cntrl,
2009 
                                        ddr_web_cntrl           => ram2_ddr2_web_cntrl,
2010 
                                        ddr_ba_cntrl            => ram2_ddr2_ba_cntrl,
2011 
                                        ddr_address_cntrl       => ram2_ddr2_address_cntrl,
2012 
                                        ddr_cke_cntrl           => ram2_ddr2_cke_cntrl,
2013 
                                        ddr_csb_cntrl           => ram2_ddr2_csb_cntrl,
2014 
                                        ddr_ODT_cntrl           => ram2_ddr2_ODT_cntrl,
2015 
                                        dqs_enable                      => ram2_ddr2_dqs_enable,
2016 
                                        dqs_reset                       => ram2_ddr2_dqs_reset,
2017 
                                        write_enable            => ram2_ddr2_write_enable,
2018 
                                        rst_calib                       => ram2_ddr2_rst_calib1,
2019 
                                        rst_dqs_div_int => ram2_ddr2_rst_dqs_div_int,
2020 
                                        cmd_ack                         => ram2_ddr2_cmd_ack,
2021 
                                        init                                    => ram2_ddr2_init_done,
2022 
                                        ar_done                         => ram2_ddr2_autorefresh_done    -- output
2023 
                                );
2024 
 
2025 
 
2026 
 
2027 
        ram2_ddr2_data_path: ddr2_data_path
2028 
                PORT MAP(user_input_data                => ram2_ddr2_user_input_data,
2029 
                                        clk                                             => clk_int,
2030 
                                        clk180                                  => clk180_int,
2031 
                                        clk90                                           => clk90_int,
2032 
                                        reset                                           => ram2_ddr2_sys_rst,
2033 
                                        reset90                                 => ram2_ddr2_sys_rst90,
2034 
                                        reset180                                        => ram2_ddr2_sys_rst180,
2035 
                                        reset270                                        => ram2_ddr2_sys_rst270,
2036 
                                        write_enable                    => ram2_ddr2_write_enable,
2037 
                                        rst_dqs_div_in                  => ram2_ddr2_rst_dqs_div,
2038 
                                        delay_sel                               => ram2_ddr2_delay_sel,
2039 
                                        dqs_int_delay_in0               => ram2_ddr2_dqs_int_delay_in0,
2040 
                                        dqs_int_delay_in1               => ram2_ddr2_dqs_int_delay_in1,
2041 
                                        dq_in_rising                    => ram2_ddr2_dq_in_rising,
2042 
                                        dq_in_falling                   => ram2_ddr2_dq_in_falling,
2043 
                                        u_data_val                              => ram2_ddr2_user_data_val,
2044 
                                        user_output_data                => ram2_ddr2_user_output_data,
2045 
                                        write_en_val                    => ram2_ddr2_write_en_val,
2046 
                                        write_en_val1                   => ram2_ddr2_write_en_val1,
2047 
                                        reset90_r_val                   => ram2_ddr2_reset90_r,
2048 
                                        data_mask_f                             => ram2_ddr2_data_mask_f,
2049 
                                        data_mask_r                             => ram2_ddr2_data_mask_r,
2050 
                                        write_data_falling      => ram2_ddr2_write_data_falling,
2051 
                                        write_data_rising               => ram2_ddr2_write_data_rising,
2052 
                                        test_fifo_wr_addr               => ram2_test_fifo_wr_addr
2053 
                                );
2054 
 
2055 
 
2056 
        ram2_ddr2_iobs: ddr2_iobs
2057 
                PORT MAP(clk0                                           => clk_int,
2058 
                                        clk180                                  => clk180_int,
2059 
                                        clk90                                           => clk90_int,
2060 
                                        ddr_rasb_cntrl                  => ram2_ddr2_rasb_cntrl,
2061 
                                        ddr_ODT_cntrl                   => ram2_ddr2_ODT_cntrl,
2062 
                                        ddr_casb_cntrl                  => ram2_ddr2_casb_cntrl,
2063 
                                        ddr_web_cntrl                   => ram2_ddr2_web_cntrl,
2064 
                                        ddr_cke_cntrl                   => ram2_ddr2_cke_cntrl,
2065 
                                        ddr_csb_cntrl                   => ram2_ddr2_csb_cntrl,
2066 
                                        ddr_address_cntrl               => ram2_ddr2_address_cntrl,
2067 
                                        ddr_ba_cntrl                    => ram2_ddr2_ba_cntrl,
2068 
                                        rst_dqs_div_int         => ram2_ddr2_rst_dqs_div_int,
2069 
                                        dqs_reset                               => ram2_ddr2_dqs_reset,
2070 
                                        dqs_enable                              => ram2_ddr2_dqs_enable,
2071 
                                        ddr_dqs                                 => ddr2_dqs,
2072 
                                        ddr_dq                                  => ddr2_dq,
2073 
                                        write_data_falling      => ram2_ddr2_write_data_falling,
2074 
                                        write_data_rising               => ram2_ddr2_write_data_rising,
2075 
                                        write_en_val                    => ram2_ddr2_write_en_val,
2076 
                                        write_en_val1                   => ram2_ddr2_write_en_val1,
2077 
                                        reset90_r                               => ram2_ddr2_reset90_r,
2078 
                                        data_mask_f                             => ram2_ddr2_data_mask_f,
2079 
                                        data_mask_r                             => ram2_ddr2_data_mask_r,
2080 
                                        ddr_ODT0                                        => ddr2_ODT0,
2081 
                                        ddr_rasb                                        => ddr2_rasb,
2082 
                                        ddr_casb                                        => ddr2_casb,
2083 
                                        ddr_web                                 => ddr2_web,
2084 
                                        ddr_ba                                  => ddr2_ba,
2085 
                                        ddr_address                             => ddr2_address,
2086 
                                        ddr_cke                                 => ddr2_cke,
2087 
                                        ddr_csb                                 => ddr2_csb,
2088 
                                        rst_dqs_div                             => ram2_ddr2_rst_dqs_div,
2089 
                                        rst_dqs_div_iob         => ddr2_rst_dqs_div_iob,
2090 
                                        dqs_int_delay_in0               => ram2_ddr2_dqs_int_delay_in0,
2091 
                                        dqs_int_delay_in1               => ram2_ddr2_dqs_int_delay_in1,
2092 
                                        dq_in_rising                    => ram2_ddr2_dq_in_rising,
2093 
                                        dq_in_falling                   => ram2_ddr2_dq_in_falling,
2094 
                                        ddr_dm                                  => ddr2_dm
2095 
                                );
2096 
 
2097 
 
2098 
U30 : OBUFT  port map ( I => '0',
2099 
                        T => '1' ,
2100 
                        O => ddr2_dqs_reserve(0));
2101 
U31 : OBUFT  port map ( I => '0',
2102 
                        T => '1' ,
2103 
                        O => ddr2_dqs_reserve(1));
2104 
 
2105 
 
2106 
 
2107 
ddr2_ba2_reserve <= '0' ; -- only to force to use the pad
2108 
 
2109 
 
2110 
-- **************************************************************************************************
2111 
-- VME Prot IOs
2112 
-- **************************************************************************************************
2113 
 
2114 
vme_adc_prot_IOs : process (sys_clk_100, wst_out_en, vme_out_ad_en)
2115 
begin
2116 
-- control in
2117 
        if rising_edge (sys_clk_100) then
2118 
            fpga_sel_ireg                               <=    not i_fpga_sel_l  ;
2119 
            fpga_ds_ireg                                <=    not i_fpga_ds_l  ;
2120 
            fpga_write_ireg                     <=    not i_fpga_write_l  ;
2121 
            fpga_block_ireg                     <=    not i_fpga_block_l  ;
2122 
            fpga_key_reset_ibuf         <=    not i_fpga_key_reset_l  ;-- mod. 25.10.2006
2123 
   end if;
2124 
 
2125 
-- weil short pulse (Übersprecher) am FPGA ADC78 zu sehen waren
2126 
        if rising_edge (sys_clk_100) then
2127 
            fpga_key_reset_delay1     <=    fpga_key_reset_ibuf  ;-- mod. 27.3.2009
2128 
            fpga_key_reset_delay2     <=    fpga_key_reset_delay1  ;-- mod. 27.3.2009
2129 
            fpga_key_reset_degliched  <=    fpga_key_reset_ibuf and fpga_key_reset_delay1 and fpga_key_reset_delay2;-- mod. 27.3.2009
2130 
   end if;
2131 
 
2132 
--control out
2133 
   if (wst_out_en = '0') then                              wst_out_l_oreg  <= 'Z' ;
2134 
            elsif rising_edge(sys_clk_100) then    wst_out_l_oreg  <= not vme_out_wst ;
2135 
   end if;
2136 
 
2137 
-- data in
2138 
        if rising_edge (sys_clk_100) then
2139 
            vme_ad_ireg  <=   io_fpga_ad  ;
2140 
   end if;
2141 
 
2142 
--data out
2143 
   if (vme_out_ad_en = '0') then               io_fpga_ad  <= (others => 'Z') ;
2144 
            elsif rising_edge(sys_clk_100) then    io_fpga_ad  <= vme_ad_oreg ;
2145 
   end if;
2146 
 
2147 
end process;
2148 
 
2149 
 
2150 
vme_synch_logic : process (sys_clk_100)
2151 
begin
2152 
        if rising_edge (sys_clk_100) then
2153 
                vme_adc1_ram_address_counter(24 downto 2)  <= adc1_ram_fifo_addr_wr_addr(24 downto 2) ;
2154 
                vme_adc1_ram_address_counter(1 downto 0)   <= "00" ;
2155 
 
2156 
                vme_adc2_ram_address_counter(24 downto 2)  <= adc2_ram_fifo_addr_wr_addr(24 downto 2);
2157 
                vme_adc2_ram_address_counter(1 downto 0)   <= "00" ;
2158 
   end if;
2159 
end process;
2160 
 
2161 
---------------------------------------------------------------------------------------------------------------
2162 
--      single bit command lines
2163 
---------------------------------------------------------------------------------------------------------------
2164 
        cmd_start_adc_S                                                         <= vme_0x04_reg_S(2);
2165 
        cmd_soft_trigger_S                                                      <= vme_0x04_reg_S(3);
2166 
        cmd_output_select_S                                                     <= vme_0x04_reg_S(7 downto 4);
2167 
        cmd_invert_data_in_S                                                    <= vme_0x04_reg_S(8);
2168 
        cmd_baseline_enable_S                                           <= vme_0x04_reg_S(9);
2169 
        cmd_enableFE1_S                                                         <= vme_0x04_reg_S(10);
2170 
        cmd_enableFE2_S                                                         <= vme_0x04_reg_S(11);
2171 
        cmd_double_CF_S                                                         <= vme_0x04_reg_S(12);
2172 
        cmd_program_params_S                                                    <= vme_0x04_reg_S(13);
2173 
        cmd_bypass_mwd_S                                                                <= vme_0x04_reg_S(14);
2174 
        cmd_bypass_reshape_S                                                    <= vme_0x04_reg_S(15);
2175 
 
2176 
        decay_correction_S                                                      <= vme_0x08_reg_S;
2177 
        reshape_correction_S                                                    <= vme_0x0C_reg_S;
2178 
 
2179 
---------------------------------------------------------------------------------------------------------------
2180 
--      process-parameter registers
2181 
---------------------------------------------------------------------------------------------------------------
2182 
        buffer_size_S                                                                   <=      vme_0x40_reg_S;
2183 
        int_signal_threshold_S                                          <=      vme_0x44_reg_S;                                 -- 15-bit reg
2184 
        mwd_pwr_S                                                                               <=      vme_0x48_reg_S(7 downto 0);      -- 15-bit reg
2185 
        cf_pwr_S                                                                                        <=      vme_0x4c_reg_S(7 downto 0);      -- 15-bit reg
2186 
        cf_integral_pwr_S                                                               <=      vme_0x50_reg_S(7 downto 0);      -- 15-bit reg
2187 
        baseline_inhibit_cnt_S                                          <=      vme_0x54_reg_S(7 downto 0);      -- 15-bit reg
2188 
        event_inhibit_cnt_S                                                     <=      vme_0x58_reg_S(7 downto 0);      -- 15-bit reg
2189 
        baseline_pwr_S                                                                  <=      vme_0x5C_reg_S(7 downto 0);      -- 15-bit reg
2190 
 
2191 
---------------------------------------------------------------------------------------------------------------
2192 
        vme_0x80_feedback_reg_S(0)                                       <= FE1_running_S;
2193 
        vme_0x80_feedback_reg_S(1)                                      <= FE1_enable_S;
2194 
        vme_0x80_feedback_reg_S(2)                                      <= FE2_running_S;
2195 
        vme_0x80_feedback_reg_S(3)                                      <= FE2_enable_S;
2196 
        vme_0x80_feedback_reg_S(4)                                      <= cmd_invert_data_in_S;
2197 
        vme_0x80_feedback_reg_S(5)                                      <= cmd_double_CF_S;
2198 
        vme_0x80_feedback_reg_S(31 downto 6)    <=      (others => '0');
2199 
---------------------------------------------------------------------------------------------------------------
2200 
        vme_0x84_feedback_reg_S                                         <=      feedback_bus0_S;
2201 
---------------------------------------------------------------------------------------------------------------
2202 
        vme_0x88_feedback_reg_S                                         <=      feedback_bus1_S;
2203 
---------------------------------------------------------------------------------------------------------------
2204 
        vme_0x8C_feedback_reg_S                                         <=      feedback_bus2_S;
2205 
---------------------------------------------------------------------------------------------------------------
2206 
        vme_0x90_feedback_reg_S                                         <=      feedback_bus3_S;
2207 
---------------------------------------------------------------------------------------------------------------
2208 
        vme_0x94_feedback_reg_S                                         <=      feedback_bus4_S;
2209 
---------------------------------------------------------------------------------------------------------------
2210 
        vme_0x98_feedback_reg_S                                         <=      feedback_bus5_S;
2211 
---------------------------------------------------------------------------------------------------------------
2212 
        vme_0x9C_feedback_reg_S                                         <=      feedback_bus6_S;        --(others => '0');
2213 
 
2214 
        Inst_vme_intf: vme_intf
2215 
                PORT MAP(MHZ100                                                                                 => sys_clk_100,
2216 
                                        fpga_sel                                                                                        => fpga_sel_ireg,
2217 
                                        fpga_ds                                                                                 => fpga_ds_ireg,
2218 
                                        fpga_write                                                                              => fpga_write_ireg,
2219 
                                        fpga_block                                                                              => fpga_block_ireg,
2220 
                                        fpga_reset_ibuf                                                         => new_fpga_reset_ibuf, --fpga_reset_ibuf, mod 25.10.2006
2221 
                                        fpga_key_reset_ibuf                                                     => fpga_key_reset_degliched,
2222 
                                        wst_out_en                                                                              => wst_out_en,
2223 
                                        vme_out_wst_oreg                                                                => vme_out_wst,
2224 
                                        vme_out_ad_en                                                                   => vme_out_ad_en,
2225 
                                        VME_OUT_AD                                                                              => vme_ad_oreg,
2226 
                                        VME_IN_AD                                                                               => vme_ad_ireg,
2227 
 
2228 
                                        event_config_reg                                                                => vme_event_config_reg_S(31 downto 0),
2229 
                                        vme_end_address_threshold_reg                           => vme_0x04_reg_S(23 downto 2),
2230 
 
2231 
 
2232 
                                        vme_pretrigger_delay_reg                                        => vme_0x08_reg_S(31 downto 16),
2233 
                                        vme_trigger_gate_active_window_reg              => vme_0x08_reg_S(15 downto 0),
2234 
                                        vme_buffer_copy_start_addr_reg                  => vme_0x0C_reg_S(15 downto 0),
2235 
                                        vme_buffer_copy_length_reg                                      => vme_0x0C_reg_S(31 downto 16),
2236 
                                        adc1_ram_address_counter                                        => vme_adc1_ram_address_counter(24 downto 0),
2237 
                                        adc2_ram_address_counter                                        => vme_adc2_ram_address_counter(24 downto 0),
2238 
                                        adc1_last_buffer_ram_address_counter    => adc1_last_buffer_adc_ram_fifo_wr_addr(24 downto 0),
2239 
                                        adc2_last_buffer_ram_address_counter    => adc2_last_buffer_adc_ram_fifo_wr_addr(24 downto 0),
2240 
                                        actual_adc1_data_in                                                     => vme_0x20_reg_S(31 downto 16),
2241 
                                        actual_adc2_data_in                                                     => vme_0x20_reg_S(15 downto 0),
2242 
                                        test_in                                                                                 => temp_24, --vme_test_in,
2243 
                                        test2_in                                                                                        => temp_28, --vme_test2_in,
2244 
                                        trigger_flag_latch_cnt_register                 => open,
2245 
                                        adc1_trigger_setup                                                      => vme_0x30_reg_S(31 downto 0),
2246 
                                        adc1_trigger_threshold                                          => vme_0x34_reg_S(26 downto 0),
2247 
                                        adc2_trigger_setup                                                      => vme_0x38_reg_S(31 downto 0),
2248 
                                        adc2_trigger_threshold                                          => vme_0x3C_reg_S(26 downto 0),
2249 
                                        vme_0x40_reg                                                                    => vme_0x40_reg_S(31 downto 0),
2250 
                                        vme_0x44_reg                                                                    => vme_0x44_reg_S(15 downto 0),
2251 
                                        vme_0x48_reg                                                                    => vme_0x48_reg_S(15 downto 0),
2252 
                                        vme_0x4C_reg                                                                    => vme_0x4C_reg_S(15 downto 0),
2253 
                                        vme_0x50_reg                                                                    => vme_0x50_reg_S(15 downto 0),
2254 
                                        vme_0x54_reg                                                                    => vme_0x54_reg_S(15 downto 0),
2255 
                                        vme_0x58_reg                                                                    => vme_0x58_reg_S(15 downto 0),
2256 
                                        vme_0x5C_reg                                                                    => vme_0x5C_reg_S(15 downto 0),
2257 
                                        vme_0x60_reg                                                                    => vme_0x60_reg_S(31 downto 0),
2258 
                                        vme_0x64_reg                                                                    => vme_0x64_reg_S(31 downto 0),
2259 
                                        vme_0x68_reg                                                                    => vme_0x68_reg_S(7 downto 0),
2260 
                                        vme_0x80_feedback_reg                                           => vme_0x80_feedback_reg_S,
2261 
                                        vme_0x84_feedback_reg                                           => vme_0x84_feedback_reg_S,
2262 
                                        vme_0x88_feedback_reg                                           => vme_0x88_feedback_reg_S,
2263 
                                        vme_0x8C_feedback_reg                                           => vme_0x8C_feedback_reg_S,
2264 
                                        vme_0x90_feedback_reg                                           => vme_0x90_feedback_reg_S,
2265 
                                        vme_0x94_feedback_reg                                           => vme_0x94_feedback_reg_S,
2266 
                                        vme_0x98_feedback_reg                                           => vme_0x98_feedback_reg_S,
2267 
                                        vme_0x9C_feedback_reg                                           => vme_0x9C_feedback_reg_S,
2268 
                                        bank1_rd_data                                                                   => ram1_rd_data_fifo_q,
2269 
                                        bank2_rd_data                                                                   => ram2_rd_data_fifo_q,
2270 
                                        vme_b1_addr_ld                                                                  => vme_b1_addr_ld,
2271 
                                        vme_b2_addr_ld                                                                  => vme_b2_addr_ld,
2272 
                                        vme_b1_ff_empty                                                         => ram1_vme_rd_data_fifo_empty,
2273 
                                        vme_b2_ff_empty                                                         => ram2_vme_rd_data_fifo_empty,
2274 
                                        vme_b1_rd                                                                               => vme_b1_rd,
2275 
                                        vme_b2_rd                                                                               => vme_b2_rd,
2276 
                                        vme_b1_rd_cmd                                                                   => ram1_vme_rd_fifo_rd_en,
2277 
                                        vme_b2_rd_cmd                                                                   => ram2_vme_rd_fifo_rd_en,
2278 
                                        vme_bx_rd_dma                                                                   => ramx_vme_bx_rd_dma,
2279 
                                        vme_bx_rd_cycle                                                         => ramx_vme_bx_rd_cycle,
2280 
                                        vme_bx_rd_request                                                               => ramx_vme_bx_rd_request,
2281 
 
2282 
                                        vme_b1_wr_cycle                                                         => vme_ram1_wr_cycle,
2283 
                                        vme_b2_wr_cycle                                                         => vme_ram2_wr_cycle,
2284 
                                        vme_b1_wr_cmd_pulse                                                     => vme_ram1_wr_cmd_pulse,
2285 
                                        vme_b2_wr_cmd_pulse                                                     => vme_ram2_wr_cmd_pulse,
2286 
                                        vme_adc1_event_dir_rd_ce                                        => open,
2287 
                                        vme_adc2_event_dir_rd_ce                                        => open,
2288 
                                        vme_adcx_event_dir_addr_reg                             => open,
2289 
                                        vme_adc1_event_dir_data                                         => X"00000000",
2290 
                                        vme_adc2_event_dir_data                                         => X"00000000"
2291 
                                );
2292 
 
2293 
end Behavioral;

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