Subversion Repositories pulse_processing_algorithm

-----------------------------------------------------------------------------------------------

--

--    Copyright (C) 2011 Peter Lemmens, PANDA collaboration

--              p.j.j.lemmens@rug.nl

--    http://www-panda.gsi.de

--

--    As a reference, please use:

--    E. Guliyev, M. Kavatsyuk, P.J.J. Lemmens, G. Tambave, H. Loehner,

--    "VHDL Implementation of Feature-Extraction Algorithm for the PANDA Electromagnetic Calorimeter"

--    Nuclear Inst. and Methods in Physics Research, A ....

--

--

--    This program is free software; you can redistribute it and/or modify

--    it under the terms of the GNU Lesser General Public License as published by

--    the Free Software Foundation; either version 3 of the License, or

--    (at your option) any later version.

--

--    This program is distributed in the hope that it will be useful,

--    but WITHOUT ANY WARRANTY; without even the implied warranty of

--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--    GNU Lesser General Public License for more details.

--

--    You should have received a copy of the GNU General Public License

--    along with this program; if not, write to the Free Software

--    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111 USA

--

-----------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------

-- Company:                     KVI (Kernfysisch Versneller Instituut  -- Groningen, The Netherlands    

-- Author:                      P.J.J. Lemmens

-- Design Name: Feature Extraction

-- Module Name: window_subtractor_programmable.vhd

-- Description: Subtracts a previous sample 'X(n-M) from the current sample 'X(n)' 

--                                              or vice-versa.

--                                              

-----------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

entity window_subtractor_programmable is

        generic(        FORWARD         :       boolean;                        -- if TRUE then (X(n) - X(n-M)) else (X(n-M) - X(n))

                                MAX_MWD_PWR     :       natural);               --      Mmax= 2^MAX_MWD_PWR; sets memory-size used for buffer

        Port (rst                               : in  STD_LOGIC;

                        clk                             : in  STD_LOGIC;

                        enable                  : IN    STD_LOGIC ;

                        program                 : in  STD_LOGIC;

                        window_pwr_in   : in  STD_LOGIC_VECTOR(7 downto 0);

                        data_in                 : in  STD_LOGIC_VECTOR;

                        data_out                        : out STD_LOGIC_VECTOR

                        );

end window_subtractor_programmable;

architecture Behavioral of window_subtractor_programmable is

        constant        WIDTH           : natural := data_in'length;

        component progdelay_pipeline

                generic (RAM_SIZE_PWR   : natural       := 1;

                                        FLEX_RAM_STYLE  : string                := "distributed");

                Port (clk                       : in  STD_LOGIC;

                                rst                     : in  STD_LOGIC;

                                enable          : in  STD_LOGIC;

                                program         : in  STD_LOGIC;

                                delay_in                : in    STD_LOGIC_VECTOR;

                                data_in         : in    STD_LOGIC_VECTOR;

                                data_out                : out   STD_LOGIC_VECTOR;

                                data_valid      : out   std_logic

                        );

        end component;

        component SISO_sub_a

                generic(        A_MINUS_B       :       boolean

                                        );

                port (dataa             : IN STD_LOGIC_VECTOR;

                                datab           : IN STD_LOGIC_VECTOR;

                                result  : OUT STD_LOGIC_VECTOR

                                );

        end component;

        component dff_re

                port (rst                       : in  STD_LOGIC;

                                clk                     : in    STD_LOGIC;

                                enable          : IN STD_LOGIC ;

                                data_valid      : out   STD_LOGIC;

                                d                               : in    STD_LOGIC_VECTOR;

                                q                               : out   STD_LOGIC_VECTOR

                                );

        end component;

   signal rst_S                 : std_logic := '1';

        signal clk_S                    : std_logic;

        signal enable_S         : std_logic := '1';

        signal program_S                : std_logic := '0';

        signal window_size_S    : std_logic_vector(7 downto 0)                   := (others => '0');

        signal data_in_S                : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal del_data_S               : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal sub_result_S     : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        signal data_out_S               : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');

        begin

                sub_delay_pipe : progdelay_pipeline

                        generic map(RAM_SIZE_PWR        =>      MAX_MWD_PWR,

                                                        FLEX_RAM_STYLE  => "distributed"

                                                )

                        PORT MAP(rst                                    => rst_S,

                                                clk                                     => clk_S,

                                                enable                          => enable_S,

                                                program                         => program_S,

                                                delay_in                                => window_size_S,

                                                data_in                         => data_in_S,

                                                data_out                        => del_data_S,

                                                data_valid                      => open

                                        );

                async_sub : SISO_sub_a

                        GENERIC MAP(A_MINUS_B   => FORWARD)

                        PORT MAP(dataa                          => data_in_S,

                                                datab                           => del_data_S,

                                                result                  => sub_result_S

                                        );

                output_reg : dff_re

                        PORT MAP(rst                                    => rst_S,

                                                clk                                     =>      clk_S,

                                                enable                          => enable_S,

                                                data_valid                      => open,

                                                d                                               =>      sub_result_S,

                                                q                                               =>      data_out_S

                                        );

                rst_S                                   <= rst;

                clk_S                                   <= clk;

                enable_S                                <= enable;

                program_S                       <= program;

                window_size_S           <= conv_std_logic_vector((2**conv_integer(unsigned(window_pwr_in))), 8);

                data_in_S                       <= data_in;

                data_out                                <= data_out_S;

end Behavioral;