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[/] [pwm_with_dithering/] [trunk/] [Implementation_results.txt] - Blame information for rev 5

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Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
 
 
For minimal implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              17  out of  126800     0%
 Number of Slice LUTs:                   36  out of  63400     0%
    Number used as Logic:                36  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     36
   Number with an unused Flip Flop:      19  out of     36    52%
   Number with an unused LUT:             0  out of     36     0%
   Number of fully used LUT-FF pairs:    17  out of     36    47%
   Number of unique control sets:         1
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)
   Minimum input arrival time before clock: 3.646ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     3.387ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.287ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              43  out of  126800     0%
 Number of Slice LUTs:                   49  out of  63400     0%
    Number used as Logic:                49  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     50
   Number with an unused Flip Flop:       7  out of     50    14%
   Number with an unused LUT:             1  out of     50     2%
   Number of fully used LUT-FF pairs:    42  out of     50    84%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)
   Minimum input arrival time before clock: 1.606ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.027ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.209ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For inequality based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              17  out of  126800     0%
 Number of Slice LUTs:                   43  out of  63400     0%
    Number used as Logic:                43  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     44
   Number with an unused Flip Flop:      27  out of     44    61%
   Number with an unused LUT:             1  out of     44     2%
   Number of fully used LUT-FF pairs:    16  out of     44    36%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
---------------
   Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)
   Minimum input arrival time before clock: 4.529ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     4.390ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.287ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For register based implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              30  out of  126800     0%
 Number of Slice LUTs:                   35  out of  63400     0%
    Number used as Logic:                35  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     36
   Number with an unused Flip Flop:       6  out of     36    16%
   Number with an unused LUT:             1  out of     36     2%
   Number of fully used LUT-FF pairs:    29  out of     36    80%
   Number of unique control sets:         2
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
   Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)
   Minimum input arrival time before clock: 2.410ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.436ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.212ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
 
 
For small pipelined implementation:
 
Device utilization summary:
---------------------------
 
Selected Device : 7a100tcsg324-2
 
Slice Logic Utilization:
 Number of Slice Registers:              31  out of  126800     0%
 Number of Slice LUTs:                   40  out of  63400     0%
    Number used as Logic:                40  out of  63400     0%
 
Slice Logic Distribution:
 Number of LUT Flip Flop pairs used:     41
   Number with an unused Flip Flop:      10  out of     41    24%
   Number with an unused LUT:             1  out of     41     2%
   Number of fully used LUT-FF pairs:    30  out of     41    73%
   Number of unique control sets:         3
 
IO Utilization:
 Number of IOs:                          18
 Number of bonded IOBs:                  18  out of    210     8%
 
Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
 
Timing Summary: (after synthesis)
   Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)
   Minimum input arrival time before clock: 1.868ns
   Maximum output required time after clock: 0.742ns
   Maximum combinational path delay: No path found
 
After place and route:
----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
                                            |             |    Slack   | Achievable | Errors |    Score
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     2.083ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.201ns|            |       0|           0
----------------------------------------------------------------------------------------------------------

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Subversion Repositories pwm_with_dithering

[/] [pwm_with_dithering/] [trunk/] [Implementation_results.txt] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	TeroS	`Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.`
2
3
4			`For minimal implementation:`
5
6			`Device utilization summary:`
7			`---------------------------`
8
9			`Selected Device : 7a100tcsg324-2`
10
11			`Slice Logic Utilization:`
12			`Number of Slice Registers: 17 out of 126800 0%`
13			`Number of Slice LUTs: 36 out of 63400 0%`
14			`Number used as Logic: 36 out of 63400 0%`
15
16			`Slice Logic Distribution:`
17			`Number of LUT Flip Flop pairs used: 36`
18			`Number with an unused Flip Flop: 19 out of 36 52%`
19			`Number with an unused LUT: 0 out of 36 0%`
20			`Number of fully used LUT-FF pairs: 17 out of 36 47%`
21			`Number of unique control sets: 1`
22
23			`IO Utilization:`
24			`Number of IOs: 18`
25			`Number of bonded IOBs: 18 out of 210 8%`
26
27			`Specific Feature Utilization:`
28			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
29
30			`Timing Summary: (after synthesis)`
31			`---------------`
32			`Minimum period: 3.854ns (Maximum Frequency: 259.491MHz)`
33			`Minimum input arrival time before clock: 3.646ns`
34			`Maximum output required time after clock: 0.742ns`
35			`Maximum combinational path delay: No path found`
36
37			`After place and route:`
38			`----------------------------------------------------------------------------------------------------------`
39			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
40			`\| \| Slack \| Achievable \| Errors \| Score`
41			`----------------------------------------------------------------------------------------------------------`
42			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 3.387ns\| N/A\| 0`
43			`_BUFGP \| HOLD \| 0.287ns\| \| 0\| 0`
44			`----------------------------------------------------------------------------------------------------------`
45
46
47			`For pipelined implementation:`
48
49			`Device utilization summary:`
50			`---------------------------`
51
52			`Selected Device : 7a100tcsg324-2`
53
54			`Slice Logic Utilization:`
55			`Number of Slice Registers: 43 out of 126800 0%`
56			`Number of Slice LUTs: 49 out of 63400 0%`
57			`Number used as Logic: 49 out of 63400 0%`
58
59			`Slice Logic Distribution:`
60			`Number of LUT Flip Flop pairs used: 50`
61			`Number with an unused Flip Flop: 7 out of 50 14%`
62			`Number with an unused LUT: 1 out of 50 2%`
63			`Number of fully used LUT-FF pairs: 42 out of 50 84%`
64			`Number of unique control sets: 2`
65
66			`IO Utilization:`
67			`Number of IOs: 18`
68			`Number of bonded IOBs: 18 out of 210 8%`
69
70			`Specific Feature Utilization:`
71			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
72
73			`Timing Summary: (after synthesis)`
74			`---------------`
75			`Minimum period: 2.069ns (Maximum Frequency: 483.255MHz)`
76			`Minimum input arrival time before clock: 1.606ns`
77			`Maximum output required time after clock: 0.742ns`
78			`Maximum combinational path delay: No path found`
79
80			`After place and route:`
81			`----------------------------------------------------------------------------------------------------------`
82			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
83			`\| \| Slack \| Achievable \| Errors \| Score`
84			`----------------------------------------------------------------------------------------------------------`
85			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.027ns\| N/A\| 0`
86			`_BUFGP \| HOLD \| 0.209ns\| \| 0\| 0`
87			`----------------------------------------------------------------------------------------------------------`
88
89
90			`For inequality based implementation:`
91
92			`Device utilization summary:`
93			`---------------------------`
94
95			`Selected Device : 7a100tcsg324-2`
96
97			`Slice Logic Utilization:`
98			`Number of Slice Registers: 17 out of 126800 0%`
99			`Number of Slice LUTs: 43 out of 63400 0%`
100			`Number used as Logic: 43 out of 63400 0%`
101
102			`Slice Logic Distribution:`
103			`Number of LUT Flip Flop pairs used: 44`
104			`Number with an unused Flip Flop: 27 out of 44 61%`
105			`Number with an unused LUT: 1 out of 44 2%`
106			`Number of fully used LUT-FF pairs: 16 out of 44 36%`
107			`Number of unique control sets: 2`
108
109			`IO Utilization:`
110			`Number of IOs: 18`
111			`Number of bonded IOBs: 18 out of 210 8%`
112
113			`Specific Feature Utilization:`
114			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
115
116			`Timing Summary: (after synthesis)`
117			`---------------`
118			`Minimum period: 4.737ns (Maximum Frequency: 211.113MHz)`
119			`Minimum input arrival time before clock: 4.529ns`
120			`Maximum output required time after clock: 0.742ns`
121			`Maximum combinational path delay: No path found`
122
123			`After place and route:`
124			`----------------------------------------------------------------------------------------------------------`
125			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
126			`\| \| Slack \| Achievable \| Errors \| Score`
127			`----------------------------------------------------------------------------------------------------------`
128			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 4.390ns\| N/A\| 0`
129			`_BUFGP \| HOLD \| 0.287ns\| \| 0\| 0`
130			`----------------------------------------------------------------------------------------------------------`
131
132
133			`For register based implementation:`
134
135			`Device utilization summary:`
136			`---------------------------`
137
138			`Selected Device : 7a100tcsg324-2`
139
140			`Slice Logic Utilization:`
141			`Number of Slice Registers: 30 out of 126800 0%`
142			`Number of Slice LUTs: 35 out of 63400 0%`
143			`Number used as Logic: 35 out of 63400 0%`
144
145			`Slice Logic Distribution:`
146			`Number of LUT Flip Flop pairs used: 36`
147			`Number with an unused Flip Flop: 6 out of 36 16%`
148			`Number with an unused LUT: 1 out of 36 2%`
149			`Number of fully used LUT-FF pairs: 29 out of 36 80%`
150			`Number of unique control sets: 2`
151
152			`IO Utilization:`
153			`Number of IOs: 18`
154			`Number of bonded IOBs: 18 out of 210 8%`
155
156			`Specific Feature Utilization:`
157			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
158
159			`Timing Summary: (after synthesis)`
160			`Minimum period: 2.618ns (Maximum Frequency: 381.912MHz)`
161			`Minimum input arrival time before clock: 2.410ns`
162			`Maximum output required time after clock: 0.742ns`
163			`Maximum combinational path delay: No path found`
164
165			`After place and route:`
166			`----------------------------------------------------------------------------------------------------------`
167			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
168			`\| \| Slack \| Achievable \| Errors \| Score`
169			`----------------------------------------------------------------------------------------------------------`
170			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.436ns\| N/A\| 0`
171			`_BUFGP \| HOLD \| 0.212ns\| \| 0\| 0`
172			`----------------------------------------------------------------------------------------------------------`
173
174
175			`For small pipelined implementation:`
176
177			`Device utilization summary:`
178			`---------------------------`
179
180			`Selected Device : 7a100tcsg324-2`
181
182			`Slice Logic Utilization:`
183			`Number of Slice Registers: 31 out of 126800 0%`
184			`Number of Slice LUTs: 40 out of 63400 0%`
185			`Number used as Logic: 40 out of 63400 0%`
186
187			`Slice Logic Distribution:`
188			`Number of LUT Flip Flop pairs used: 41`
189			`Number with an unused Flip Flop: 10 out of 41 24%`
190			`Number with an unused LUT: 1 out of 41 2%`
191			`Number of fully used LUT-FF pairs: 30 out of 41 73%`
192			`Number of unique control sets: 3`
193
194			`IO Utilization:`
195			`Number of IOs: 18`
196			`Number of bonded IOBs: 18 out of 210 8%`
197
198			`Specific Feature Utilization:`
199			`Number of BUFG/BUFGCTRLs: 1 out of 32 3%`
200
201			`Timing Summary: (after synthesis)`
202			`Minimum period: 2.286ns (Maximum Frequency: 437.350MHz)`
203			`Minimum input arrival time before clock: 1.868ns`
204			`Maximum output required time after clock: 0.742ns`
205			`Maximum combinational path delay: No path found`
206
207			`After place and route:`
208			`----------------------------------------------------------------------------------------------------------`
209			`Constraint \| Check \| Worst Case \| Best Case \| Timing \| Timing`
210			`\| \| Slack \| Achievable \| Errors \| Score`
211			`----------------------------------------------------------------------------------------------------------`
212			`Autotimespec constraint for clock net clk \| SETUP \| N/A\| 2.083ns\| N/A\| 0`
213			`_BUFGP \| HOLD \| 0.201ns\| \| 0\| 0`
214			`----------------------------------------------------------------------------------------------------------`