Subversion Repositories pwm_with_dithering

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-- Company:              Aboa Space Research Oy (ASRO)

-- Engineer:             Tero Säntti

-- 

-- Create Date:    16:41:42 02/04/2021 

-- Design Name:          PWM verifier

-- Module Name:    pseudo_ADC - Behavioral 

-- Target Devices: None / Simulation ONLY

-- Tool versions:  None / non-specific

-- Description:          Show ADC-like conversion from real to digital.

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.math_real.all;

entity pseudo_ADC is

    Generic (

                                bits : integer :=16;

                                supply_voltage : real:=3.3

                                );

    Port ( v_in : in  real;

                          digital_out : out std_logic_vector(bits-1 downto 0)

                          );

end pseudo_ADC;

architecture Behavioral of pseudo_ADC is

signal v_internal:real:=0.0;

signal scale:real:=(2.0 ** bits);

signal max:real:=(2.0 ** bits) - 1.0;

begin

ADC:process(v_in)

variable value:real;

begin

        value := scale*v_in/supply_voltage;

        if value > max then value:= max; end if;

        digital_out <= STD_LOGIC_VECTOR(to_unsigned(natural(value),bits));

end process;

end Behavioral;