Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////

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//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

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//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

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//////////////////////////////////////////////////////////////////////

module

  PCIe_debug

  (

    PCIe_debug_if dbg_bus,

    input [31:0] h0,

    input [31:0] h1,

    input [31:0] h2,

    input [31:0] h3,

    input enable,

    input reset,

    input clk

  );

  // --------------------------------------------------------------------

  //

  always_ff @(posedge clk)

  begin

    dbg_bus.h0_r      <= h0;

    dbg_bus.h1_r      <= h1;

    dbg_bus.h2_r      <= h2;

    dbg_bus.h3_r      <= h3;

    dbg_bus.enable_r  <= enable;

  end

  // --------------------------------------------------------------------

  //

  always_ff @(posedge clk)

    if(dbg_bus.enable_r)

    begin

      dbg_bus.tlp_fmt     <= dbg_bus.h0_r[31:29];

      dbg_bus.tlp_type    <= dbg_bus.h0_r[28:24];

      dbg_bus.tlp_tc      <= dbg_bus.h0_r[22:20];

      dbg_bus.tlp_th      <= dbg_bus.h0_r[16];

      dbg_bus.tlp_td      <= dbg_bus.h0_r[15];

      dbg_bus.tlp_ep      <= dbg_bus.h0_r[14];

      dbg_bus.tlp_attr    <= {dbg_bus.h0_r[18], dbg_bus.h0_r[13:12]};

      dbg_bus.tlp_at      <= dbg_bus.h0_r[11:10];

      dbg_bus.tlp_length  <= dbg_bus.h0_r[9:0];

    end

  // --------------------------------------------------------------------

  //

  assign dbg_bus.tlp_is_3dw   = ~dbg_bus.h0_r[29];

  assign dbg_bus.tlp_is_4dw   = dbg_bus.h0_r[29];

  assign dbg_bus.tlp_address  = dbg_bus.tlp_is_4dw

                              ? {dbg_bus.h2_r,  dbg_bus.h3_r}

                              : {32'h0,         dbg_bus.h2_r};

// --------------------------------------------------------------------

//

endmodule