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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  riffa_chnl_rx_fsm

  (

    input   rx,

    input   rx_data_valid,

    input   rx_ready,

    output  rx_ack,

    output  rx_done,

    input   reset,

    input   clk

  );

  //---------------------------------------------------

  //  state machine binary definitions

  enum reg [4:0]

    {

      IDLE    = 5'b0_0001,

      ACK     = 5'b0_0010,

      RX      = 5'b0_0100,

      PENDING = 5'b0_1000,

      ERROR   = 5'b1_0000

    } state, next_state;

  //---------------------------------------------------

  //  state machine flop

  always_ff @(posedge clk)

    if(reset)

      state <= IDLE;

    else

      state <= next_state;

  //---------------------------------------------------

  //  state machine

  always_comb

    case(state)

      IDLE:     if(rx)

                  next_state <= ACK;

                else

                  next_state <= IDLE;

      // ACK:      next_state <= RX;

      ACK:      if(rx_ready)

                  next_state <= RX;

                else

                  next_state <= ACK;

      RX:       if(rx)

                  next_state <= RX;

                else if(rx_data_valid)

                  next_state <= PENDING;

                else

                  next_state <= IDLE;

      PENDING:  if(rx_data_valid)

                  next_state <= PENDING;

                else

                  next_state <= IDLE;

      ERROR:    next_state <= IDLE;

      default:  next_state <= ERROR;

    endcase

  // --------------------------------------------------------------------

  //

  assign rx_ack = (state == ACK);

  assign rx_done = (state != IDLE) & (next_state == IDLE);

// --------------------------------------------------------------------

//

endmodule