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qaztronic |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module
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riffa_chnl_tester
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#(
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C_PCI_DATA_WIDTH // Settings from Vivado IP Generator
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)
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(
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riffa_chnl_if chnl_bus,
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input clk, // must be same clock domain as rx_clk & tx_clk
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input reset // must be same clock domain as rx_clk & tx_clk
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);
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// --------------------------------------------------------------------
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//
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chnl_tester #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
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chnl_tester_i
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(
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.CLK(clk),
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.RST(reset), // riffa_reset includes riffa_endpoint resets
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// Rx interface
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.CHNL_RX_CLK(chnl_bus.rx_clk),
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.CHNL_RX(chnl_bus.rx),
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.CHNL_RX_ACK(chnl_bus.rx_ack),
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.CHNL_RX_LAST(chnl_bus.rx_last),
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.CHNL_RX_LEN(chnl_bus.rx_len),
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.CHNL_RX_OFF(chnl_bus.rx_off),
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.CHNL_RX_DATA(chnl_bus.rx_data),
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.CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
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.CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
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// Tx interface
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.CHNL_TX_CLK(chnl_bus.tx_clk),
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.CHNL_TX(chnl_bus.tx),
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.CHNL_TX_ACK(chnl_bus.tx_ack),
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.CHNL_TX_LAST(chnl_bus.tx_last),
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.CHNL_TX_LEN(chnl_bus.tx_len),
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.CHNL_TX_OFF(chnl_bus.tx_off),
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.CHNL_TX_DATA(chnl_bus.tx_data),
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.CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
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.CHNL_TX_DATA_REN(chnl_bus.tx_data_ren)
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);
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// --------------------------------------------------------------------
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//
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endmodule
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