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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  riffa_rx_to_axis

  #(

    N // RIFFA bus width in bytes

  )

  (

    axis_if       axis_out,

    riffa_chnl_if chnl_bus,

    input         rx_ready,

    output        rx_done,

    output [30:0] rx_index,

    output        rx_last,

    output [31:0] rx_len,

    output [30:0] rx_off,

    input         clk,

    input         reset

  );

  // --------------------------------------------------------------------

  //

  wire rd_empty;

  wire [(8*N)-1:0] rd_data;

  wire rd_en = axis_out.tvalid & axis_out.tready;

  riffa_chn_rx #(.N(N))

    riffa_chn_rx_i(.*);

  // --------------------------------------------------------------------

  //

  assign chnl_bus.rx_clk    = clk;

  assign chnl_bus.rx_reset  = reset;

  assign axis_out.tvalid    = ~rd_empty;

  assign axis_out.tdata     = rd_data;

// --------------------------------------------------------------------

//

endmodule